Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform |
| 3 | * driver source file |
| 4 | * |
| 5 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 and |
| 9 | * only version 2 as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/mmc/host.h> |
| 20 | #include <linux/mmc/card.h> |
| 21 | #include <linux/mmc/sdio_func.h> |
| 22 | #include <linux/gfp.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/of_gpio.h> |
| 25 | #include <linux/regulator/consumer.h> |
| 26 | #include <linux/types.h> |
| 27 | #include <linux/input.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/wait.h> |
| 30 | |
| 31 | #include "sdhci-pltfm.h" |
| 32 | |
| 33 | #define CORE_HC_MODE 0x78 |
| 34 | #define HC_MODE_EN 0x1 |
| 35 | |
| 36 | #define CORE_POWER 0x0 |
| 37 | #define CORE_SW_RST (1 << 7) |
| 38 | |
| 39 | #define CORE_PWRCTL_STATUS 0xDC |
| 40 | #define CORE_PWRCTL_MASK 0xE0 |
| 41 | #define CORE_PWRCTL_CLEAR 0xE4 |
| 42 | #define CORE_PWRCTL_CTL 0xE8 |
| 43 | |
| 44 | #define CORE_PWRCTL_BUS_OFF 0x01 |
| 45 | #define CORE_PWRCTL_BUS_ON (1 << 1) |
| 46 | #define CORE_PWRCTL_IO_LOW (1 << 2) |
| 47 | #define CORE_PWRCTL_IO_HIGH (1 << 3) |
| 48 | |
| 49 | #define CORE_PWRCTL_BUS_SUCCESS 0x01 |
| 50 | #define CORE_PWRCTL_BUS_FAIL (1 << 1) |
| 51 | #define CORE_PWRCTL_IO_SUCCESS (1 << 2) |
| 52 | #define CORE_PWRCTL_IO_FAIL (1 << 3) |
| 53 | |
| 54 | #define INT_MASK 0xF |
| 55 | |
| 56 | /* This structure keeps information per regulator */ |
| 57 | struct sdhci_msm_reg_data { |
| 58 | /* voltage regulator handle */ |
| 59 | struct regulator *reg; |
| 60 | /* regulator name */ |
| 61 | const char *name; |
| 62 | /* voltage level to be set */ |
| 63 | u32 low_vol_level; |
| 64 | u32 high_vol_level; |
| 65 | /* Load values for low power and high power mode */ |
| 66 | u32 lpm_uA; |
| 67 | u32 hpm_uA; |
| 68 | |
| 69 | /* is this regulator enabled? */ |
| 70 | bool is_enabled; |
| 71 | /* is this regulator needs to be always on? */ |
| 72 | bool is_always_on; |
| 73 | /* is low power mode setting required for this regulator? */ |
| 74 | bool lpm_sup; |
| 75 | bool set_voltage_sup; |
| 76 | }; |
| 77 | |
| 78 | /* |
| 79 | * This structure keeps information for all the |
| 80 | * regulators required for a SDCC slot. |
| 81 | */ |
| 82 | struct sdhci_msm_slot_reg_data { |
| 83 | /* keeps VDD/VCC regulator info */ |
| 84 | struct sdhci_msm_reg_data *vdd_data; |
| 85 | /* keeps VDD IO regulator info */ |
| 86 | struct sdhci_msm_reg_data *vdd_io_data; |
| 87 | }; |
| 88 | |
| 89 | struct sdhci_msm_gpio { |
| 90 | u32 no; |
| 91 | const char *name; |
| 92 | bool is_enabled; |
| 93 | }; |
| 94 | |
| 95 | struct sdhci_msm_gpio_data { |
| 96 | struct sdhci_msm_gpio *gpio; |
| 97 | u8 size; |
| 98 | }; |
| 99 | |
| 100 | struct sdhci_msm_pin_data { |
| 101 | /* |
| 102 | * = 1 if controller pins are using gpios |
| 103 | * = 0 if controller has dedicated MSM pads |
| 104 | */ |
| 105 | bool cfg_sts; |
| 106 | struct sdhci_msm_gpio_data *gpio_data; |
| 107 | }; |
| 108 | |
| 109 | struct sdhci_msm_pltfm_data { |
| 110 | /* Supported UHS-I Modes */ |
| 111 | u32 caps; |
| 112 | |
| 113 | /* More capabilities */ |
| 114 | u32 caps2; |
| 115 | |
| 116 | unsigned long mmc_bus_width; |
| 117 | u32 max_clk; |
| 118 | struct sdhci_msm_slot_reg_data *vreg_data; |
| 119 | bool nonremovable; |
| 120 | struct sdhci_msm_pin_data *pin_data; |
| 121 | }; |
| 122 | |
| 123 | struct sdhci_msm_host { |
| 124 | void __iomem *core_mem; /* MSM SDCC mapped address */ |
| 125 | struct clk *clk; /* main SD/MMC bus clock */ |
| 126 | struct clk *pclk; /* SDHC peripheral bus clock */ |
| 127 | struct clk *bus_clk; /* SDHC bus voter clock */ |
| 128 | struct sdhci_msm_pltfm_data *pdata; |
| 129 | struct mmc_host *mmc; |
| 130 | struct sdhci_pltfm_data sdhci_msm_pdata; |
| 131 | wait_queue_head_t pwr_irq_wait; |
| 132 | }; |
| 133 | |
| 134 | enum vdd_io_level { |
| 135 | /* set vdd_io_data->low_vol_level */ |
| 136 | VDD_IO_LOW, |
| 137 | /* set vdd_io_data->high_vol_level */ |
| 138 | VDD_IO_HIGH, |
| 139 | /* |
| 140 | * set whatever there in voltage_level (third argument) of |
| 141 | * sdhci_msm_set_vdd_io_vol() function. |
| 142 | */ |
| 143 | VDD_IO_SET_LEVEL, |
| 144 | }; |
| 145 | |
| 146 | static int sdhci_msm_setup_gpio(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 147 | { |
| 148 | struct sdhci_msm_gpio_data *curr; |
| 149 | int i, ret = 0; |
| 150 | |
| 151 | curr = pdata->pin_data->gpio_data; |
| 152 | for (i = 0; i < curr->size; i++) { |
| 153 | if (!gpio_is_valid(curr->gpio[i].no)) { |
| 154 | ret = -EINVAL; |
| 155 | pr_err("%s: Invalid gpio = %d\n", __func__, |
| 156 | curr->gpio[i].no); |
| 157 | goto free_gpios; |
| 158 | } |
| 159 | if (enable) { |
| 160 | ret = gpio_request(curr->gpio[i].no, |
| 161 | curr->gpio[i].name); |
| 162 | if (ret) { |
| 163 | pr_err("%s: gpio_request(%d, %s) failed %d\n", |
| 164 | __func__, curr->gpio[i].no, |
| 165 | curr->gpio[i].name, ret); |
| 166 | goto free_gpios; |
| 167 | } |
| 168 | curr->gpio[i].is_enabled = true; |
| 169 | } else { |
| 170 | gpio_free(curr->gpio[i].no); |
| 171 | curr->gpio[i].is_enabled = false; |
| 172 | } |
| 173 | } |
| 174 | return ret; |
| 175 | |
| 176 | free_gpios: |
| 177 | for (i--; i >= 0; i--) { |
| 178 | gpio_free(curr->gpio[i].no); |
| 179 | curr->gpio[i].is_enabled = false; |
| 180 | } |
| 181 | return ret; |
| 182 | } |
| 183 | |
| 184 | static int sdhci_msm_setup_pins(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 185 | { |
| 186 | int ret = 0; |
| 187 | |
| 188 | if (!pdata->pin_data || (pdata->pin_data->cfg_sts == enable)) |
| 189 | return 0; |
| 190 | |
| 191 | ret = sdhci_msm_setup_gpio(pdata, enable); |
| 192 | if (!ret) |
| 193 | pdata->pin_data->cfg_sts = enable; |
| 194 | |
| 195 | return ret; |
| 196 | } |
| 197 | |
| 198 | #define MAX_PROP_SIZE 32 |
| 199 | static int sdhci_msm_dt_parse_vreg_info(struct device *dev, |
| 200 | struct sdhci_msm_reg_data **vreg_data, const char *vreg_name) |
| 201 | { |
| 202 | int len, ret = 0; |
| 203 | const __be32 *prop; |
| 204 | char prop_name[MAX_PROP_SIZE]; |
| 205 | struct sdhci_msm_reg_data *vreg; |
| 206 | struct device_node *np = dev->of_node; |
| 207 | |
| 208 | snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", vreg_name); |
| 209 | if (!of_parse_phandle(np, prop_name, 0)) { |
| 210 | dev_err(dev, "No vreg data found for %s\n", vreg_name); |
| 211 | ret = -EINVAL; |
| 212 | return ret; |
| 213 | } |
| 214 | |
| 215 | vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); |
| 216 | if (!vreg) { |
| 217 | dev_err(dev, "No memory for vreg: %s\n", vreg_name); |
| 218 | ret = -ENOMEM; |
| 219 | return ret; |
| 220 | } |
| 221 | |
| 222 | vreg->name = vreg_name; |
| 223 | |
| 224 | snprintf(prop_name, MAX_PROP_SIZE, |
| 225 | "qcom,%s-always-on", vreg_name); |
| 226 | if (of_get_property(np, prop_name, NULL)) |
| 227 | vreg->is_always_on = true; |
| 228 | |
| 229 | snprintf(prop_name, MAX_PROP_SIZE, |
| 230 | "qcom,%s-lpm-sup", vreg_name); |
| 231 | if (of_get_property(np, prop_name, NULL)) |
| 232 | vreg->lpm_sup = true; |
| 233 | |
| 234 | snprintf(prop_name, MAX_PROP_SIZE, |
| 235 | "qcom,%s-voltage-level", vreg_name); |
| 236 | prop = of_get_property(np, prop_name, &len); |
| 237 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 238 | dev_warn(dev, "%s %s property\n", |
| 239 | prop ? "invalid format" : "no", prop_name); |
| 240 | } else { |
| 241 | vreg->low_vol_level = be32_to_cpup(&prop[0]); |
| 242 | vreg->high_vol_level = be32_to_cpup(&prop[1]); |
| 243 | } |
| 244 | |
| 245 | snprintf(prop_name, MAX_PROP_SIZE, |
| 246 | "qcom,%s-current-level", vreg_name); |
| 247 | prop = of_get_property(np, prop_name, &len); |
| 248 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 249 | dev_warn(dev, "%s %s property\n", |
| 250 | prop ? "invalid format" : "no", prop_name); |
| 251 | } else { |
| 252 | vreg->lpm_uA = be32_to_cpup(&prop[0]); |
| 253 | vreg->hpm_uA = be32_to_cpup(&prop[1]); |
| 254 | } |
| 255 | |
| 256 | *vreg_data = vreg; |
| 257 | dev_dbg(dev, "%s: %s %s vol=[%d %d]uV, curr=[%d %d]uA\n", |
| 258 | vreg->name, vreg->is_always_on ? "always_on," : "", |
| 259 | vreg->lpm_sup ? "lpm_sup," : "", vreg->low_vol_level, |
| 260 | vreg->high_vol_level, vreg->lpm_uA, vreg->hpm_uA); |
| 261 | |
| 262 | return ret; |
| 263 | } |
| 264 | |
| 265 | #define GPIO_NAME_MAX_LEN 32 |
| 266 | static int sdhci_msm_dt_parse_gpio_info(struct device *dev, |
| 267 | struct sdhci_msm_pltfm_data *pdata) |
| 268 | { |
| 269 | int ret = 0, cnt, i; |
| 270 | struct sdhci_msm_pin_data *pin_data; |
| 271 | struct device_node *np = dev->of_node; |
| 272 | |
| 273 | pin_data = devm_kzalloc(dev, sizeof(*pin_data), GFP_KERNEL); |
| 274 | if (!pin_data) { |
| 275 | dev_err(dev, "No memory for pin_data\n"); |
| 276 | ret = -ENOMEM; |
| 277 | goto out; |
| 278 | } |
| 279 | |
| 280 | cnt = of_gpio_count(np); |
| 281 | if (cnt > 0) { |
| 282 | pin_data->gpio_data = devm_kzalloc(dev, |
| 283 | sizeof(struct sdhci_msm_gpio_data), GFP_KERNEL); |
| 284 | if (!pin_data->gpio_data) { |
| 285 | dev_err(dev, "No memory for gpio_data\n"); |
| 286 | ret = -ENOMEM; |
| 287 | goto out; |
| 288 | } |
| 289 | pin_data->gpio_data->size = cnt; |
| 290 | pin_data->gpio_data->gpio = devm_kzalloc(dev, cnt * |
| 291 | sizeof(struct sdhci_msm_gpio), GFP_KERNEL); |
| 292 | |
| 293 | if (!pin_data->gpio_data->gpio) { |
| 294 | dev_err(dev, "No memory for gpio\n"); |
| 295 | ret = -ENOMEM; |
| 296 | goto out; |
| 297 | } |
| 298 | |
| 299 | for (i = 0; i < cnt; i++) { |
| 300 | const char *name = NULL; |
| 301 | char result[GPIO_NAME_MAX_LEN]; |
| 302 | pin_data->gpio_data->gpio[i].no = of_get_gpio(np, i); |
| 303 | of_property_read_string_index(np, |
| 304 | "qcom,gpio-names", i, &name); |
| 305 | |
| 306 | snprintf(result, GPIO_NAME_MAX_LEN, "%s-%s", |
| 307 | dev_name(dev), name ? name : "?"); |
| 308 | pin_data->gpio_data->gpio[i].name = result; |
| 309 | dev_dbg(dev, "%s: gpio[%s] = %d\n", __func__, |
| 310 | pin_data->gpio_data->gpio[i].name, |
| 311 | pin_data->gpio_data->gpio[i].no); |
| 312 | pdata->pin_data = pin_data; |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | out: |
| 317 | if (ret) |
| 318 | dev_err(dev, "%s failed with err %d\n", __func__, ret); |
| 319 | return ret; |
| 320 | } |
| 321 | |
| 322 | /* Parse platform data */ |
| 323 | static struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev) |
| 324 | { |
| 325 | struct sdhci_msm_pltfm_data *pdata = NULL; |
| 326 | struct device_node *np = dev->of_node; |
| 327 | u32 bus_width = 0; |
| 328 | int len, i; |
| 329 | |
| 330 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
| 331 | if (!pdata) { |
| 332 | dev_err(dev, "failed to allocate memory for platform data\n"); |
| 333 | goto out; |
| 334 | } |
| 335 | |
| 336 | of_property_read_u32(np, "qcom,bus-width", &bus_width); |
| 337 | if (bus_width == 8) |
| 338 | pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA; |
| 339 | else if (bus_width == 4) |
| 340 | pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA; |
| 341 | else { |
| 342 | dev_notice(dev, "invalid bus-width, default to 1-bit mode\n"); |
| 343 | pdata->mmc_bus_width = 0; |
| 344 | } |
| 345 | |
| 346 | pdata->vreg_data = devm_kzalloc(dev, sizeof(struct |
| 347 | sdhci_msm_slot_reg_data), |
| 348 | GFP_KERNEL); |
| 349 | if (!pdata->vreg_data) { |
| 350 | dev_err(dev, "failed to allocate memory for vreg data\n"); |
| 351 | goto out; |
| 352 | } |
| 353 | |
| 354 | if (sdhci_msm_dt_parse_vreg_info(dev, &pdata->vreg_data->vdd_data, |
| 355 | "vdd")) { |
| 356 | dev_err(dev, "failed parsing vdd data\n"); |
| 357 | goto out; |
| 358 | } |
| 359 | if (sdhci_msm_dt_parse_vreg_info(dev, |
| 360 | &pdata->vreg_data->vdd_io_data, |
| 361 | "vdd-io")) { |
| 362 | dev_err(dev, "failed parsing vdd-io data\n"); |
| 363 | goto out; |
| 364 | } |
| 365 | |
| 366 | if (sdhci_msm_dt_parse_gpio_info(dev, pdata)) { |
| 367 | dev_err(dev, "failed parsing gpio data\n"); |
| 368 | goto out; |
| 369 | } |
| 370 | |
| 371 | of_property_read_u32(np, "qcom,max-clk-rate", &pdata->max_clk); |
| 372 | |
| 373 | len = of_property_count_strings(np, "qcom,bus-speed-mode"); |
| 374 | |
| 375 | for (i = 0; i < len; i++) { |
| 376 | const char *name = NULL; |
| 377 | |
| 378 | of_property_read_string_index(np, |
| 379 | "qcom,bus-speed-mode", i, &name); |
| 380 | if (!name) |
| 381 | continue; |
| 382 | |
| 383 | if (!strncmp(name, "HS200_1p8v", sizeof("HS200_1p8v"))) |
| 384 | pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR; |
| 385 | else if (!strncmp(name, "HS200_1p2v", sizeof("HS200_1p2v"))) |
| 386 | pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR; |
| 387 | else if (!strncmp(name, "DDR_1p8v", sizeof("DDR_1p8v"))) |
| 388 | pdata->caps |= MMC_CAP_1_8V_DDR |
| 389 | | MMC_CAP_UHS_DDR50; |
| 390 | else if (!strncmp(name, "DDR_1p2v", sizeof("DDR_1p2v"))) |
| 391 | pdata->caps |= MMC_CAP_1_2V_DDR |
| 392 | | MMC_CAP_UHS_DDR50; |
| 393 | } |
| 394 | |
| 395 | if (of_get_property(np, "qcom,nonremovable", NULL)) |
| 396 | pdata->nonremovable = true; |
| 397 | |
| 398 | return pdata; |
| 399 | out: |
| 400 | return NULL; |
| 401 | } |
| 402 | |
| 403 | /* Regulator utility functions */ |
| 404 | static int sdhci_msm_vreg_init_reg(struct device *dev, |
| 405 | struct sdhci_msm_reg_data *vreg) |
| 406 | { |
| 407 | int ret = 0; |
| 408 | |
| 409 | /* check if regulator is already initialized? */ |
| 410 | if (vreg->reg) |
| 411 | goto out; |
| 412 | |
| 413 | /* Get the regulator handle */ |
| 414 | vreg->reg = devm_regulator_get(dev, vreg->name); |
| 415 | if (IS_ERR(vreg->reg)) { |
| 416 | ret = PTR_ERR(vreg->reg); |
| 417 | pr_err("%s: devm_regulator_get(%s) failed. ret=%d\n", |
| 418 | __func__, vreg->name, ret); |
| 419 | goto out; |
| 420 | } |
| 421 | |
| 422 | /* sanity check */ |
| 423 | if (!vreg->high_vol_level || !vreg->hpm_uA) { |
| 424 | pr_err("%s: %s invalid constraints specified\n", |
| 425 | __func__, vreg->name); |
| 426 | ret = -EINVAL; |
| 427 | } |
| 428 | |
| 429 | out: |
| 430 | return ret; |
| 431 | } |
| 432 | |
| 433 | static void sdhci_msm_vreg_deinit_reg(struct sdhci_msm_reg_data *vreg) |
| 434 | { |
| 435 | if (vreg->reg) |
| 436 | devm_regulator_put(vreg->reg); |
| 437 | } |
| 438 | |
| 439 | static int sdhci_msm_vreg_set_optimum_mode(struct sdhci_msm_reg_data |
| 440 | *vreg, int uA_load) |
| 441 | { |
| 442 | int ret = 0; |
| 443 | |
| 444 | /* |
| 445 | * regulators that do not support regulator_set_voltage also |
| 446 | * do not support regulator_set_optimum_mode |
| 447 | */ |
| 448 | if (vreg->set_voltage_sup) { |
| 449 | ret = regulator_set_load(vreg->reg, uA_load); |
| 450 | if (ret < 0) |
| 451 | pr_err("%s: regulator_set_load(reg=%s,uA_load=%d) failed. ret=%d\n", |
| 452 | __func__, vreg->name, uA_load, ret); |
| 453 | else |
| 454 | /* |
| 455 | * regulator_set_load() can return non zero |
| 456 | * value even for success case. |
| 457 | */ |
| 458 | ret = 0; |
| 459 | } |
| 460 | return ret; |
| 461 | } |
| 462 | |
| 463 | static int sdhci_msm_vreg_set_voltage(struct sdhci_msm_reg_data *vreg, |
| 464 | int min_uV, int max_uV) |
| 465 | { |
| 466 | int ret = 0; |
| 467 | |
| 468 | ret = regulator_set_voltage(vreg->reg, min_uV, max_uV); |
| 469 | if (ret) { |
| 470 | pr_err("%s: regulator_set_voltage(%s)failed. min_uV=%d,max_uV=%d,ret=%d\n", |
| 471 | __func__, vreg->name, min_uV, max_uV, ret); |
| 472 | } |
| 473 | |
| 474 | return ret; |
| 475 | } |
| 476 | |
| 477 | static int sdhci_msm_vreg_enable(struct sdhci_msm_reg_data *vreg) |
| 478 | { |
| 479 | int ret = 0; |
| 480 | |
| 481 | /* Put regulator in HPM (high power mode) */ |
| 482 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, vreg->hpm_uA); |
| 483 | if (ret < 0) |
| 484 | return ret; |
| 485 | |
| 486 | if (!vreg->is_enabled) { |
| 487 | /* Set voltage level */ |
| 488 | ret = sdhci_msm_vreg_set_voltage(vreg, vreg->high_vol_level, |
| 489 | vreg->high_vol_level); |
| 490 | if (ret) |
| 491 | return ret; |
| 492 | } |
| 493 | ret = regulator_enable(vreg->reg); |
| 494 | if (ret) { |
| 495 | pr_err("%s: regulator_enable(%s) failed. ret=%d\n", |
| 496 | __func__, vreg->name, ret); |
| 497 | return ret; |
| 498 | } |
| 499 | vreg->is_enabled = true; |
| 500 | return ret; |
| 501 | } |
| 502 | |
| 503 | static int sdhci_msm_vreg_disable(struct sdhci_msm_reg_data *vreg) |
| 504 | { |
| 505 | int ret = 0; |
| 506 | |
| 507 | /* Never disable regulator marked as always_on */ |
| 508 | if (vreg->is_enabled && !vreg->is_always_on) { |
| 509 | ret = regulator_disable(vreg->reg); |
| 510 | if (ret) { |
| 511 | pr_err("%s: regulator_disable(%s) failed. ret=%d\n", |
| 512 | __func__, vreg->name, ret); |
| 513 | goto out; |
| 514 | } |
| 515 | vreg->is_enabled = false; |
| 516 | |
| 517 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, 0); |
| 518 | if (ret < 0) |
| 519 | goto out; |
| 520 | |
| 521 | /* Set min. voltage level to 0 */ |
| 522 | ret = sdhci_msm_vreg_set_voltage(vreg, 0, vreg->high_vol_level); |
| 523 | if (ret) |
| 524 | goto out; |
| 525 | } else if (vreg->is_enabled && vreg->is_always_on) { |
| 526 | if (vreg->lpm_sup) { |
| 527 | /* Put always_on regulator in LPM (low power mode) */ |
| 528 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, |
| 529 | vreg->lpm_uA); |
| 530 | if (ret < 0) |
| 531 | goto out; |
| 532 | } |
| 533 | } |
| 534 | out: |
| 535 | return ret; |
| 536 | } |
| 537 | |
| 538 | static int sdhci_msm_setup_vreg(struct sdhci_msm_pltfm_data *pdata, |
| 539 | bool enable, bool is_init) |
| 540 | { |
| 541 | int ret = 0, i; |
| 542 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 543 | struct sdhci_msm_reg_data *vreg_table[2]; |
| 544 | |
| 545 | curr_slot = pdata->vreg_data; |
| 546 | if (!curr_slot) { |
| 547 | pr_debug("%s: vreg info unavailable,assuming the slot is powered by always on domain\n", |
| 548 | __func__); |
| 549 | goto out; |
| 550 | } |
| 551 | |
| 552 | vreg_table[0] = curr_slot->vdd_data; |
| 553 | vreg_table[1] = curr_slot->vdd_io_data; |
| 554 | |
| 555 | for (i = 0; i < ARRAY_SIZE(vreg_table); i++) { |
| 556 | if (vreg_table[i]) { |
| 557 | if (enable) |
| 558 | ret = sdhci_msm_vreg_enable(vreg_table[i]); |
| 559 | else |
| 560 | ret = sdhci_msm_vreg_disable(vreg_table[i]); |
| 561 | if (ret) |
| 562 | goto out; |
| 563 | } |
| 564 | } |
| 565 | out: |
| 566 | return ret; |
| 567 | } |
| 568 | |
| 569 | /* |
| 570 | * Reset vreg by ensuring it is off during probe. A call |
| 571 | * to enable vreg is needed to balance disable vreg |
| 572 | */ |
| 573 | static int sdhci_msm_vreg_reset(struct sdhci_msm_pltfm_data *pdata) |
| 574 | { |
| 575 | int ret; |
| 576 | |
| 577 | ret = sdhci_msm_setup_vreg(pdata, 1, true); |
| 578 | if (ret) |
| 579 | return ret; |
| 580 | ret = sdhci_msm_setup_vreg(pdata, 0, true); |
| 581 | return ret; |
| 582 | } |
| 583 | |
| 584 | /* This init function should be called only once for each SDHC slot */ |
| 585 | static int sdhci_msm_vreg_init(struct device *dev, |
| 586 | struct sdhci_msm_pltfm_data *pdata, |
| 587 | bool is_init) |
| 588 | { |
| 589 | int ret = 0; |
| 590 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 591 | struct sdhci_msm_reg_data *curr_vdd_reg, *curr_vdd_io_reg; |
| 592 | |
| 593 | curr_slot = pdata->vreg_data; |
| 594 | if (!curr_slot) |
| 595 | goto out; |
| 596 | |
| 597 | curr_vdd_reg = curr_slot->vdd_data; |
| 598 | curr_vdd_io_reg = curr_slot->vdd_io_data; |
| 599 | |
| 600 | if (!is_init) |
| 601 | /* Deregister all regulators from regulator framework */ |
| 602 | goto vdd_io_reg_deinit; |
| 603 | |
| 604 | /* |
| 605 | * Get the regulator handle from voltage regulator framework |
| 606 | * and then try to set the voltage level for the regulator |
| 607 | */ |
| 608 | if (curr_vdd_reg) { |
| 609 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_reg); |
| 610 | if (ret) |
| 611 | goto out; |
| 612 | } |
| 613 | if (curr_vdd_io_reg) { |
| 614 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_io_reg); |
| 615 | if (ret) |
| 616 | goto vdd_reg_deinit; |
| 617 | } |
| 618 | ret = sdhci_msm_vreg_reset(pdata); |
| 619 | if (ret) |
| 620 | dev_err(dev, "vreg reset failed (%d)\n", ret); |
| 621 | goto out; |
| 622 | |
| 623 | vdd_io_reg_deinit: |
| 624 | if (curr_vdd_io_reg) |
| 625 | sdhci_msm_vreg_deinit_reg(curr_vdd_io_reg); |
| 626 | vdd_reg_deinit: |
| 627 | if (curr_vdd_reg) |
| 628 | sdhci_msm_vreg_deinit_reg(curr_vdd_reg); |
| 629 | out: |
| 630 | return ret; |
| 631 | } |
| 632 | |
| 633 | |
| 634 | static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata, |
| 635 | enum vdd_io_level level, |
| 636 | unsigned int voltage_level) |
| 637 | { |
| 638 | int ret = 0; |
| 639 | int set_level; |
| 640 | struct sdhci_msm_reg_data *vdd_io_reg; |
| 641 | |
| 642 | if (!pdata->vreg_data) |
| 643 | return ret; |
| 644 | |
| 645 | vdd_io_reg = pdata->vreg_data->vdd_io_data; |
| 646 | if (vdd_io_reg && vdd_io_reg->is_enabled) { |
| 647 | switch (level) { |
| 648 | case VDD_IO_LOW: |
| 649 | set_level = vdd_io_reg->low_vol_level; |
| 650 | break; |
| 651 | case VDD_IO_HIGH: |
| 652 | set_level = vdd_io_reg->high_vol_level; |
| 653 | break; |
| 654 | case VDD_IO_SET_LEVEL: |
| 655 | set_level = voltage_level; |
| 656 | break; |
| 657 | default: |
| 658 | pr_err("%s: invalid argument level = %d", |
| 659 | __func__, level); |
| 660 | ret = -EINVAL; |
| 661 | return ret; |
| 662 | } |
| 663 | ret = sdhci_msm_vreg_set_voltage(vdd_io_reg, set_level, |
| 664 | set_level); |
| 665 | } |
| 666 | return ret; |
| 667 | } |
| 668 | |
| 669 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) |
| 670 | { |
| 671 | struct sdhci_msm_host *msm_host = (struct sdhci_msm_host *)data; |
| 672 | u8 irq_status = 0; |
| 673 | u8 irq_ack = 0; |
| 674 | int ret = 0; |
| 675 | |
| 676 | irq_status = readb_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); |
| 677 | pr_debug("%s: Received IRQ(%d), status=0x%x\n", |
| 678 | mmc_hostname(msm_host->mmc), irq, irq_status); |
| 679 | |
| 680 | /* Clear the interrupt */ |
| 681 | writeb_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR)); |
| 682 | /* |
| 683 | * SDHC has core_mem and hc_mem device memory and these memory |
| 684 | * addresses do not fall within 1KB region. Hence, any update to |
| 685 | * core_mem address space would require an mb() to ensure this gets |
| 686 | * completed before its next update to registers within hc_mem. |
| 687 | */ |
| 688 | mb(); |
| 689 | |
| 690 | /* Handle BUS ON/OFF*/ |
| 691 | if (irq_status & CORE_PWRCTL_BUS_ON) { |
| 692 | ret = sdhci_msm_setup_vreg(msm_host->pdata, true, false); |
| 693 | if (!ret) |
| 694 | ret = sdhci_msm_setup_pins(msm_host->pdata, true); |
| 695 | if (ret) |
| 696 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 697 | else |
| 698 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
| 699 | } |
| 700 | if (irq_status & CORE_PWRCTL_BUS_OFF) { |
| 701 | ret = sdhci_msm_setup_vreg(msm_host->pdata, false, false); |
| 702 | if (!ret) |
| 703 | ret = sdhci_msm_setup_pins(msm_host->pdata, false); |
| 704 | if (ret) |
| 705 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 706 | else |
| 707 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
| 708 | } |
| 709 | /* Handle IO LOW/HIGH */ |
| 710 | if (irq_status & CORE_PWRCTL_IO_LOW) { |
| 711 | /* Switch voltage Low */ |
| 712 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0); |
| 713 | if (ret) |
| 714 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 715 | else |
| 716 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
| 717 | } |
| 718 | if (irq_status & CORE_PWRCTL_IO_HIGH) { |
| 719 | /* Switch voltage High */ |
| 720 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0); |
| 721 | if (ret) |
| 722 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 723 | else |
| 724 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
| 725 | } |
| 726 | |
| 727 | /* ACK status to the core */ |
| 728 | writeb_relaxed(irq_ack, (msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 729 | /* |
| 730 | * SDHC has core_mem and hc_mem device memory and these memory |
| 731 | * addresses do not fall within 1KB region. Hence, any update to |
| 732 | * core_mem address space would require an mb() to ensure this gets |
| 733 | * completed before its next update to registers within hc_mem. |
| 734 | */ |
| 735 | mb(); |
| 736 | |
| 737 | pr_debug("%s: Handled IRQ(%d), ret=%d, ack=0x%x\n", |
| 738 | mmc_hostname(msm_host->mmc), irq, ret, irq_ack); |
| 739 | wake_up_interruptible(&msm_host->pwr_irq_wait); |
| 740 | return IRQ_HANDLED; |
| 741 | } |
| 742 | |
| 743 | static void sdhci_msm_check_power_status(struct sdhci_host *host) |
| 744 | { |
| 745 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 746 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 747 | int ret = 0; |
| 748 | |
| 749 | pr_debug("%s: %s: power status before waiting 0x%x\n", |
| 750 | mmc_hostname(host->mmc), __func__, |
| 751 | readb_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 752 | |
| 753 | ret = wait_event_interruptible(msm_host->pwr_irq_wait, |
| 754 | (readb_relaxed(msm_host->core_mem + |
| 755 | CORE_PWRCTL_CTL)) != 0x0); |
| 756 | if (ret) |
| 757 | pr_warning("%s: %s: returned due to error %d\n", |
| 758 | mmc_hostname(host->mmc), __func__, ret); |
| 759 | pr_debug("%s: %s: ret %d power status after handling power IRQ 0x%x\n", |
| 760 | mmc_hostname(host->mmc), __func__, ret, |
| 761 | readb_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 762 | } |
| 763 | |
| 764 | static struct sdhci_ops sdhci_msm_ops = { |
| 765 | .check_power_status = sdhci_msm_check_power_status, |
| 766 | }; |
| 767 | |
| 768 | static int sdhci_msm_probe(struct platform_device *pdev) |
| 769 | { |
| 770 | struct sdhci_host *host; |
| 771 | struct sdhci_pltfm_host *pltfm_host; |
| 772 | struct sdhci_msm_host *msm_host; |
| 773 | struct resource *core_memres = NULL; |
| 774 | int ret = 0, pwr_irq = 0, dead = 0; |
| 775 | |
| 776 | pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__); |
| 777 | msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host), |
| 778 | GFP_KERNEL); |
| 779 | if (!msm_host) { |
| 780 | ret = -ENOMEM; |
| 781 | goto out; |
| 782 | } |
| 783 | init_waitqueue_head(&msm_host->pwr_irq_wait); |
| 784 | |
| 785 | msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops; |
| 786 | host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0); |
| 787 | if (IS_ERR(host)) { |
| 788 | ret = PTR_ERR(host); |
| 789 | goto out; |
| 790 | } |
| 791 | |
| 792 | pltfm_host = sdhci_priv(host); |
| 793 | pltfm_host->priv = msm_host; |
| 794 | msm_host->mmc = host->mmc; |
| 795 | |
| 796 | /* Extract platform data */ |
| 797 | if (pdev->dev.of_node) { |
| 798 | msm_host->pdata = sdhci_msm_populate_pdata(&pdev->dev); |
| 799 | if (!msm_host->pdata) { |
| 800 | dev_err(&pdev->dev, "DT parsing error\n"); |
| 801 | goto pltfm_free; |
| 802 | } |
| 803 | } else { |
| 804 | dev_err(&pdev->dev, "No device tree node\n"); |
| 805 | goto pltfm_free; |
| 806 | } |
| 807 | |
| 808 | /* Setup Clocks */ |
| 809 | |
| 810 | /* Setup SDCC bus voter clock. */ |
| 811 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); |
| 812 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { |
| 813 | /* Vote for max. clk rate for max. performance */ |
| 814 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); |
| 815 | if (ret) |
| 816 | goto pltfm_free; |
| 817 | ret = clk_prepare_enable(msm_host->bus_clk); |
| 818 | if (ret) |
| 819 | goto pltfm_free; |
| 820 | } |
| 821 | |
| 822 | /* Setup main peripheral bus clock */ |
| 823 | msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk"); |
| 824 | if (!IS_ERR(msm_host->pclk)) { |
| 825 | ret = clk_prepare_enable(msm_host->pclk); |
| 826 | if (ret) |
| 827 | goto bus_clk_disable; |
| 828 | } |
| 829 | |
| 830 | /* Setup SDC MMC clock */ |
| 831 | msm_host->clk = devm_clk_get(&pdev->dev, "core_clk"); |
| 832 | if (IS_ERR(msm_host->clk)) { |
| 833 | ret = PTR_ERR(msm_host->clk); |
| 834 | goto pclk_disable; |
| 835 | } |
| 836 | |
| 837 | ret = clk_prepare_enable(msm_host->clk); |
| 838 | if (ret) |
| 839 | goto pclk_disable; |
| 840 | |
| 841 | /* Setup regulators */ |
| 842 | ret = sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, true); |
| 843 | if (ret) { |
| 844 | dev_err(&pdev->dev, "Regulator setup failed (%d)\n", ret); |
| 845 | goto clk_disable; |
| 846 | } |
| 847 | |
| 848 | /* Reset the core and Enable SDHC mode */ |
| 849 | core_memres = platform_get_resource_byname(pdev, |
| 850 | IORESOURCE_MEM, "core_mem"); |
| 851 | msm_host->core_mem = devm_ioremap(&pdev->dev, core_memres->start, |
| 852 | resource_size(core_memres)); |
| 853 | |
| 854 | if (!msm_host->core_mem) { |
| 855 | dev_err(&pdev->dev, "Failed to remap registers\n"); |
| 856 | ret = -ENOMEM; |
| 857 | goto vreg_deinit; |
| 858 | } |
| 859 | |
| 860 | /* Set SW_RST bit in POWER register (Offset 0x0) */ |
| 861 | writel_relaxed(CORE_SW_RST, msm_host->core_mem + CORE_POWER); |
| 862 | /* Set HC_MODE_EN bit in HC_MODE register */ |
| 863 | writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); |
| 864 | |
| 865 | /* |
| 866 | * Following are the deviations from SDHC spec v3.0 - |
| 867 | * 1. Card detection is handled using separate GPIO. |
| 868 | * 2. Bus power control is handled by interacting with PMIC. |
| 869 | */ |
| 870 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
| 871 | host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE; |
| 872 | |
| 873 | pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); |
| 874 | if (pwr_irq < 0) { |
| 875 | dev_err(&pdev->dev, "Failed to get pwr_irq by name (%d)\n", |
| 876 | pwr_irq); |
| 877 | goto vreg_deinit; |
| 878 | } |
| 879 | ret = devm_request_threaded_irq(&pdev->dev, pwr_irq, NULL, |
| 880 | sdhci_msm_pwr_irq, IRQF_ONESHOT, |
| 881 | dev_name(&pdev->dev), msm_host); |
| 882 | if (ret) { |
| 883 | dev_err(&pdev->dev, "Request threaded irq(%d) failed (%d)\n", |
| 884 | pwr_irq, ret); |
| 885 | goto vreg_deinit; |
| 886 | } |
| 887 | |
| 888 | /* Enable pwr irq interrupts */ |
| 889 | writel_relaxed(INT_MASK, (msm_host->core_mem + CORE_PWRCTL_MASK)); |
| 890 | |
| 891 | /* Set host capabilities */ |
| 892 | msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width; |
| 893 | msm_host->mmc->caps |= msm_host->pdata->caps; |
| 894 | |
| 895 | msm_host->mmc->caps2 |= msm_host->pdata->caps2; |
| 896 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR; |
| 897 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR_CONTROL; |
| 898 | |
| 899 | if (msm_host->pdata->nonremovable) |
| 900 | msm_host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
| 901 | |
| 902 | ret = sdhci_add_host(host); |
| 903 | if (ret) { |
| 904 | dev_err(&pdev->dev, "Add host failed (%d)\n", ret); |
| 905 | goto vreg_deinit; |
| 906 | } |
| 907 | |
| 908 | /* Set core clk rate, optionally override from dts */ |
| 909 | if (msm_host->pdata->max_clk) |
| 910 | host->max_clk = msm_host->pdata->max_clk; |
| 911 | ret = clk_set_rate(msm_host->clk, host->max_clk); |
| 912 | if (ret) { |
| 913 | dev_err(&pdev->dev, "MClk rate set failed (%d)\n", ret); |
| 914 | goto remove_host; |
| 915 | } |
| 916 | |
| 917 | /* Successful initialization */ |
| 918 | goto out; |
| 919 | |
| 920 | remove_host: |
| 921 | dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
| 922 | sdhci_remove_host(host, dead); |
| 923 | vreg_deinit: |
| 924 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
| 925 | clk_disable: |
| 926 | if (!IS_ERR(msm_host->clk)) |
| 927 | clk_disable_unprepare(msm_host->clk); |
| 928 | pclk_disable: |
| 929 | if (!IS_ERR(msm_host->pclk)) |
| 930 | clk_disable_unprepare(msm_host->pclk); |
| 931 | bus_clk_disable: |
| 932 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 933 | clk_disable_unprepare(msm_host->bus_clk); |
| 934 | pltfm_free: |
| 935 | sdhci_pltfm_free(pdev); |
| 936 | out: |
| 937 | pr_debug("%s: Exit %s\n", dev_name(&pdev->dev), __func__); |
| 938 | return ret; |
| 939 | } |
| 940 | |
| 941 | static int sdhci_msm_remove(struct platform_device *pdev) |
| 942 | { |
| 943 | struct sdhci_host *host = platform_get_drvdata(pdev); |
| 944 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 945 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 946 | struct sdhci_msm_pltfm_data *pdata = msm_host->pdata; |
| 947 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
| 948 | 0xffffffff); |
| 949 | |
| 950 | pr_debug("%s: %s\n", dev_name(&pdev->dev), __func__); |
| 951 | sdhci_remove_host(host, dead); |
| 952 | sdhci_pltfm_free(pdev); |
| 953 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
| 954 | if (!IS_ERR(msm_host->clk)) |
| 955 | clk_disable_unprepare(msm_host->clk); |
| 956 | if (!IS_ERR(msm_host->pclk)) |
| 957 | clk_disable_unprepare(msm_host->pclk); |
| 958 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 959 | clk_disable_unprepare(msm_host->bus_clk); |
| 960 | if (pdata->pin_data) |
| 961 | sdhci_msm_setup_gpio(pdata, false); |
| 962 | return 0; |
| 963 | } |
| 964 | |
| 965 | static const struct of_device_id sdhci_msm_dt_match[] = { |
| 966 | {.compatible = "qcom,sdhci-msm"}, |
| 967 | }; |
| 968 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); |
| 969 | |
| 970 | static struct platform_driver sdhci_msm_driver = { |
| 971 | .probe = sdhci_msm_probe, |
| 972 | .remove = sdhci_msm_remove, |
| 973 | .driver = { |
| 974 | .name = "sdhci_msm", |
| 975 | .owner = THIS_MODULE, |
| 976 | .of_match_table = sdhci_msm_dt_match, |
| 977 | }, |
| 978 | }; |
| 979 | |
| 980 | module_platform_driver(sdhci_msm_driver); |
| 981 | |
| 982 | MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Secure Digital Host Controller Interface driver"); |
| 983 | MODULE_LICENSE("GPL v2"); |