Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3xxx PRM module functions |
| 3 | * |
| 4 | * Copyright (C) 2010-2012 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2010 Nokia Corporation |
| 6 | * BenoƮt Cousson |
| 7 | * Paul Walmsley |
Paul Walmsley | 4981539 | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 8 | * Rajendra Nayak <rnayak@ti.com> |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/irq.h> |
| 20 | |
Tony Lindgren | e8d3d47 | 2012-12-16 11:29:58 -0800 | [diff] [blame] | 21 | #include "soc.h" |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 22 | #include "common.h" |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 23 | #include "vp.h" |
Paul Walmsley | 4981539 | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 24 | #include "powerdomain.h" |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 25 | #include "prm3xxx.h" |
Paul Walmsley | 4981539 | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 26 | #include "prm2xxx_3xxx.h" |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 27 | #include "cm2xxx_3xxx.h" |
| 28 | #include "prm-regbits-34xx.h" |
Tero Kristo | 0efc0f6 | 2014-02-25 15:40:30 +0200 | [diff] [blame^] | 29 | #include "cm3xxx.h" |
| 30 | #include "cm-regbits-34xx.h" |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 31 | |
| 32 | static const struct omap_prcm_irq omap3_prcm_irqs[] = { |
| 33 | OMAP_PRCM_IRQ("wkup", 0, 0), |
| 34 | OMAP_PRCM_IRQ("io", 9, 1), |
| 35 | }; |
| 36 | |
| 37 | static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { |
| 38 | .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET, |
| 39 | .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET, |
| 40 | .nr_regs = 1, |
| 41 | .irqs = omap3_prcm_irqs, |
| 42 | .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), |
| 43 | .irq = 11 + OMAP_INTC_START, |
| 44 | .read_pending_irqs = &omap3xxx_prm_read_pending_irqs, |
| 45 | .ocp_barrier = &omap3xxx_prm_ocp_barrier, |
| 46 | .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, |
| 47 | .restore_irqen = &omap3xxx_prm_restore_irqen, |
Tero Kristo | 8124365 | 2014-03-31 18:15:43 +0300 | [diff] [blame] | 48 | .reconfigure_io_chain = &omap3xxx_prm_reconfigure_io_chain, |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 49 | }; |
| 50 | |
Paul Walmsley | 2bb2a5d | 2012-10-21 01:01:13 -0600 | [diff] [blame] | 51 | /* |
| 52 | * omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware |
| 53 | * register (which are specific to OMAP3xxx SoCs) to reset source ID |
| 54 | * bit shifts (which is an OMAP SoC-independent enumeration) |
| 55 | */ |
| 56 | static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = { |
| 57 | { OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT }, |
| 58 | { OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT }, |
| 59 | { OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT }, |
| 60 | { OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, |
| 61 | { OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, |
| 62 | { OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT }, |
| 63 | { OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT, |
| 64 | OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT }, |
| 65 | { OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT, |
| 66 | OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT }, |
| 67 | { OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT }, |
| 68 | { OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT }, |
| 69 | { -1, -1 }, |
| 70 | }; |
| 71 | |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 72 | /* PRM VP */ |
| 73 | |
| 74 | /* |
| 75 | * struct omap3_vp - OMAP3 VP register access description. |
| 76 | * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg |
| 77 | */ |
| 78 | struct omap3_vp { |
| 79 | u32 tranxdone_status; |
| 80 | }; |
| 81 | |
| 82 | static struct omap3_vp omap3_vp[] = { |
| 83 | [OMAP3_VP_VDD_MPU_ID] = { |
| 84 | .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK, |
| 85 | }, |
| 86 | [OMAP3_VP_VDD_CORE_ID] = { |
| 87 | .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK, |
| 88 | }, |
| 89 | }; |
| 90 | |
| 91 | #define MAX_VP_ID ARRAY_SIZE(omap3_vp); |
| 92 | |
| 93 | u32 omap3_prm_vp_check_txdone(u8 vp_id) |
| 94 | { |
| 95 | struct omap3_vp *vp = &omap3_vp[vp_id]; |
| 96 | u32 irqstatus; |
| 97 | |
| 98 | irqstatus = omap2_prm_read_mod_reg(OCP_MOD, |
| 99 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 100 | return irqstatus & vp->tranxdone_status; |
| 101 | } |
| 102 | |
| 103 | void omap3_prm_vp_clear_txdone(u8 vp_id) |
| 104 | { |
| 105 | struct omap3_vp *vp = &omap3_vp[vp_id]; |
| 106 | |
| 107 | omap2_prm_write_mod_reg(vp->tranxdone_status, |
| 108 | OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 109 | } |
| 110 | |
| 111 | u32 omap3_prm_vcvp_read(u8 offset) |
| 112 | { |
| 113 | return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); |
| 114 | } |
| 115 | |
| 116 | void omap3_prm_vcvp_write(u32 val, u8 offset) |
| 117 | { |
| 118 | omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); |
| 119 | } |
| 120 | |
| 121 | u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) |
| 122 | { |
| 123 | return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); |
| 124 | } |
| 125 | |
| 126 | /** |
Paul Walmsley | d08cce6 | 2012-10-29 20:55:46 -0600 | [diff] [blame] | 127 | * omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC |
| 128 | * |
| 129 | * Set the DPLL3 reset bit, which should reboot the SoC. This is the |
| 130 | * recommended way to restart the SoC, considering Errata i520. No |
| 131 | * return value. |
| 132 | */ |
| 133 | void omap3xxx_prm_dpll3_reset(void) |
| 134 | { |
| 135 | omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, |
| 136 | OMAP2_RM_RSTCTRL); |
| 137 | /* OCP barrier */ |
| 138 | omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL); |
| 139 | } |
| 140 | |
| 141 | /** |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 142 | * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events |
| 143 | * @events: ptr to a u32, preallocated by caller |
| 144 | * |
| 145 | * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM |
| 146 | * MPU IRQs, and store the result into the u32 pointed to by @events. |
| 147 | * No return value. |
| 148 | */ |
| 149 | void omap3xxx_prm_read_pending_irqs(unsigned long *events) |
| 150 | { |
| 151 | u32 mask, st; |
| 152 | |
| 153 | /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */ |
| 154 | mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
| 155 | st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 156 | |
| 157 | events[0] = mask & st; |
| 158 | } |
| 159 | |
| 160 | /** |
| 161 | * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete |
| 162 | * |
| 163 | * Force any buffered writes to the PRM IP block to complete. Needed |
| 164 | * by the PRM IRQ handler, which reads and writes directly to the IP |
| 165 | * block, to avoid race conditions after acknowledging or clearing IRQ |
| 166 | * bits. No return value. |
| 167 | */ |
| 168 | void omap3xxx_prm_ocp_barrier(void) |
| 169 | { |
| 170 | omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); |
| 171 | } |
| 172 | |
| 173 | /** |
| 174 | * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg |
| 175 | * @saved_mask: ptr to a u32 array to save IRQENABLE bits |
| 176 | * |
| 177 | * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask |
| 178 | * must be allocated by the caller. Intended to be used in the PRM |
| 179 | * interrupt handler suspend callback. The OCP barrier is needed to |
| 180 | * ensure the write to disable PRM interrupts reaches the PRM before |
| 181 | * returning; otherwise, spurious interrupts might occur. No return |
| 182 | * value. |
| 183 | */ |
| 184 | void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask) |
| 185 | { |
| 186 | saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD, |
| 187 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
| 188 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
| 189 | |
| 190 | /* OCP barrier */ |
| 191 | omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); |
| 192 | } |
| 193 | |
| 194 | /** |
| 195 | * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args |
| 196 | * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously |
| 197 | * |
| 198 | * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended |
| 199 | * to be used in the PRM interrupt handler resume callback to restore |
| 200 | * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP |
| 201 | * barrier should be needed here; any pending PRM interrupts will fire |
| 202 | * once the writes reach the PRM. No return value. |
| 203 | */ |
| 204 | void omap3xxx_prm_restore_irqen(u32 *saved_mask) |
| 205 | { |
| 206 | omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, |
| 207 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
| 208 | } |
| 209 | |
| 210 | /** |
Tero Kristo | 0efc0f6 | 2014-02-25 15:40:30 +0200 | [diff] [blame^] | 211 | * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt |
| 212 | * @module: PRM module to clear wakeups from |
| 213 | * @regs: register set to clear, 1 or 3 |
| 214 | * @ignore_bits: wakeup status bits to ignore |
| 215 | * |
| 216 | * The purpose of this function is to clear any wake-up events latched |
| 217 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event |
| 218 | * may occur whilst attempting to clear a PM_WKST_x register and thus |
| 219 | * set another bit in this register. A while loop is used to ensure |
| 220 | * that any peripheral wake-up events occurring while attempting to |
| 221 | * clear the PM_WKST_x are detected and cleared. |
| 222 | */ |
| 223 | int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) |
| 224 | { |
| 225 | u32 wkst, fclk, iclk, clken; |
| 226 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
| 227 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; |
| 228 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; |
| 229 | u16 grpsel_off = (regs == 3) ? |
| 230 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; |
| 231 | int c = 0; |
| 232 | |
| 233 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
| 234 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); |
| 235 | wkst &= ~ignore_bits; |
| 236 | if (wkst) { |
| 237 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
| 238 | fclk = omap2_cm_read_mod_reg(module, fclk_off); |
| 239 | while (wkst) { |
| 240 | clken = wkst; |
| 241 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
| 242 | /* |
| 243 | * For USBHOST, we don't know whether HOST1 or |
| 244 | * HOST2 woke us up, so enable both f-clocks |
| 245 | */ |
| 246 | if (module == OMAP3430ES2_USBHOST_MOD) |
| 247 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; |
| 248 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
| 249 | omap2_prm_write_mod_reg(wkst, module, wkst_off); |
| 250 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
| 251 | wkst &= ~ignore_bits; |
| 252 | c++; |
| 253 | } |
| 254 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
| 255 | omap2_cm_write_mod_reg(fclk, module, fclk_off); |
| 256 | } |
| 257 | |
| 258 | return c; |
| 259 | } |
| 260 | |
| 261 | /** |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 262 | * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain |
| 263 | * |
| 264 | * Clear any previously-latched I/O wakeup events and ensure that the |
| 265 | * I/O wakeup gates are aligned with the current mux settings. Works |
| 266 | * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then |
| 267 | * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No |
| 268 | * return value. |
| 269 | */ |
| 270 | void omap3xxx_prm_reconfigure_io_chain(void) |
| 271 | { |
| 272 | int i = 0; |
| 273 | |
| 274 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
| 275 | PM_WKEN); |
| 276 | |
| 277 | omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) & |
| 278 | OMAP3430_ST_IO_CHAIN_MASK, |
| 279 | MAX_IOPAD_LATCH_TIME, i); |
| 280 | if (i == MAX_IOPAD_LATCH_TIME) |
| 281 | pr_warn("PRM: I/O chain clock line assertion timed out\n"); |
| 282 | |
| 283 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
| 284 | PM_WKEN); |
| 285 | |
| 286 | omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, |
| 287 | PM_WKST); |
| 288 | |
| 289 | omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST); |
| 290 | } |
| 291 | |
| 292 | /** |
| 293 | * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches |
| 294 | * |
| 295 | * Activates the I/O wakeup event latches and allows events logged by |
| 296 | * those latches to signal a wakeup event to the PRCM. For I/O |
| 297 | * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux |
| 298 | * registers, and omap3xxx_prm_reconfigure_io_chain() must be called. |
| 299 | * No return value. |
| 300 | */ |
| 301 | static void __init omap3xxx_prm_enable_io_wakeup(void) |
| 302 | { |
Tero Kristo | 2541d15 | 2014-03-31 18:15:44 +0300 | [diff] [blame] | 303 | if (prm_features & PRM_HAS_IO_WAKEUP) |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 304 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
| 305 | PM_WKEN); |
| 306 | } |
| 307 | |
Paul Walmsley | 2bb2a5d | 2012-10-21 01:01:13 -0600 | [diff] [blame] | 308 | /** |
| 309 | * omap3xxx_prm_read_reset_sources - return the last SoC reset source |
| 310 | * |
| 311 | * Return a u32 representing the last reset sources of the SoC. The |
| 312 | * returned reset source bits are standardized across OMAP SoCs. |
| 313 | */ |
| 314 | static u32 omap3xxx_prm_read_reset_sources(void) |
| 315 | { |
| 316 | struct prm_reset_src_map *p; |
| 317 | u32 r = 0; |
| 318 | u32 v; |
| 319 | |
| 320 | v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST); |
| 321 | |
| 322 | p = omap3xxx_prm_reset_src_map; |
| 323 | while (p->reg_shift >= 0 && p->std_shift >= 0) { |
| 324 | if (v & (1 << p->reg_shift)) |
| 325 | r |= 1 << p->std_shift; |
| 326 | p++; |
| 327 | } |
| 328 | |
| 329 | return r; |
| 330 | } |
| 331 | |
Paul Walmsley | 4981539 | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 332 | /* Powerdomain low-level functions */ |
| 333 | |
Paul Walmsley | 7e7fff8 | 2012-12-28 02:10:44 -0700 | [diff] [blame] | 334 | static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) |
| 335 | { |
| 336 | omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, |
| 337 | (pwrst << OMAP_POWERSTATE_SHIFT), |
| 338 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); |
| 339 | return 0; |
| 340 | } |
| 341 | |
| 342 | static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) |
| 343 | { |
| 344 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 345 | OMAP2_PM_PWSTCTRL, |
| 346 | OMAP_POWERSTATE_MASK); |
| 347 | } |
| 348 | |
| 349 | static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm) |
| 350 | { |
| 351 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 352 | OMAP2_PM_PWSTST, |
| 353 | OMAP_POWERSTATEST_MASK); |
| 354 | } |
| 355 | |
Paul Walmsley | 4981539 | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 356 | /* Applicable only for OMAP3. Not supported on OMAP2 */ |
| 357 | static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) |
| 358 | { |
| 359 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 360 | OMAP3430_PM_PREPWSTST, |
| 361 | OMAP3430_LASTPOWERSTATEENTERED_MASK); |
| 362 | } |
| 363 | |
| 364 | static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) |
| 365 | { |
| 366 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 367 | OMAP2_PM_PWSTST, |
| 368 | OMAP3430_LOGICSTATEST_MASK); |
| 369 | } |
| 370 | |
| 371 | static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) |
| 372 | { |
| 373 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 374 | OMAP2_PM_PWSTCTRL, |
| 375 | OMAP3430_LOGICSTATEST_MASK); |
| 376 | } |
| 377 | |
| 378 | static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) |
| 379 | { |
| 380 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 381 | OMAP3430_PM_PREPWSTST, |
| 382 | OMAP3430_LASTLOGICSTATEENTERED_MASK); |
| 383 | } |
| 384 | |
| 385 | static int omap3_get_mem_bank_lastmemst_mask(u8 bank) |
| 386 | { |
| 387 | switch (bank) { |
| 388 | case 0: |
| 389 | return OMAP3430_LASTMEM1STATEENTERED_MASK; |
| 390 | case 1: |
| 391 | return OMAP3430_LASTMEM2STATEENTERED_MASK; |
| 392 | case 2: |
| 393 | return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; |
| 394 | case 3: |
| 395 | return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; |
| 396 | default: |
| 397 | WARN_ON(1); /* should never happen */ |
| 398 | return -EEXIST; |
| 399 | } |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) |
| 404 | { |
| 405 | u32 m; |
| 406 | |
| 407 | m = omap3_get_mem_bank_lastmemst_mask(bank); |
| 408 | |
| 409 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
| 410 | OMAP3430_PM_PREPWSTST, m); |
| 411 | } |
| 412 | |
| 413 | static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) |
| 414 | { |
| 415 | omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); |
| 416 | return 0; |
| 417 | } |
| 418 | |
| 419 | static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) |
| 420 | { |
| 421 | return omap2_prm_rmw_mod_reg_bits(0, |
| 422 | 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, |
| 423 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); |
| 424 | } |
| 425 | |
| 426 | static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) |
| 427 | { |
| 428 | return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, |
| 429 | 0, pwrdm->prcm_offs, |
| 430 | OMAP2_PM_PWSTCTRL); |
| 431 | } |
| 432 | |
| 433 | struct pwrdm_ops omap3_pwrdm_operations = { |
Paul Walmsley | 7e7fff8 | 2012-12-28 02:10:44 -0700 | [diff] [blame] | 434 | .pwrdm_set_next_pwrst = omap3_pwrdm_set_next_pwrst, |
| 435 | .pwrdm_read_next_pwrst = omap3_pwrdm_read_next_pwrst, |
| 436 | .pwrdm_read_pwrst = omap3_pwrdm_read_pwrst, |
Paul Walmsley | 4981539 | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 437 | .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, |
| 438 | .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, |
| 439 | .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, |
| 440 | .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, |
| 441 | .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, |
| 442 | .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, |
| 443 | .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, |
| 444 | .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, |
| 445 | .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, |
| 446 | .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst, |
| 447 | .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst, |
| 448 | .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar, |
| 449 | .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar, |
| 450 | .pwrdm_wait_transition = omap2_pwrdm_wait_transition, |
| 451 | }; |
| 452 | |
| 453 | /* |
| 454 | * |
| 455 | */ |
| 456 | |
Tero Kristo | b550e47 | 2014-03-31 18:15:45 +0300 | [diff] [blame] | 457 | static int omap3xxx_prm_late_init(void); |
| 458 | |
Paul Walmsley | 2bb2a5d | 2012-10-21 01:01:13 -0600 | [diff] [blame] | 459 | static struct prm_ll_data omap3xxx_prm_ll_data = { |
| 460 | .read_reset_sources = &omap3xxx_prm_read_reset_sources, |
Tero Kristo | b550e47 | 2014-03-31 18:15:45 +0300 | [diff] [blame] | 461 | .late_init = &omap3xxx_prm_late_init, |
Paul Walmsley | 2bb2a5d | 2012-10-21 01:01:13 -0600 | [diff] [blame] | 462 | }; |
| 463 | |
Paul Walmsley | 63a293e | 2012-11-21 16:15:16 -0700 | [diff] [blame] | 464 | int __init omap3xxx_prm_init(void) |
| 465 | { |
Tero Kristo | 2541d15 | 2014-03-31 18:15:44 +0300 | [diff] [blame] | 466 | if (omap3_has_io_wakeup()) |
| 467 | prm_features |= PRM_HAS_IO_WAKEUP; |
Paul Walmsley | 63a293e | 2012-11-21 16:15:16 -0700 | [diff] [blame] | 468 | |
| 469 | return prm_register(&omap3xxx_prm_ll_data); |
| 470 | } |
| 471 | |
Tony Lindgren | ea351c1 | 2014-05-16 15:26:22 -0700 | [diff] [blame] | 472 | static int omap3xxx_prm_late_init(void) |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 473 | { |
| 474 | int ret; |
| 475 | |
Tero Kristo | 2541d15 | 2014-03-31 18:15:44 +0300 | [diff] [blame] | 476 | if (!(prm_features & PRM_HAS_IO_WAKEUP)) |
Paul Walmsley | 139563a | 2012-10-21 01:01:10 -0600 | [diff] [blame] | 477 | return 0; |
| 478 | |
| 479 | omap3xxx_prm_enable_io_wakeup(); |
| 480 | ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); |
| 481 | if (!ret) |
| 482 | irq_set_status_flags(omap_prcm_event_to_irq("io"), |
| 483 | IRQ_NOAUTOEN); |
| 484 | |
| 485 | return ret; |
| 486 | } |
Paul Walmsley | 2bb2a5d | 2012-10-21 01:01:13 -0600 | [diff] [blame] | 487 | |
| 488 | static void __exit omap3xxx_prm_exit(void) |
| 489 | { |
Tero Kristo | d8871cd | 2014-05-11 19:54:58 -0600 | [diff] [blame] | 490 | prm_unregister(&omap3xxx_prm_ll_data); |
Paul Walmsley | 2bb2a5d | 2012-10-21 01:01:13 -0600 | [diff] [blame] | 491 | } |
| 492 | __exitcall(omap3xxx_prm_exit); |