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gerrit-public.fairphone.software / kernel / msm-4.9 / 0f04afb59565c3029563b9a79b3513c9f3327a27 / . / include / asm-mips / serial.h
blob: ce1043530e5978121d267d3db05cf62cfb953662 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SERIAL_H
10#define _ASM_SERIAL_H
11
12#include <linux/config.h>
13
14/*
15 * This assumes you have a 1.8432 MHz clock for your UART.
16 *
17 * It'd be nice if someone built a serial card with a 24.576 MHz
18 * clock, since the 16550A is capable of handling a top speed of 1.5
19 * megabits/second; but this requires the faster clock.
20 */
21#define BASE_BAUD (1843200 / 16)
22
23/* Standard COM flags (except for COM4, because of the 8514 problem) */
24#ifdef CONFIG_SERIAL_DETECT_IRQ
25#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
26#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
27#else
28#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
30#endif
31
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]32#ifdef CONFIG_MACH_JAZZ
33#include <asm/jazz.h>
34
35#ifndef CONFIG_OLIVETTI_M700
36 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
37 exactly which ones ... XXX */
38#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
39#else
40/* but the M700 isn't such a strange beast */
41#define JAZZ_BASE_BAUD BASE_BAUD
42#endif
43
44#define _JAZZ_SERIAL_INIT(int, base) \
45 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
46 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
47 .io_type = SERIAL_IO_MEM }
48#define JAZZ_SERIAL_PORT_DEFNS \
49 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
50 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
51#else
52#define JAZZ_SERIAL_PORT_DEFNS
53#endif
54
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]55/*
56 * Both Galileo boards have the same UART mappings.
57 */
58#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
59#include <asm/galileo-boards/ev96100.h>
60#include <asm/galileo-boards/ev96100int.h>
61#define EV96100_SERIAL_PORT_DEFNS \
62 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
63 .flags = STD_COM_FLAGS, \
64 .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
65 .io_type = SERIAL_IO_MEM }, \
66 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
67 .flags = STD_COM_FLAGS, \
68 .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
69 .io_type = SERIAL_IO_MEM },
70#else
71#define EV96100_SERIAL_PORT_DEFNS
72#endif
73
74#ifdef CONFIG_MIPS_ITE8172
75#include <asm/it8172/it8172.h>
76#include <asm/it8172/it8172_int.h>
77#include <asm/it8712.h>
78#define ITE_SERIAL_PORT_DEFNS \
79 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
80 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
81 { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
82 .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
83 /* Smart Card Reader 0 */ \
84 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
85 .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
86 /* Smart Card Reader 1 */ \
87 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
88 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
89#else
90#define ITE_SERIAL_PORT_DEFNS
91#endif
92
93#ifdef CONFIG_MIPS_IVR
94#include <asm/it8172/it8172.h>
95#include <asm/it8172/it8172_int.h>
96#define IVR_SERIAL_PORT_DEFNS \
97 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
98 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
99 /* Smart Card Reader 1 */ \
100 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
101 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
102#else
103#define IVR_SERIAL_PORT_DEFNS
104#endif
105
106#ifdef CONFIG_TOSHIBA_JMR3927
107#include <asm/jmr3927/jmr3927.h>
108#define TXX927_SERIAL_PORT_DEFNS \
109 { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
110 .flags = UART0_FLAGS, .type = 1 }, \
111 { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
112 .flags = UART1_FLAGS, .type = 1 },
113#else
114#define TXX927_SERIAL_PORT_DEFNS
115#endif
116
117#ifdef CONFIG_SERIAL_AU1X00
118#include <asm/mach-au1x00/au1000.h>
119#ifdef CONFIG_SOC_AU1000
120#define AU1000_SERIAL_PORT_DEFNS \
121 { .baud_base = 0, .port = UART0_ADDR, \
122 .iomem_base = (unsigned char *)UART0_ADDR, \
123 .irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
124 .iomem_reg_shift = 2 }, \
125 { .baud_base = 0, .port = UART1_ADDR, \
126 .iomem_base = (unsigned char *)UART1_ADDR, \
127 .irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
128 .iomem_reg_shift = 2 }, \
129 { .baud_base = 0, .port = UART2_ADDR, \
130 .iomem_base = (unsigned char *)UART2_ADDR, \
131 .irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
132 .iomem_reg_shift = 2 }, \
133 { .baud_base = 0, .port = UART3_ADDR, \
134 .iomem_base = (unsigned char *)UART3_ADDR, \
135 .irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
136 .iomem_reg_shift = 2 },
137#endif
138
139#ifdef CONFIG_SOC_AU1500
140#define AU1000_SERIAL_PORT_DEFNS \
141 { .baud_base = 0, .port = UART0_ADDR, \
142 .iomem_base = (unsigned char *)UART0_ADDR, \
143 .irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
144 .iomem_reg_shift = 2 }, \
145 { .baud_base = 0, .port = UART3_ADDR, \
146 .iomem_base = (unsigned char *)UART3_ADDR, \
147 .irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
148 .iomem_reg_shift = 2 },
149#endif
150
151#ifdef CONFIG_SOC_AU1100
152#define AU1000_SERIAL_PORT_DEFNS \
153 { .baud_base = 0, .port = UART0_ADDR, \
154 .iomem_base = (unsigned char *)UART0_ADDR, \
155 .irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
156 .iomem_reg_shift = 2 }, \
157 { .baud_base = 0, .port = UART1_ADDR, \
158 .iomem_base = (unsigned char *)UART1_ADDR, \
159 .irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
160 .iomem_reg_shift = 2 }, \
161 { .baud_base = 0, .port = UART3_ADDR, \
162 .iomem_base = (unsigned char *)UART3_ADDR, \
163 .irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
164 .iomem_reg_shift = 2 },
165#endif
166
167#ifdef CONFIG_SOC_AU1550
168#define AU1000_SERIAL_PORT_DEFNS \
169 { .baud_base = 0, .port = UART0_ADDR, \
170 .iomem_base = (unsigned char *)UART0_ADDR, \
171 .irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
172 .iomem_reg_shift = 2 }, \
173 { .baud_base = 0, .port = UART1_ADDR, \
174 .iomem_base = (unsigned char *)UART1_ADDR, \
175 .irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
176 .iomem_reg_shift = 2 }, \
177 { .baud_base = 0, .port = UART3_ADDR, \
178 .iomem_base = (unsigned char *)UART3_ADDR, \
179 .irq = AU1550_UART3_INT, .flags = STD_COM_FLAGS,\
180 .iomem_reg_shift = 2 },
181#endif
182
183#ifdef CONFIG_SOC_AU1200
184#define AU1000_SERIAL_PORT_DEFNS \
185 { .baud_base = 0, .port = UART0_ADDR, \
186 .iomem_base = (unsigned char *)UART0_ADDR, \
187 .irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
188 .iomem_reg_shift = 2 }, \
189 { .baud_base = 0, .port = UART1_ADDR, \
190 .iomem_base = (unsigned char *)UART1_ADDR, \
191 .irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
192 .iomem_reg_shift = 2 },
193#endif
194
195#else
196#define AU1000_SERIAL_PORT_DEFNS
197#endif
198
199#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
200#define STD_SERIAL_PORT_DEFNS \
201 /* UART CLK PORT IRQ FLAGS */ \
202 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
203 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
204 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
205 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
206
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]207#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
208#define STD_SERIAL_PORT_DEFNS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]209#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
210
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]211#ifdef CONFIG_MOMENCO_JAGUAR_ATX
212/* Ordinary NS16552 duart with a 20MHz crystal. */
213#define JAGUAR_ATX_UART_CLK 20000000
214#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
215
216#define JAGUAR_ATX_SERIAL1_IRQ 6
217#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
218
219#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
Ralf Baechle0f04afb2005-03-01 10:38:58 +0000[diff] [blame^]220 { .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
221 .flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
222 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]223 io_type: SERIAL_IO_MEM }
224#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
225 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
226#else
227#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
228#endif
229
230#ifdef CONFIG_MOMENCO_OCELOT_3
231#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
232#define OCELOT_3_SERIAL_IRQ 6
233#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
234
235#define _OCELOT_3_SERIAL_INIT(int, base) \
Ralf Baechle0f04afb2005-03-01 10:38:58 +0000[diff] [blame^]236 { .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
237 .flags = STD_COM_FLAGS, \
238 .iomem_base = (u8 *) base, iomem_reg_shift: 2, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]239 io_type: SERIAL_IO_MEM }
240
241#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
242 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
243#else
244#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
245#endif
246
247#ifdef CONFIG_MOMENCO_OCELOT
248/* Ordinary NS16552 duart with a 20MHz crystal. */
249#define OCELOT_BASE_BAUD ( 20000000 / 16 )
250
251#define OCELOT_SERIAL1_IRQ 4
252#define OCELOT_SERIAL1_BASE 0xe0001020
253
254#define _OCELOT_SERIAL_INIT(int, base) \
255 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
256 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
257 .io_type = SERIAL_IO_MEM }
258#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
259 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
260#else
261#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
262#endif
263
264#ifdef CONFIG_MOMENCO_OCELOT_G
265/* Ordinary NS16552 duart with a 20MHz crystal. */
266#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
267
268#define OCELOT_G_SERIAL1_IRQ 4
269#if 0
270#define OCELOT_G_SERIAL1_BASE 0xe0001020
271#else
272#define OCELOT_G_SERIAL1_BASE 0xfd000020
273#endif
274
275#define _OCELOT_G_SERIAL_INIT(int, base) \
276 { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
277 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
278 .io_type = SERIAL_IO_MEM }
279#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
280 _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
281#else
282#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
283#endif
284
285#ifdef CONFIG_MOMENCO_OCELOT_C
286/* Ordinary NS16552 duart with a 20MHz crystal. */
287#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
288
289#define OCELOT_C_SERIAL1_IRQ 80
290#define OCELOT_C_SERIAL1_BASE 0xfd000020
291
292#define OCELOT_C_SERIAL2_IRQ 81
293#define OCELOT_C_SERIAL2_BASE 0xfd000000
294
295#define _OCELOT_C_SERIAL_INIT(int, base) \
296 { .baud_base = OCELOT_C_BASE_BAUD, \
297 .irq = (int), \
298 .flags = STD_COM_FLAGS, \
299 .iomem_base = (u8 *) base, \
300 .iomem_reg_shift = 2, \
301 .io_type = SERIAL_IO_MEM \
302 }
303#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
304 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
305 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
306#else
307#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
308#endif
309
310#ifdef CONFIG_DDB5477
311#include <asm/ddb5xxx/ddb5477.h>
312#define DDB5477_SERIAL_PORT_DEFNS \
313 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
314 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
315 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
316 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
317 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
318 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
319#else
320#define DDB5477_SERIAL_PORT_DEFNS
321#endif
322
323#ifdef CONFIG_SGI_IP32
324/*
325 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
326 * They are initialized in ip32_setup
327 */
328#define IP32_SERIAL_PORT_DEFNS \
329 {},{},
330#else
331#define IP32_SERIAL_PORT_DEFNS
332#endif /* CONFIG_SGI_IP32 */
333
334#define SERIAL_PORT_DFNS \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]335 DDB5477_SERIAL_PORT_DEFNS \
336 EV96100_SERIAL_PORT_DEFNS \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]337 IP32_SERIAL_PORT_DEFNS \
338 ITE_SERIAL_PORT_DEFNS \
339 IVR_SERIAL_PORT_DEFNS \
340 JAZZ_SERIAL_PORT_DEFNS \
341 STD_SERIAL_PORT_DEFNS \
342 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
343 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
344 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
345 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
346 TXX927_SERIAL_PORT_DEFNS \
347 AU1000_SERIAL_PORT_DEFNS
348
349#endif /* _ASM_SERIAL_H */