Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2000, 07 MIPS Technologies, Inc. |
| 7 | * |
| 8 | * Multiprocessor Subsystem Register Definitions |
| 9 | * |
| 10 | */ |
| 11 | #ifndef _ASM_GCMPREGS_H |
| 12 | #define _ASM_GCMPREGS_H |
| 13 | |
| 14 | |
| 15 | /* Offsets to major blocks within GCMP from GCMP base */ |
| 16 | #define GCMP_GCB_OFS 0x0000 /* Global Control Block */ |
| 17 | #define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */ |
| 18 | #define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */ |
| 19 | #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ |
| 20 | |
| 21 | /* Offsets to individual GCMP registers from GCMP base */ |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 22 | #define GCMPOFS(block, tag, reg) \ |
| 23 | (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) |
| 24 | #define GCMPOFSn(block, tag, reg, n) \ |
| 25 | (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n)) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 26 | |
| 27 | #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 28 | #define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 29 | #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) |
| 30 | #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) |
| 31 | #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) |
| 32 | |
| 33 | /* GCMP register access */ |
| 34 | #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 35 | #define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 36 | #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) |
| 37 | #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) |
| 38 | #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) |
| 39 | |
| 40 | /* Mask generation */ |
| 41 | #define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF) |
| 42 | #define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits) |
| 43 | #define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits) |
| 44 | #define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits) |
| 45 | |
| 46 | /* GCB registers */ |
| 47 | #define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ |
| 48 | #define GCMP_GCB_GC_NUMIOCU_SHF 8 |
| 49 | #define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) |
| 50 | #define GCMP_GCB_GC_NUMCORES_SHF 0 |
| 51 | #define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) |
| 52 | #define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ |
| 53 | #define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 |
| 54 | #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) |
| 55 | #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 |
| 56 | #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 57 | #define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 |
| 58 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 |
| 59 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 |
| 60 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 61 | #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ |
| 62 | #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ |
| 63 | #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 |
| 64 | #define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) |
| 65 | #define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ |
| 66 | #define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ |
| 67 | #define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ |
| 68 | #define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 |
| 69 | #define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) |
| 70 | #define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 |
| 71 | #define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) |
| 72 | #define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ |
| 73 | #define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ |
| 74 | #define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 |
| 75 | #define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) |
| 76 | #define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ |
| 77 | #define GCMP_GCB_GICBA_BASE_SHF 17 |
| 78 | #define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) |
| 79 | #define GCMP_GCB_GICBA_EN_SHF 0 |
| 80 | #define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) |
| 81 | |
| 82 | /* GCB Regions */ |
| 83 | #define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ |
| 84 | #define GCMP_GCB_CMxBASE_BASE_SHF 16 |
| 85 | #define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) |
| 86 | #define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ |
| 87 | #define GCMP_GCB_CMxMASK_MASK_SHF 16 |
| 88 | #define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) |
| 89 | #define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 |
| 90 | #define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) |
| 91 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 |
| 92 | #define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 |
| 93 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 |
| 94 | #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 |
| 95 | |
| 96 | |
| 97 | /* Core local/Core other control block registers */ |
| 98 | #define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ |
| 99 | #define GCMP_CCB_RESETR_INRESET_SHF 0 |
| 100 | #define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) |
| 101 | #define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ |
| 102 | #define GCMP_CCB_COHCTL_DOMAIN_SHF 0 |
| 103 | #define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) |
| 104 | #define GCMP_CCB_CFG_OFS 0x0010 /* Config */ |
| 105 | #define GCMP_CCB_CFG_IOCUTYPE_SHF 10 |
| 106 | #define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) |
| 107 | #define GCMP_CCB_CFG_IOCUTYPE_CPU 0 |
| 108 | #define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 |
| 109 | #define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 |
| 110 | #define GCMP_CCB_CFG_NUMVPE_SHF 0 |
| 111 | #define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) |
| 112 | #define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ |
| 113 | #define GCMP_CCB_OTHER_CORENUM_SHF 16 |
| 114 | #define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) |
| 115 | #define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ |
| 116 | #define GCMP_CCB_RESETBASE_BEV_SHF 12 |
| 117 | #define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) |
| 118 | #define GCMP_CCB_ID_OFS 0x0028 /* Identification */ |
| 119 | #define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ |
| 120 | #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ |
| 121 | |
Tim Anderson | 47b178b | 2009-06-17 16:25:18 -0700 | [diff] [blame] | 122 | extern int __init gcmp_probe(unsigned long, unsigned long); |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 123 | extern int __init gcmp_niocu(void); |
| 124 | extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 125 | #endif /* _ASM_GCMPREGS_H */ |