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Pete Popove3ad1c22005-03-01 06:33:16 +00001/*
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +04002 * AMD Alchemy DBAu1200 Reference Board
3 * Board register defines.
Pete Popove3ad1c22005-03-01 06:33:16 +00004 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_DB1200_H
25#define __ASM_DB1200_H
26
27#include <linux/types.h>
Manuel Lauss7e50b2b2009-10-04 14:55:26 +020028#include <asm/mach-au1x00/au1000.h>
Manuel Lauss9e39ffe2008-02-24 20:03:42 +010029#include <asm/mach-au1x00/au1xxx_psc.h>
Pete Popove3ad1c22005-03-01 06:33:16 +000030
Pete Popove3ad1c22005-03-01 06:33:16 +000031/* Bit positions for the different interrupt sources */
32#define BCSR_INT_IDE 0x0001
33#define BCSR_INT_ETH 0x0002
34#define BCSR_INT_PC0 0x0004
35#define BCSR_INT_PC0STSCHG 0x0008
36#define BCSR_INT_PC1 0x0010
37#define BCSR_INT_PC1STSCHG 0x0020
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040038#define BCSR_INT_DC 0x0040
Pete Popove3ad1c22005-03-01 06:33:16 +000039#define BCSR_INT_FLASHBUSY 0x0080
40#define BCSR_INT_PC0INSERT 0x0100
41#define BCSR_INT_PC0EJECT 0x0200
42#define BCSR_INT_PC1INSERT 0x0400
43#define BCSR_INT_PC1EJECT 0x0800
44#define BCSR_INT_SD0INSERT 0x1000
45#define BCSR_INT_SD0EJECT 0x2000
Manuel Lauss6f7c8622011-11-10 12:06:22 +000046#define BCSR_INT_SD1INSERT 0x4000
47#define BCSR_INT_SD1EJECT 0x8000
Pete Popove3ad1c22005-03-01 06:33:16 +000048
Sergei Shtylyovfcbd3b42008-04-28 19:54:38 +040049#define IDE_REG_SHIFT 5
Pete Popove3ad1c22005-03-01 06:33:16 +000050
Manuel Lauss6f7c8622011-11-10 12:06:22 +000051#define DB1200_IDE_PHYS_ADDR 0x18800000
Manuel Lauss63323ec2009-11-02 21:21:43 +010052#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
53#define DB1200_ETH_PHYS_ADDR 0x19000300
54#define DB1200_NAND_PHYS_ADDR 0x20000000
Pete Popove3ad1c22005-03-01 06:33:16 +000055
Manuel Lauss6f7c8622011-11-10 12:06:22 +000056#define PB1200_IDE_PHYS_ADDR 0x0C800000
57#define PB1200_ETH_PHYS_ADDR 0x0D000300
58#define PB1200_NAND_PHYS_ADDR 0x1C000000
59
Pete Popove3ad1c22005-03-01 06:33:16 +000060/*
Sergei Shtylyovc3d1d5c2008-04-30 23:29:04 +040061 * External Interrupts for DBAu1200 as of 8/6/2004.
Ralf Baechle9d360ab2007-10-17 15:38:30 +010062 * Bit positions in the CPLD registers can be calculated by taking
63 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
64 *
65 * Example: IDE bis pos is = 64 - 64
66 * ETH bit pos is = 65 - 64
Pete Popove3ad1c22005-03-01 06:33:16 +000067 */
Manuel Lauss63323ec2009-11-02 21:21:43 +010068enum external_db1200_ints {
Ralf Baechle9d360ab2007-10-17 15:38:30 +010069 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
Pete Popove3ad1c22005-03-01 06:33:16 +000070
Ralf Baechle9d360ab2007-10-17 15:38:30 +010071 DB1200_IDE_INT = DB1200_INT_BEGIN,
72 DB1200_ETH_INT,
73 DB1200_PC0_INT,
74 DB1200_PC0_STSCHG_INT,
75 DB1200_PC1_INT,
76 DB1200_PC1_STSCHG_INT,
77 DB1200_DC_INT,
78 DB1200_FLASHBUSY_INT,
79 DB1200_PC0_INSERT_INT,
80 DB1200_PC0_EJECT_INT,
81 DB1200_PC1_INSERT_INT,
82 DB1200_PC1_EJECT_INT,
83 DB1200_SD0_INSERT_INT,
84 DB1200_SD0_EJECT_INT,
Manuel Lauss6f7c8622011-11-10 12:06:22 +000085 PB1200_SD1_INSERT_INT,
86 PB1200_SD1_EJECT_INT,
Ralf Baechle9d360ab2007-10-17 15:38:30 +010087
88 DB1200_INT_END = DB1200_INT_BEGIN + 15,
89};
90
Pete Popove3ad1c22005-03-01 06:33:16 +000091#endif /* __ASM_DB1200_H */