| Daniel Laird | edb6310 | 2008-06-16 15:49:21 +0100 | [diff] [blame] | 1 | |
| 2 | /* |
| 3 | * irq.h: IRQ mappings for PNX833X. |
| 4 | * |
| 5 | * Copyright 2008 NXP Semiconductors |
| 6 | * Chris Steel <chris.steel@nxp.com> |
| 7 | * Daniel Laird <daniel.j.laird@nxp.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 22 | */ |
| 23 | |
| 24 | #ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H |
| 25 | #define __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H |
| 26 | /* |
| 27 | * The "IRQ numbers" are completely virtual. |
| 28 | * |
| 29 | * In PNX8330/1, we have 48 interrupt lines, numbered from 1 to 48. |
| 30 | * Let's use numbers 1..48 for PIC interrupts, number 0 for timer interrupt, |
| 31 | * numbers 49..64 for (virtual) GPIO interrupts. |
| 32 | * |
| 33 | * In PNX8335, we have 57 interrupt lines, numbered from 1 to 57, |
| 34 | * connected to PIC, which uses core hardware interrupt 2, and also |
| 35 | * a timer interrupt through hardware interrupt 5. |
| 36 | * Let's use numbers 1..64 for PIC interrupts, number 0 for timer interrupt, |
| 37 | * numbers 65..80 for (virtual) GPIO interrupts. |
| 38 | * |
| 39 | */ |
| 40 | #include <irq.h> |
| 41 | |
| 42 | #define PNX833X_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) |
| 43 | |
| 44 | /* Interrupts supported by PIC */ |
| 45 | #define PNX833X_PIC_I2C0_INT (PNX833X_PIC_IRQ_BASE + 1) |
| 46 | #define PNX833X_PIC_I2C1_INT (PNX833X_PIC_IRQ_BASE + 2) |
| 47 | #define PNX833X_PIC_UART0_INT (PNX833X_PIC_IRQ_BASE + 3) |
| 48 | #define PNX833X_PIC_UART1_INT (PNX833X_PIC_IRQ_BASE + 4) |
| 49 | #define PNX833X_PIC_TS_IN0_DV_INT (PNX833X_PIC_IRQ_BASE + 5) |
| 50 | #define PNX833X_PIC_TS_IN0_DMA_INT (PNX833X_PIC_IRQ_BASE + 6) |
| 51 | #define PNX833X_PIC_GPIO_INT (PNX833X_PIC_IRQ_BASE + 7) |
| 52 | #define PNX833X_PIC_AUDIO_DEC_INT (PNX833X_PIC_IRQ_BASE + 8) |
| 53 | #define PNX833X_PIC_VIDEO_DEC_INT (PNX833X_PIC_IRQ_BASE + 9) |
| 54 | #define PNX833X_PIC_CONFIG_INT (PNX833X_PIC_IRQ_BASE + 10) |
| 55 | #define PNX833X_PIC_AOI_INT (PNX833X_PIC_IRQ_BASE + 11) |
| 56 | #define PNX833X_PIC_SYNC_INT (PNX833X_PIC_IRQ_BASE + 12) |
| 57 | #define PNX8330_PIC_SPU_INT (PNX833X_PIC_IRQ_BASE + 13) |
| 58 | #define PNX8335_PIC_SATA_INT (PNX833X_PIC_IRQ_BASE + 13) |
| 59 | #define PNX833X_PIC_OSD_INT (PNX833X_PIC_IRQ_BASE + 14) |
| 60 | #define PNX833X_PIC_DISP1_INT (PNX833X_PIC_IRQ_BASE + 15) |
| 61 | #define PNX833X_PIC_DEINTERLACER_INT (PNX833X_PIC_IRQ_BASE + 16) |
| 62 | #define PNX833X_PIC_DISPLAY2_INT (PNX833X_PIC_IRQ_BASE + 17) |
| 63 | #define PNX833X_PIC_VC_INT (PNX833X_PIC_IRQ_BASE + 18) |
| 64 | #define PNX833X_PIC_SC_INT (PNX833X_PIC_IRQ_BASE + 19) |
| 65 | #define PNX833X_PIC_IDE_INT (PNX833X_PIC_IRQ_BASE + 20) |
| 66 | #define PNX833X_PIC_IDE_DMA_INT (PNX833X_PIC_IRQ_BASE + 21) |
| 67 | #define PNX833X_PIC_TS_IN1_DV_INT (PNX833X_PIC_IRQ_BASE + 22) |
| 68 | #define PNX833X_PIC_TS_IN1_DMA_INT (PNX833X_PIC_IRQ_BASE + 23) |
| 69 | #define PNX833X_PIC_SGDX_DMA_INT (PNX833X_PIC_IRQ_BASE + 24) |
| 70 | #define PNX833X_PIC_TS_OUT_INT (PNX833X_PIC_IRQ_BASE + 25) |
| 71 | #define PNX833X_PIC_IR_INT (PNX833X_PIC_IRQ_BASE + 26) |
| 72 | #define PNX833X_PIC_VMSP1_INT (PNX833X_PIC_IRQ_BASE + 27) |
| 73 | #define PNX833X_PIC_VMSP2_INT (PNX833X_PIC_IRQ_BASE + 28) |
| 74 | #define PNX833X_PIC_PIBC_INT (PNX833X_PIC_IRQ_BASE + 29) |
| 75 | #define PNX833X_PIC_TS_IN0_TRD_INT (PNX833X_PIC_IRQ_BASE + 30) |
| 76 | #define PNX833X_PIC_SGDX_TPD_INT (PNX833X_PIC_IRQ_BASE + 31) |
| 77 | #define PNX833X_PIC_USB_INT (PNX833X_PIC_IRQ_BASE + 32) |
| 78 | #define PNX833X_PIC_TS_IN1_TRD_INT (PNX833X_PIC_IRQ_BASE + 33) |
| 79 | #define PNX833X_PIC_CLOCK_INT (PNX833X_PIC_IRQ_BASE + 34) |
| 80 | #define PNX833X_PIC_SGDX_PARSER_INT (PNX833X_PIC_IRQ_BASE + 35) |
| 81 | #define PNX833X_PIC_VMSP_DMA_INT (PNX833X_PIC_IRQ_BASE + 36) |
| 82 | |
| 83 | #if defined(CONFIG_SOC_PNX8335) |
| 84 | #define PNX8335_PIC_MIU_INT (PNX833X_PIC_IRQ_BASE + 37) |
| 85 | #define PNX8335_PIC_AVCHIP_IRQ_INT (PNX833X_PIC_IRQ_BASE + 38) |
| 86 | #define PNX8335_PIC_SYNC_HD_INT (PNX833X_PIC_IRQ_BASE + 39) |
| 87 | #define PNX8335_PIC_DISP_HD_INT (PNX833X_PIC_IRQ_BASE + 40) |
| 88 | #define PNX8335_PIC_DISP_SCALER_INT (PNX833X_PIC_IRQ_BASE + 41) |
| 89 | #define PNX8335_PIC_OSD_HD1_INT (PNX833X_PIC_IRQ_BASE + 42) |
| 90 | #define PNX8335_PIC_DTL_WRITER_Y_INT (PNX833X_PIC_IRQ_BASE + 43) |
| 91 | #define PNX8335_PIC_DTL_WRITER_C_INT (PNX833X_PIC_IRQ_BASE + 44) |
| 92 | #define PNX8335_PIC_DTL_EMULATOR_Y_IR_INT (PNX833X_PIC_IRQ_BASE + 45) |
| 93 | #define PNX8335_PIC_DTL_EMULATOR_C_IR_INT (PNX833X_PIC_IRQ_BASE + 46) |
| 94 | #define PNX8335_PIC_DENC_TTX_INT (PNX833X_PIC_IRQ_BASE + 47) |
| 95 | #define PNX8335_PIC_MMI_SIF0_INT (PNX833X_PIC_IRQ_BASE + 48) |
| 96 | #define PNX8335_PIC_MMI_SIF1_INT (PNX833X_PIC_IRQ_BASE + 49) |
| 97 | #define PNX8335_PIC_MMI_CDMMU_INT (PNX833X_PIC_IRQ_BASE + 50) |
| 98 | #define PNX8335_PIC_PIBCS_INT (PNX833X_PIC_IRQ_BASE + 51) |
| 99 | #define PNX8335_PIC_ETHERNET_INT (PNX833X_PIC_IRQ_BASE + 52) |
| 100 | #define PNX8335_PIC_VMSP1_0_INT (PNX833X_PIC_IRQ_BASE + 53) |
| 101 | #define PNX8335_PIC_VMSP1_1_INT (PNX833X_PIC_IRQ_BASE + 54) |
| 102 | #define PNX8335_PIC_VMSP1_DMA_INT (PNX833X_PIC_IRQ_BASE + 55) |
| 103 | #define PNX8335_PIC_TDGR_DE_INT (PNX833X_PIC_IRQ_BASE + 56) |
| 104 | #define PNX8335_PIC_IR1_IRQ_INT (PNX833X_PIC_IRQ_BASE + 57) |
| 105 | #endif |
| 106 | |
| 107 | /* GPIO interrupts */ |
| 108 | #define PNX833X_GPIO_0_INT (PNX833X_GPIO_IRQ_BASE + 0) |
| 109 | #define PNX833X_GPIO_1_INT (PNX833X_GPIO_IRQ_BASE + 1) |
| 110 | #define PNX833X_GPIO_2_INT (PNX833X_GPIO_IRQ_BASE + 2) |
| 111 | #define PNX833X_GPIO_3_INT (PNX833X_GPIO_IRQ_BASE + 3) |
| 112 | #define PNX833X_GPIO_4_INT (PNX833X_GPIO_IRQ_BASE + 4) |
| 113 | #define PNX833X_GPIO_5_INT (PNX833X_GPIO_IRQ_BASE + 5) |
| 114 | #define PNX833X_GPIO_6_INT (PNX833X_GPIO_IRQ_BASE + 6) |
| 115 | #define PNX833X_GPIO_7_INT (PNX833X_GPIO_IRQ_BASE + 7) |
| 116 | #define PNX833X_GPIO_8_INT (PNX833X_GPIO_IRQ_BASE + 8) |
| 117 | #define PNX833X_GPIO_9_INT (PNX833X_GPIO_IRQ_BASE + 9) |
| 118 | #define PNX833X_GPIO_10_INT (PNX833X_GPIO_IRQ_BASE + 10) |
| 119 | #define PNX833X_GPIO_11_INT (PNX833X_GPIO_IRQ_BASE + 11) |
| 120 | #define PNX833X_GPIO_12_INT (PNX833X_GPIO_IRQ_BASE + 12) |
| 121 | #define PNX833X_GPIO_13_INT (PNX833X_GPIO_IRQ_BASE + 13) |
| 122 | #define PNX833X_GPIO_14_INT (PNX833X_GPIO_IRQ_BASE + 14) |
| 123 | #define PNX833X_GPIO_15_INT (PNX833X_GPIO_IRQ_BASE + 15) |
| 124 | |
| 125 | #endif |