blob: a82a4ba8de4fc2a6f27280a127a5997dfbd39637 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001
2/*********************************************************************
3 *
4 * vlsi_ir.h: VLSI82C147 PCI IrDA controller driver for Linux
5 *
6 * Version: 0.5
7 *
8 * Copyright (c) 2001-2003 Martin Diehl
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 ********************************************************************/
26
27#ifndef IRDA_VLSI_FIR_H
28#define IRDA_VLSI_FIR_H
29
30/* ================================================================
31 * compatibility stuff
32 */
33
34/* definitions not present in pci_ids.h */
35
36#ifndef PCI_CLASS_WIRELESS_IRDA
37#define PCI_CLASS_WIRELESS_IRDA 0x0d00
38#endif
39
40#ifndef PCI_CLASS_SUBCLASS_MASK
41#define PCI_CLASS_SUBCLASS_MASK 0xffff
42#endif
43
44/* in recent 2.5 interrupt handlers have non-void return value */
45#ifndef IRQ_RETVAL
46typedef void irqreturn_t;
47#define IRQ_NONE
48#define IRQ_HANDLED
49#define IRQ_RETVAL(x)
50#endif
51
52/* some stuff need to check kernelversion. Not all 2.5 stuff was present
53 * in early 2.5.x - the test is merely to separate 2.4 from 2.5
54 */
55#include <linux/version.h>
56
57#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
58
59/* PDE() introduced in 2.5.4 */
60#ifdef CONFIG_PROC_FS
61#define PDE(inode) ((inode)->u.generic_ip)
62#endif
63
64/* irda crc16 calculation exported in 2.5.42 */
65#define irda_calc_crc16(fcs,buf,len) (GOOD_FCS)
66
67/* we use this for unified pci device name access */
68#define PCIDEV_NAME(pdev) ((pdev)->name)
69
70#else /* 2.5 or later */
71
Linus Torvalds1da177e2005-04-16 15:20:36 -070072/* whatever we get from the associated struct device - bus:slot:dev.fn id */
73#define PCIDEV_NAME(pdev) (pci_name(pdev))
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75#endif
76
77/* ================================================================ */
78
79/* non-standard PCI registers */
80
81enum vlsi_pci_regs {
82 VLSI_PCI_CLKCTL = 0x40, /* chip clock input control */
83 VLSI_PCI_MSTRPAGE = 0x41, /* addr [31:24] for all busmaster cycles */
84 VLSI_PCI_IRMISC = 0x42 /* mainly legacy UART related */
85};
86
87/* ------------------------------------------ */
88
89/* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */
90
91/* Three possible clock sources: either on-chip 48MHz PLL or
92 * external clock applied to EXTCLK pin. External clock may
93 * be either 48MHz or 40MHz, which is indicated by XCKSEL.
94 * CLKSTP controls whether the selected clock source gets
95 * connected to the IrDA block.
96 *
97 * On my HP OB-800 the BIOS sets external 40MHz clock as source
98 * when IrDA enabled and I've never detected any PLL lock success.
99 * Apparently the 14.3...MHz OSC input required for the PLL to work
100 * is not connected and the 40MHz EXTCLK is provided externally.
101 * At least this is what makes the driver working for me.
102 */
103
104enum vlsi_pci_clkctl {
105
106 /* PLL control */
107
108 CLKCTL_PD_INV = 0x04, /* PD#: inverted power down signal,
109 * i.e. PLL is powered, if PD_INV set */
110 CLKCTL_LOCK = 0x40, /* (ro) set, if PLL is locked */
111
112 /* clock source selection */
113
114 CLKCTL_EXTCLK = 0x20, /* set to select external clock input, not PLL */
115 CLKCTL_XCKSEL = 0x10, /* set to indicate EXTCLK is 40MHz, not 48MHz */
116
117 /* IrDA block control */
118
119 CLKCTL_CLKSTP = 0x80, /* set to disconnect from selected clock source */
120 CLKCTL_WAKE = 0x08 /* set to enable wakeup feature: whenever IR activity
121 * is detected, PD_INV gets set(?) and CLKSTP cleared */
122};
123
124/* ------------------------------------------ */
125
126/* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */
127
128#define DMA_MASK_USED_BY_HW 0xffffffff
129#define DMA_MASK_MSTRPAGE 0x00ffffff
130#define MSTRPAGE_VALUE (DMA_MASK_MSTRPAGE >> 24)
131
132 /* PCI busmastering is somewhat special for this guy - in short:
133 *
134 * We select to operate using fixed MSTRPAGE=0, use ISA DMA
135 * address restrictions to make the PCI BM api aware of this,
136 * but ensure the hardware is dealing with real 32bit access.
137 *
138 * In detail:
139 * The chip executes normal 32bit busmaster cycles, i.e.
140 * drives all 32 address lines. These addresses however are
141 * composed of [0:23] taken from various busaddr-pointers
142 * and [24:31] taken from the MSTRPAGE register in the VLSI82C147
143 * config space. Therefore _all_ busmastering must be
144 * targeted to/from one single 16MB (busaddr-) superpage!
145 * The point is to make sure all the allocations for memory
146 * locations with busmaster access (ring descriptors, buffers)
147 * are indeed bus-mappable to the same 16MB range (for x86 this
148 * means they must reside in the same 16MB physical memory address
149 * range). The only constraint we have which supports "several objects
150 * mappable to common 16MB range" paradigma, is the old ISA DMA
151 * restriction to the first 16MB of physical address range.
152 * Hence the approach here is to enable PCI busmaster support using
153 * the correct 32bit dma-mask used by the chip. Afterwards the device's
154 * dma-mask gets restricted to 24bit, which must be honoured somehow by
155 * all allocations for memory areas to be exposed to the chip ...
156 *
157 * Note:
158 * Don't be surprised to get "Setting latency timer..." messages every
159 * time when PCI busmastering is enabled for the chip.
160 * The chip has its PCI latency timer RO fixed at 0 - which is not a
161 * problem here, because it is never requesting _burst_ transactions.
162 */
163
164/* ------------------------------------------ */
165
166/* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */
167
168/* legacy UART emulation - not used by this driver - would require:
169 * (see below for some register-value definitions)
170 *
171 * - IRMISC_UARTEN must be set to enable UART address decoding
172 * - IRMISC_UARTSEL configured
173 * - IRCFG_MASTER must be cleared
174 * - IRCFG_SIR must be set
175 * - IRENABLE_PHYANDCLOCK must be asserted 0->1 (and hence IRENABLE_SIR_ON)
176 */
177
178enum vlsi_pci_irmisc {
179
180 /* IR transceiver control */
181
182 IRMISC_IRRAIL = 0x40, /* (ro?) IR rail power indication (and control?)
183 * 0=3.3V / 1=5V. Probably set during power-on?
184 * unclear - not touched by driver */
185 IRMISC_IRPD = 0x08, /* transceiver power down, if set */
186
187 /* legacy UART control */
188
189 IRMISC_UARTTST = 0x80, /* UART test mode - "always write 0" */
190 IRMISC_UARTEN = 0x04, /* enable UART address decoding */
191
192 /* bits [1:0] IRMISC_UARTSEL to select legacy UART address */
193
194 IRMISC_UARTSEL_3f8 = 0x00,
195 IRMISC_UARTSEL_2f8 = 0x01,
196 IRMISC_UARTSEL_3e8 = 0x02,
197 IRMISC_UARTSEL_2e8 = 0x03
198};
199
200/* ================================================================ */
201
202/* registers mapped to 32 byte PCI IO space */
203
204/* note: better access all registers at the indicated u8/u16 size
205 * although some of them contain only 1 byte of information.
206 * some of them (particaluarly PROMPT and IRCFG) ignore
207 * access when using the wrong addressing mode!
208 */
209
210enum vlsi_pio_regs {
211 VLSI_PIO_IRINTR = 0x00, /* interrupt enable/request (u8, rw) */
212 VLSI_PIO_RINGPTR = 0x02, /* rx/tx ring pointer (u16, ro) */
213 VLSI_PIO_RINGBASE = 0x04, /* [23:10] of ring address (u16, rw) */
214 VLSI_PIO_RINGSIZE = 0x06, /* rx/tx ring size (u16, rw) */
215 VLSI_PIO_PROMPT = 0x08, /* triggers ring processing (u16, wo) */
216 /* 0x0a-0x0f: reserved / duplicated UART regs */
217 VLSI_PIO_IRCFG = 0x10, /* configuration select (u16, rw) */
218 VLSI_PIO_SIRFLAG = 0x12, /* BOF/EOF for filtered SIR (u16, ro) */
219 VLSI_PIO_IRENABLE = 0x14, /* enable and status register (u16, rw/ro) */
220 VLSI_PIO_PHYCTL = 0x16, /* physical layer current status (u16, ro) */
221 VLSI_PIO_NPHYCTL = 0x18, /* next physical layer select (u16, rw) */
222 VLSI_PIO_MAXPKT = 0x1a, /* [11:0] max len for packet receive (u16, rw) */
223 VLSI_PIO_RCVBCNT = 0x1c /* current receive-FIFO byte count (u16, ro) */
224 /* 0x1e-0x1f: reserved / duplicated UART regs */
225};
226
227/* ------------------------------------------ */
228
229/* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */
230
231/* enable-bits:
232 * 1 = enable / 0 = disable
233 * interrupt condition bits:
234 * set according to corresponding interrupt source
235 * (regardless of the state of the enable bits)
236 * enable bit status indicates whether interrupt gets raised
237 * write-to-clear
238 * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-)
239 */
240
241enum vlsi_pio_irintr {
242 IRINTR_ACTEN = 0x80, /* activity interrupt enable */
243 IRINTR_ACTIVITY = 0x40, /* activity monitor (traffic detected) */
244 IRINTR_RPKTEN = 0x20, /* receive packet interrupt enable*/
245 IRINTR_RPKTINT = 0x10, /* rx-packet transfered from fifo to memory finished */
246 IRINTR_TPKTEN = 0x08, /* transmit packet interrupt enable */
247 IRINTR_TPKTINT = 0x04, /* last bit of tx-packet+crc shifted to ir-pulser */
248 IRINTR_OE_EN = 0x02, /* UART rx fifo overrun error interrupt enable */
249 IRINTR_OE_INT = 0x01 /* UART rx fifo overrun error (read LSR to clear) */
250};
251
252/* we use this mask to check whether the (shared PCI) interrupt is ours */
253
254#define IRINTR_INT_MASK (IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT)
255
256/* ------------------------------------------ */
257
258/* VLSI_PIO_RINGPTR: Ring Pointer Read-Back Register (u16, ro) */
259
260/* _both_ ring pointers are indices relative to the _entire_ rx,tx-ring!
261 * i.e. the referenced descriptor is located
262 * at RINGBASE + PTR * sizeof(descr) for rx and tx
263 * therefore, the tx-pointer has offset MAX_RING_DESCR
264 */
265
266#define MAX_RING_DESCR 64 /* tx, rx rings may contain up to 64 descr each */
267
268#define RINGPTR_RX_MASK (MAX_RING_DESCR-1)
269#define RINGPTR_TX_MASK ((MAX_RING_DESCR-1)<<8)
270
271#define RINGPTR_GET_RX(p) ((p)&RINGPTR_RX_MASK)
272#define RINGPTR_GET_TX(p) (((p)&RINGPTR_TX_MASK)>>8)
273
274/* ------------------------------------------ */
275
276/* VLSI_PIO_RINGBASE: Ring Pointer Base Address Register (u16, ro) */
277
278/* Contains [23:10] part of the ring base (bus-) address
279 * which must be 1k-alinged. [31:24] is taken from
280 * VLSI_PCI_MSTRPAGE above.
281 * The controller initiates non-burst PCI BM cycles to
282 * fetch and update the descriptors in the ring.
283 * Once fetched, the descriptor remains cached onchip
284 * until it gets closed and updated due to the ring
285 * processing state machine.
286 * The entire ring area is split in rx and tx areas with each
287 * area consisting of 64 descriptors of 8 bytes each.
288 * The rx(tx) ring is located at ringbase+0 (ringbase+64*8).
289 */
290
291#define BUS_TO_RINGBASE(p) (((p)>>10)&0x3fff)
292
293/* ------------------------------------------ */
294
295/* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */
296
297/* bit mask to indicate the ring size to be used for rx and tx.
298 * possible values encoded bits
299 * 4 0000
300 * 8 0001
301 * 16 0011
302 * 32 0111
303 * 64 1111
304 * located at [15:12] for tx and [11:8] for rx ([7:0] unused)
305 *
306 * note: probably a good idea to have IRCFG_MSTR cleared when writing
307 * this so the state machines are stopped and the RINGPTR is reset!
308 */
309
310#define SIZE_TO_BITS(num) ((((num)-1)>>2)&0x0f)
311#define TX_RX_TO_RINGSIZE(tx,rx) ((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8))
312#define RINGSIZE_TO_RXSIZE(rs) ((((rs)&0x0f00)>>6)+4)
313#define RINGSIZE_TO_TXSIZE(rs) ((((rs)&0xf000)>>10)+4)
314
315
316/* ------------------------------------------ */
317
318/* VLSI_PIO_PROMPT: Ring Prompting Register (u16, write-to-start) */
319
320/* writing any value kicks the ring processing state machines
321 * for both tx, rx rings as follows:
322 * - active rings (currently owning an active descriptor)
323 * ignore the prompt and continue
324 * - idle rings fetch the next descr from the ring and start
325 * their processing
326 */
327
328/* ------------------------------------------ */
329
330/* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */
331
332/* notes:
333 * - not more than one SIR/MIR/FIR bit must be set at any time
334 * - SIR, MIR, FIR and CRC16 select the configuration which will
335 * be applied on next 0->1 transition of IRENABLE_PHYANDCLOCK (see below).
336 * - besides allowing the PCI interface to execute busmaster cycles
337 * and therefore the ring SM to operate, the MSTR bit has side-effects:
338 * when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode
339 * (in contrast to busmaster access mode) gets enabled.
340 * - clearing ENRX or setting ENTX while data is received may stall the
341 * receive fifo until ENRX reenabled _and_ another packet arrives
342 * - SIRFILT means the chip performs the required unwrapping of hardware
343 * headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction.
344 * Only the resulting IrLAP payload is copied to the receive buffers -
345 * but with the 16bit FCS still encluded. Question remains, whether it
346 * was already checked or we should do it before passing the packet to IrLAP?
347 */
348
349enum vlsi_pio_ircfg {
350 IRCFG_LOOP = 0x4000, /* enable loopback test mode */
351 IRCFG_ENTX = 0x1000, /* transmit enable */
352 IRCFG_ENRX = 0x0800, /* receive enable */
353 IRCFG_MSTR = 0x0400, /* master enable */
354 IRCFG_RXANY = 0x0200, /* receive any packet */
355 IRCFG_CRC16 = 0x0080, /* 16bit (not 32bit) CRC select for MIR/FIR */
356 IRCFG_FIR = 0x0040, /* FIR 4PPM encoding mode enable */
357 IRCFG_MIR = 0x0020, /* MIR HDLC encoding mode enable */
358 IRCFG_SIR = 0x0010, /* SIR encoding mode enable */
359 IRCFG_SIRFILT = 0x0008, /* enable SIR decode filter (receiver unwrapping) */
360 IRCFG_SIRTEST = 0x0004, /* allow SIR decode filter when not in SIR mode */
361 IRCFG_TXPOL = 0x0002, /* invert tx polarity when set */
362 IRCFG_RXPOL = 0x0001 /* invert rx polarity when set */
363};
364
365/* ------------------------------------------ */
366
367/* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */
368
369/* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8]
370 * which is used for unwrapping received frames in SIR decode-filter mode
371 */
372
373/* ------------------------------------------ */
374
375/* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */
376
377/* notes:
378 * - IREN acts as gate for latching the configured IR mode information
379 * from IRCFG and IRPHYCTL when IREN=reset and applying them when
380 * IREN gets set afterwards.
381 * - ENTXST reflects IRCFG_ENTX
382 * - ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP)
383 */
384
385enum vlsi_pio_irenable {
386 IRENABLE_PHYANDCLOCK = 0x8000, /* enable IR phy and gate the mode config (rw) */
387 IRENABLE_CFGER = 0x4000, /* mode configuration error (ro) */
388 IRENABLE_FIR_ON = 0x2000, /* FIR on status (ro) */
389 IRENABLE_MIR_ON = 0x1000, /* MIR on status (ro) */
390 IRENABLE_SIR_ON = 0x0800, /* SIR on status (ro) */
391 IRENABLE_ENTXST = 0x0400, /* transmit enable status (ro) */
392 IRENABLE_ENRXST = 0x0200, /* Receive enable status (ro) */
393 IRENABLE_CRC16_ON = 0x0100 /* 16bit (not 32bit) CRC enabled status (ro) */
394};
395
396#define IRENABLE_MASK 0xff00 /* Read mask */
397
398/* ------------------------------------------ */
399
400/* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */
401
402/* read-back of the currently applied physical layer status.
403 * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_PHYANDCLOCK
404 * contents identical to VLSI_PIO_NPHYCTL (see below)
405 */
406
407/* ------------------------------------------ */
408
409/* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */
410
411/* latched during IRENABLE_PHYANDCLOCK=0 and applied at 0-1 transition
412 *
413 * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows:
414 *
415 * SIR-mode: BAUD = (115.2kHz / baudrate) - 1
416 * PLSWID = (pulsetime * freq / (BAUD+1)) - 1
417 * where pulsetime is the requested IrPHY pulse width
418 * and freq is 8(16)MHz for 40(48)MHz primary input clock
419 * PREAMB: don't care for SIR
420 *
421 * The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12
422 * fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz).
423 * IrPHY also allows shorter pulses down to the nominal pulse duration
424 * at 115.2kbaud (minus some tolerance) which is 1.41 usec.
425 * Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by two for 48MHz)
426 * we get the minimum acceptable PLSWID values according to the VLSI
427 * specification, which provides 1.5 usec pulse width for all speeds (except
428 * for 2.4kbaud getting 6usec). This is fine with IrPHY v1.3 specs and
429 * reduces the transceiver power which drains the battery. At 9.6kbaud for
430 * example this amounts to more than 90% battery power saving!
431 *
432 * MIR-mode: BAUD = 0
433 * PLSWID = 9(10) for 40(48) MHz input clock
434 * to get nominal MIR pulse width
435 * PREAMB = 1
436 *
437 * FIR-mode: BAUD = 0
438 * PLSWID: don't care
439 * PREAMB = 15
440 */
441
442#define PHYCTL_BAUD_SHIFT 10
443#define PHYCTL_BAUD_MASK 0xfc00
444#define PHYCTL_PLSWID_SHIFT 5
445#define PHYCTL_PLSWID_MASK 0x03e0
446#define PHYCTL_PREAMB_SHIFT 0
447#define PHYCTL_PREAMB_MASK 0x001f
448
449#define PHYCTL_TO_BAUD(bwp) (((bwp)&PHYCTL_BAUD_MASK)>>PHYCTL_BAUD_SHIFT)
450#define PHYCTL_TO_PLSWID(bwp) (((bwp)&PHYCTL_PLSWID_MASK)>>PHYCTL_PLSWID_SHIFT)
451#define PHYCTL_TO_PREAMB(bwp) (((bwp)&PHYCTL_PREAMB_MASK)>>PHYCTL_PREAMB_SHIFT)
452
453#define BWP_TO_PHYCTL(b,w,p) ((((b)<<PHYCTL_BAUD_SHIFT)&PHYCTL_BAUD_MASK) \
454 | (((w)<<PHYCTL_PLSWID_SHIFT)&PHYCTL_PLSWID_MASK) \
455 | (((p)<<PHYCTL_PREAMB_SHIFT)&PHYCTL_PREAMB_MASK))
456
457#define BAUD_BITS(br) ((115200/(br))-1)
458
459static inline unsigned
460calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect)
461{
462 unsigned tmp;
463
464 if (widthselect) /* nominal 3/16 puls width */
465 return (clockselect) ? 12 : 24;
466
467 tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1);
468
469 /* intermediate result of integer division needed here */
470
471 return (tmp>0) ? (tmp-1) : 0;
472}
473
474#define PHYCTL_SIR(br,ws,cs) BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0)
475#define PHYCTL_MIR(cs) BWP_TO_PHYCTL(0,((cs)?9:10),1)
476#define PHYCTL_FIR BWP_TO_PHYCTL(0,0,15)
477
478/* quite ugly, I know. But implementing these calculations here avoids
479 * having magic numbers in the code and allows some playing with pulsewidths
480 * without risk to violate the standards.
481 * FWIW, here is the table for reference:
482 *
483 * baudrate BAUD min-PLSWID nom-PLSWID PREAMB
484 * 2400 47 0(0) 12(24) 0
485 * 9600 11 0(0) 12(24) 0
486 * 19200 5 1(2) 12(24) 0
487 * 38400 2 3(6) 12(24) 0
488 * 57600 1 5(10) 12(24) 0
489 * 115200 0 11(22) 12(24) 0
490 * MIR 0 - 9(10) 1
491 * FIR 0 - 0 15
492 *
493 * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock
494 */
495
496/* ------------------------------------------ */
497
498
499/* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */
500
501/* maximum acceptable length for received packets */
502
503/* hw imposed limitation - register uses only [11:0] */
504#define MAX_PACKET_LENGTH 0x0fff
505
506/* IrLAP I-field (apparently not defined elsewhere) */
507#define IRDA_MTU 2048
508
509/* complete packet consists of A(1)+C(1)+I(<=IRDA_MTU) */
510#define IRLAP_SKB_ALLOCSIZE (1+1+IRDA_MTU)
511
512/* the buffers we use to exchange frames with the hardware need to be
513 * larger than IRLAP_SKB_ALLOCSIZE because we may have up to 4 bytes FCS
514 * appended and, in SIR mode, a lot of frame wrapping bytes. The worst
515 * case appears to be a SIR packet with I-size==IRDA_MTU and all bytes
516 * requiring to be escaped to provide transparency. Furthermore, the peer
517 * might ask for quite a number of additional XBOFs:
518 * up to 115+48 XBOFS 163
519 * regular BOF 1
520 * A-field 1
521 * C-field 1
522 * I-field, IRDA_MTU, all escaped 4096
523 * FCS (16 bit at SIR, escaped) 4
524 * EOF 1
525 * AFAICS nothing in IrLAP guarantees A/C field not to need escaping
526 * (f.e. 0xc0/0xc1 - i.e. BOF/EOF - are legal values there) so in the
527 * worst case we have 4269 bytes total frame size.
528 * However, the VLSI uses 12 bits only for all buffer length values,
529 * which limits the maximum useable buffer size <= 4095.
530 * Note this is not a limitation in the receive case because we use
531 * the SIR filtering mode where the hw unwraps the frame and only the
532 * bare packet+fcs is stored into the buffer - in contrast to the SIR
533 * tx case where we have to pass frame-wrapped packets to the hw.
534 * If this would ever become an issue in real life, the only workaround
535 * I see would be using the legacy UART emulation in SIR mode.
536 */
537
538#define XFER_BUF_SIZE MAX_PACKET_LENGTH
539
540/* ------------------------------------------ */
541
542/* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */
543
544/* receive packet counter gets incremented on every non-filtered
545 * byte which was put in the receive fifo and reset for each
546 * new packet. Used to decide whether we are just in the middle
547 * of receiving
548 */
549
550/* better apply the [11:0] mask when reading, as some docs say the
551 * reserved [15:12] would return 1 when reading - which is wrong AFAICS
552 */
553#define RCVBCNT_MASK 0x0fff
554
555/******************************************************************/
556
557/* descriptors for rx/tx ring
558 *
559 * accessed by hardware - don't change!
560 *
561 * the descriptor is owned by hardware, when the ACTIVE status bit
562 * is set and nothing (besides reading status to test the bit)
563 * shall be done. The bit gets cleared by hw, when the descriptor
564 * gets closed. Premature reaping of descriptors owned be the chip
565 * can be achieved by disabling IRCFG_MSTR
566 *
567 * Attention: Writing addr overwrites status!
568 *
569 * ### FIXME: depends on endianess (but there ain't no non-i586 ob800 ;-)
570 */
571
572struct ring_descr_hw {
573 volatile u16 rd_count; /* tx/rx count [11:0] */
574 u16 reserved;
575 union {
576 u32 addr; /* [23:0] of the buffer's busaddress */
577 struct {
578 u8 addr_res[3];
579 volatile u8 status; /* descriptor status */
Jan Blunck6a878182006-01-08 01:05:07 -0800580 } __attribute__((packed)) rd_s;
581 } __attribute((packed)) rd_u;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582} __attribute__ ((packed));
583
584#define rd_addr rd_u.addr
585#define rd_status rd_u.rd_s.status
586
587/* ring descriptor status bits */
588
589#define RD_ACTIVE 0x80 /* descriptor owned by hw (both TX,RX) */
590
591/* TX ring descriptor status */
592
593#define RD_TX_DISCRC 0x40 /* do not send CRC (for SIR) */
594#define RD_TX_BADCRC 0x20 /* force a bad CRC */
595#define RD_TX_PULSE 0x10 /* send indication pulse after this frame (MIR/FIR) */
596#define RD_TX_FRCEUND 0x08 /* force underrun */
597#define RD_TX_CLRENTX 0x04 /* clear ENTX after this frame */
598#define RD_TX_UNDRN 0x01 /* TX fifo underrun (probably PCI problem) */
599
600/* RX ring descriptor status */
601
602#define RD_RX_PHYERR 0x40 /* physical encoding error */
603#define RD_RX_CRCERR 0x20 /* CRC error (MIR/FIR) */
604#define RD_RX_LENGTH 0x10 /* frame exceeds buffer length */
605#define RD_RX_OVER 0x08 /* RX fifo overrun (probably PCI problem) */
606#define RD_RX_SIRBAD 0x04 /* EOF missing: BOF follows BOF (SIR, filtered) */
607
608#define RD_RX_ERROR 0x7c /* any error in received frame */
609
610/* the memory required to hold the 2 descriptor rings */
611#define HW_RING_AREA_SIZE (2 * MAX_RING_DESCR * sizeof(struct ring_descr_hw))
612
613/******************************************************************/
614
615/* sw-ring descriptors consists of a bus-mapped transfer buffer with
616 * associated skb and a pointer to the hw entry descriptor
617 */
618
619struct ring_descr {
620 struct ring_descr_hw *hw;
621 struct sk_buff *skb;
622 void *buf;
623};
624
625/* wrappers for operations on hw-exposed ring descriptors
626 * access to the hw-part of the descriptors must use these.
627 */
628
629static inline int rd_is_active(struct ring_descr *rd)
630{
631 return ((rd->hw->rd_status & RD_ACTIVE) != 0);
632}
633
634static inline void rd_activate(struct ring_descr *rd)
635{
636 rd->hw->rd_status |= RD_ACTIVE;
637}
638
639static inline void rd_set_status(struct ring_descr *rd, u8 s)
640{
641 rd->hw->rd_status = s; /* may pass ownership to the hardware */
642}
643
644static inline void rd_set_addr_status(struct ring_descr *rd, dma_addr_t a, u8 s)
645{
646 /* order is important for two reasons:
647 * - overlayed: writing addr overwrites status
648 * - we want to write status last so we have valid address in
649 * case status has RD_ACTIVE set
650 */
651
652 if ((a & ~DMA_MASK_MSTRPAGE)>>24 != MSTRPAGE_VALUE) {
653 IRDA_ERROR("%s: pci busaddr inconsistency!\n", __FUNCTION__);
654 dump_stack();
655 return;
656 }
657
658 a &= DMA_MASK_MSTRPAGE; /* clear highbyte to make sure we won't write
659 * to status - just in case MSTRPAGE_VALUE!=0
660 */
661 rd->hw->rd_addr = cpu_to_le32(a);
662 wmb();
663 rd_set_status(rd, s); /* may pass ownership to the hardware */
664}
665
666static inline void rd_set_count(struct ring_descr *rd, u16 c)
667{
668 rd->hw->rd_count = cpu_to_le16(c);
669}
670
671static inline u8 rd_get_status(struct ring_descr *rd)
672{
673 return rd->hw->rd_status;
674}
675
676static inline dma_addr_t rd_get_addr(struct ring_descr *rd)
677{
678 dma_addr_t a;
679
680 a = le32_to_cpu(rd->hw->rd_addr);
681 return (a & DMA_MASK_MSTRPAGE) | (MSTRPAGE_VALUE << 24);
682}
683
684static inline u16 rd_get_count(struct ring_descr *rd)
685{
686 return le16_to_cpu(rd->hw->rd_count);
687}
688
689/******************************************************************/
690
691/* sw descriptor rings for rx, tx:
692 *
693 * operations follow producer-consumer paradigm, with the hw
694 * in the middle doing the processing.
695 * ring size must be power of two.
696 *
697 * producer advances r->tail after inserting for processing
698 * consumer advances r->head after removing processed rd
699 * ring is empty if head==tail / full if (tail+1)==head
700 */
701
702struct vlsi_ring {
703 struct pci_dev *pdev;
704 int dir;
705 unsigned len;
706 unsigned size;
707 unsigned mask;
708 atomic_t head, tail;
709 struct ring_descr *rd;
710};
711
712/* ring processing helpers */
713
714static inline struct ring_descr *ring_last(struct vlsi_ring *r)
715{
716 int t;
717
718 t = atomic_read(&r->tail) & r->mask;
719 return (((t+1) & r->mask) == (atomic_read(&r->head) & r->mask)) ? NULL : &r->rd[t];
720}
721
722static inline struct ring_descr *ring_put(struct vlsi_ring *r)
723{
724 atomic_inc(&r->tail);
725 return ring_last(r);
726}
727
728static inline struct ring_descr *ring_first(struct vlsi_ring *r)
729{
730 int h;
731
732 h = atomic_read(&r->head) & r->mask;
733 return (h == (atomic_read(&r->tail) & r->mask)) ? NULL : &r->rd[h];
734}
735
736static inline struct ring_descr *ring_get(struct vlsi_ring *r)
737{
738 atomic_inc(&r->head);
739 return ring_first(r);
740}
741
742/******************************************************************/
743
744/* our private compound VLSI-PCI-IRDA device information */
745
746typedef struct vlsi_irda_dev {
747 struct pci_dev *pdev;
748 struct net_device_stats stats;
749
750 struct irlap_cb *irlap;
751
752 struct qos_info qos;
753
754 unsigned mode;
755 int baud, new_baud;
756
757 dma_addr_t busaddr;
758 void *virtaddr;
759 struct vlsi_ring *tx_ring, *rx_ring;
760
761 struct timeval last_rx;
762
763 spinlock_t lock;
764 struct semaphore sem;
765
766 u8 resume_ok;
767 struct proc_dir_entry *proc_entry;
768
769} vlsi_irda_dev_t;
770
771/********************************************************/
772
773/* the remapped error flags we use for returning from frame
774 * post-processing in vlsi_process_tx/rx() after it was completed
775 * by the hardware. These functions either return the >=0 number
776 * of transfered bytes in case of success or the negative (-)
777 * of the or'ed error flags.
778 */
779
780#define VLSI_TX_DROP 0x0001
781#define VLSI_TX_FIFO 0x0002
782
783#define VLSI_RX_DROP 0x0100
784#define VLSI_RX_OVER 0x0200
785#define VLSI_RX_LENGTH 0x0400
786#define VLSI_RX_FRAME 0x0800
787#define VLSI_RX_CRC 0x1000
788
789/********************************************************/
790
791#endif /* IRDA_VLSI_FIR_H */
792