Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/irq.c |
| 3 | * |
| 4 | * Generic IRQ handling, GPIO IRQ demultiplexing, etc. |
| 5 | * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd. |
| 6 | * |
| 7 | * Author: Bin Yang <bin.yang@marvell.com> |
| 8 | * Haojian Zhuang <haojian.zhuang@gmail.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/irq.h> |
| 18 | #include <linux/irqdomain.h> |
| 19 | #include <linux/io.h> |
| 20 | #include <linux/ioport.h> |
| 21 | #include <linux/of_address.h> |
| 22 | #include <linux/of_irq.h> |
| 23 | |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 24 | #include <asm/exception.h> |
| 25 | #include <asm/mach/irq.h> |
| 26 | |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 27 | #include <mach/irqs.h> |
| 28 | |
Chao Xie | 87046f4 | 2012-05-07 11:22:23 +0800 | [diff] [blame] | 29 | #ifdef CONFIG_CPU_MMP2 |
| 30 | #include <mach/pm-mmp2.h> |
| 31 | #endif |
Chao Xie | 902ca22 | 2012-05-07 11:24:01 +0800 | [diff] [blame] | 32 | #ifdef CONFIG_CPU_PXA910 |
| 33 | #include <mach/pm-pxa910.h> |
| 34 | #endif |
Chao Xie | 87046f4 | 2012-05-07 11:22:23 +0800 | [diff] [blame] | 35 | |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 36 | #include "irqchip.h" |
| 37 | |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 38 | #define MAX_ICU_NR 16 |
| 39 | |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 40 | #define PJ1_INT_SEL 0x10c |
| 41 | #define PJ4_INT_SEL 0x104 |
| 42 | |
| 43 | /* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */ |
| 44 | #define SEL_INT_PENDING (1 << 6) |
| 45 | #define SEL_INT_NUM_MASK 0x3f |
| 46 | |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 47 | struct icu_chip_data { |
| 48 | int nr_irqs; |
| 49 | unsigned int virq_base; |
| 50 | unsigned int cascade_irq; |
| 51 | void __iomem *reg_status; |
| 52 | void __iomem *reg_mask; |
| 53 | unsigned int conf_enable; |
| 54 | unsigned int conf_disable; |
| 55 | unsigned int conf_mask; |
| 56 | unsigned int clr_mfp_irq_base; |
| 57 | unsigned int clr_mfp_hwirq; |
| 58 | struct irq_domain *domain; |
| 59 | }; |
| 60 | |
| 61 | struct mmp_intc_conf { |
| 62 | unsigned int conf_enable; |
| 63 | unsigned int conf_disable; |
| 64 | unsigned int conf_mask; |
| 65 | }; |
| 66 | |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 67 | static void __iomem *mmp_icu_base; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 68 | static struct icu_chip_data icu_data[MAX_ICU_NR]; |
| 69 | static int max_icu_nr; |
| 70 | |
| 71 | extern void mmp2_clear_pmic_int(void); |
| 72 | |
| 73 | static void icu_mask_ack_irq(struct irq_data *d) |
| 74 | { |
| 75 | struct irq_domain *domain = d->domain; |
| 76 | struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; |
| 77 | int hwirq; |
| 78 | u32 r; |
| 79 | |
| 80 | hwirq = d->irq - data->virq_base; |
| 81 | if (data == &icu_data[0]) { |
| 82 | r = readl_relaxed(mmp_icu_base + (hwirq << 2)); |
| 83 | r &= ~data->conf_mask; |
| 84 | r |= data->conf_disable; |
| 85 | writel_relaxed(r, mmp_icu_base + (hwirq << 2)); |
| 86 | } else { |
| 87 | #ifdef CONFIG_CPU_MMP2 |
| 88 | if ((data->virq_base == data->clr_mfp_irq_base) |
| 89 | && (hwirq == data->clr_mfp_hwirq)) |
| 90 | mmp2_clear_pmic_int(); |
| 91 | #endif |
| 92 | r = readl_relaxed(data->reg_mask) | (1 << hwirq); |
| 93 | writel_relaxed(r, data->reg_mask); |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | static void icu_mask_irq(struct irq_data *d) |
| 98 | { |
| 99 | struct irq_domain *domain = d->domain; |
| 100 | struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; |
| 101 | int hwirq; |
| 102 | u32 r; |
| 103 | |
| 104 | hwirq = d->irq - data->virq_base; |
| 105 | if (data == &icu_data[0]) { |
| 106 | r = readl_relaxed(mmp_icu_base + (hwirq << 2)); |
| 107 | r &= ~data->conf_mask; |
| 108 | r |= data->conf_disable; |
| 109 | writel_relaxed(r, mmp_icu_base + (hwirq << 2)); |
| 110 | } else { |
| 111 | r = readl_relaxed(data->reg_mask) | (1 << hwirq); |
| 112 | writel_relaxed(r, data->reg_mask); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | static void icu_unmask_irq(struct irq_data *d) |
| 117 | { |
| 118 | struct irq_domain *domain = d->domain; |
| 119 | struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; |
| 120 | int hwirq; |
| 121 | u32 r; |
| 122 | |
| 123 | hwirq = d->irq - data->virq_base; |
| 124 | if (data == &icu_data[0]) { |
| 125 | r = readl_relaxed(mmp_icu_base + (hwirq << 2)); |
| 126 | r &= ~data->conf_mask; |
| 127 | r |= data->conf_enable; |
| 128 | writel_relaxed(r, mmp_icu_base + (hwirq << 2)); |
| 129 | } else { |
| 130 | r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); |
| 131 | writel_relaxed(r, data->reg_mask); |
| 132 | } |
| 133 | } |
| 134 | |
| 135 | static struct irq_chip icu_irq_chip = { |
| 136 | .name = "icu_irq", |
| 137 | .irq_mask = icu_mask_irq, |
| 138 | .irq_mask_ack = icu_mask_ack_irq, |
| 139 | .irq_unmask = icu_unmask_irq, |
| 140 | }; |
| 141 | |
| 142 | static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc) |
| 143 | { |
| 144 | struct irq_domain *domain; |
| 145 | struct icu_chip_data *data; |
| 146 | int i; |
| 147 | unsigned long mask, status, n; |
| 148 | |
| 149 | for (i = 1; i < max_icu_nr; i++) { |
| 150 | if (irq == icu_data[i].cascade_irq) { |
| 151 | domain = icu_data[i].domain; |
| 152 | data = (struct icu_chip_data *)domain->host_data; |
| 153 | break; |
| 154 | } |
| 155 | } |
| 156 | if (i >= max_icu_nr) { |
| 157 | pr_err("Spurious irq %d in MMP INTC\n", irq); |
| 158 | return; |
| 159 | } |
| 160 | |
| 161 | mask = readl_relaxed(data->reg_mask); |
| 162 | while (1) { |
| 163 | status = readl_relaxed(data->reg_status) & ~mask; |
| 164 | if (status == 0) |
| 165 | break; |
Wei Yongjun | 93d429a | 2012-09-14 10:30:59 +0800 | [diff] [blame] | 166 | for_each_set_bit(n, &status, BITS_PER_LONG) { |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 167 | generic_handle_irq(icu_data[i].virq_base + n); |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 168 | } |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 173 | irq_hw_number_t hw) |
| 174 | { |
| 175 | irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); |
| 176 | set_irq_flags(irq, IRQF_VALID); |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node, |
| 181 | const u32 *intspec, unsigned int intsize, |
| 182 | unsigned long *out_hwirq, |
| 183 | unsigned int *out_type) |
| 184 | { |
| 185 | *out_hwirq = intspec[0]; |
| 186 | return 0; |
| 187 | } |
| 188 | |
| 189 | const struct irq_domain_ops mmp_irq_domain_ops = { |
| 190 | .map = mmp_irq_domain_map, |
| 191 | .xlate = mmp_irq_domain_xlate, |
| 192 | }; |
| 193 | |
| 194 | static struct mmp_intc_conf mmp_conf = { |
| 195 | .conf_enable = 0x51, |
| 196 | .conf_disable = 0x0, |
| 197 | .conf_mask = 0x7f, |
| 198 | }; |
| 199 | |
| 200 | static struct mmp_intc_conf mmp2_conf = { |
| 201 | .conf_enable = 0x20, |
| 202 | .conf_disable = 0x0, |
| 203 | .conf_mask = 0x7f, |
| 204 | }; |
| 205 | |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 206 | static asmlinkage void __exception_irq_entry |
| 207 | mmp_handle_irq(struct pt_regs *regs) |
| 208 | { |
| 209 | int irq, hwirq; |
| 210 | |
| 211 | hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); |
| 212 | if (!(hwirq & SEL_INT_PENDING)) |
| 213 | return; |
| 214 | hwirq &= SEL_INT_NUM_MASK; |
| 215 | irq = irq_find_mapping(icu_data[0].domain, hwirq); |
| 216 | handle_IRQ(irq, regs); |
| 217 | } |
| 218 | |
| 219 | static asmlinkage void __exception_irq_entry |
| 220 | mmp2_handle_irq(struct pt_regs *regs) |
| 221 | { |
| 222 | int irq, hwirq; |
| 223 | |
| 224 | hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL); |
| 225 | if (!(hwirq & SEL_INT_PENDING)) |
| 226 | return; |
| 227 | hwirq &= SEL_INT_NUM_MASK; |
| 228 | irq = irq_find_mapping(icu_data[0].domain, hwirq); |
| 229 | handle_IRQ(irq, regs); |
| 230 | } |
| 231 | |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 232 | /* MMP (ARMv5) */ |
| 233 | void __init icu_init_irq(void) |
| 234 | { |
| 235 | int irq; |
| 236 | |
| 237 | max_icu_nr = 1; |
| 238 | mmp_icu_base = ioremap(0xd4282000, 0x1000); |
| 239 | icu_data[0].conf_enable = mmp_conf.conf_enable; |
| 240 | icu_data[0].conf_disable = mmp_conf.conf_disable; |
| 241 | icu_data[0].conf_mask = mmp_conf.conf_mask; |
| 242 | icu_data[0].nr_irqs = 64; |
| 243 | icu_data[0].virq_base = 0; |
| 244 | icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, |
| 245 | &irq_domain_simple_ops, |
| 246 | &icu_data[0]); |
| 247 | for (irq = 0; irq < 64; irq++) { |
| 248 | icu_mask_irq(irq_get_irq_data(irq)); |
| 249 | irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); |
| 250 | set_irq_flags(irq, IRQF_VALID); |
| 251 | } |
| 252 | irq_set_default_host(icu_data[0].domain); |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 253 | set_handle_irq(mmp_handle_irq); |
Chao Xie | 902ca22 | 2012-05-07 11:24:01 +0800 | [diff] [blame] | 254 | #ifdef CONFIG_CPU_PXA910 |
| 255 | icu_irq_chip.irq_set_wake = pxa910_set_wake; |
| 256 | #endif |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | /* MMP2 (ARMv7) */ |
| 260 | void __init mmp2_init_icu(void) |
| 261 | { |
| 262 | int irq; |
| 263 | |
| 264 | max_icu_nr = 8; |
| 265 | mmp_icu_base = ioremap(0xd4282000, 0x1000); |
| 266 | icu_data[0].conf_enable = mmp2_conf.conf_enable; |
| 267 | icu_data[0].conf_disable = mmp2_conf.conf_disable; |
| 268 | icu_data[0].conf_mask = mmp2_conf.conf_mask; |
| 269 | icu_data[0].nr_irqs = 64; |
| 270 | icu_data[0].virq_base = 0; |
| 271 | icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, |
| 272 | &irq_domain_simple_ops, |
| 273 | &icu_data[0]); |
| 274 | icu_data[1].reg_status = mmp_icu_base + 0x150; |
| 275 | icu_data[1].reg_mask = mmp_icu_base + 0x168; |
| 276 | icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; |
| 277 | icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; |
| 278 | icu_data[1].nr_irqs = 2; |
Haojian Zhuang | 10bd21c | 2012-06-05 17:42:23 +0800 | [diff] [blame] | 279 | icu_data[1].cascade_irq = 4; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 280 | icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; |
| 281 | icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, |
| 282 | icu_data[1].virq_base, 0, |
| 283 | &irq_domain_simple_ops, |
| 284 | &icu_data[1]); |
| 285 | icu_data[2].reg_status = mmp_icu_base + 0x154; |
| 286 | icu_data[2].reg_mask = mmp_icu_base + 0x16c; |
| 287 | icu_data[2].nr_irqs = 2; |
Haojian Zhuang | 10bd21c | 2012-06-05 17:42:23 +0800 | [diff] [blame] | 288 | icu_data[2].cascade_irq = 5; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 289 | icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; |
| 290 | icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, |
| 291 | icu_data[2].virq_base, 0, |
| 292 | &irq_domain_simple_ops, |
| 293 | &icu_data[2]); |
| 294 | icu_data[3].reg_status = mmp_icu_base + 0x180; |
| 295 | icu_data[3].reg_mask = mmp_icu_base + 0x17c; |
| 296 | icu_data[3].nr_irqs = 3; |
Haojian Zhuang | 10bd21c | 2012-06-05 17:42:23 +0800 | [diff] [blame] | 297 | icu_data[3].cascade_irq = 9; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 298 | icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; |
| 299 | icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, |
| 300 | icu_data[3].virq_base, 0, |
| 301 | &irq_domain_simple_ops, |
| 302 | &icu_data[3]); |
| 303 | icu_data[4].reg_status = mmp_icu_base + 0x158; |
| 304 | icu_data[4].reg_mask = mmp_icu_base + 0x170; |
| 305 | icu_data[4].nr_irqs = 5; |
Haojian Zhuang | 10bd21c | 2012-06-05 17:42:23 +0800 | [diff] [blame] | 306 | icu_data[4].cascade_irq = 17; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 307 | icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; |
| 308 | icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, |
| 309 | icu_data[4].virq_base, 0, |
| 310 | &irq_domain_simple_ops, |
| 311 | &icu_data[4]); |
| 312 | icu_data[5].reg_status = mmp_icu_base + 0x15c; |
| 313 | icu_data[5].reg_mask = mmp_icu_base + 0x174; |
| 314 | icu_data[5].nr_irqs = 15; |
Haojian Zhuang | 10bd21c | 2012-06-05 17:42:23 +0800 | [diff] [blame] | 315 | icu_data[5].cascade_irq = 35; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 316 | icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; |
| 317 | icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, |
| 318 | icu_data[5].virq_base, 0, |
| 319 | &irq_domain_simple_ops, |
| 320 | &icu_data[5]); |
| 321 | icu_data[6].reg_status = mmp_icu_base + 0x160; |
| 322 | icu_data[6].reg_mask = mmp_icu_base + 0x178; |
| 323 | icu_data[6].nr_irqs = 2; |
Haojian Zhuang | 10bd21c | 2012-06-05 17:42:23 +0800 | [diff] [blame] | 324 | icu_data[6].cascade_irq = 51; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 325 | icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; |
| 326 | icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, |
| 327 | icu_data[6].virq_base, 0, |
| 328 | &irq_domain_simple_ops, |
| 329 | &icu_data[6]); |
| 330 | icu_data[7].reg_status = mmp_icu_base + 0x188; |
| 331 | icu_data[7].reg_mask = mmp_icu_base + 0x184; |
| 332 | icu_data[7].nr_irqs = 2; |
Haojian Zhuang | 10bd21c | 2012-06-05 17:42:23 +0800 | [diff] [blame] | 333 | icu_data[7].cascade_irq = 55; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 334 | icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; |
| 335 | icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, |
| 336 | icu_data[7].virq_base, 0, |
| 337 | &irq_domain_simple_ops, |
| 338 | &icu_data[7]); |
| 339 | for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) { |
| 340 | icu_mask_irq(irq_get_irq_data(irq)); |
| 341 | switch (irq) { |
| 342 | case IRQ_MMP2_PMIC_MUX: |
| 343 | case IRQ_MMP2_RTC_MUX: |
| 344 | case IRQ_MMP2_KEYPAD_MUX: |
| 345 | case IRQ_MMP2_TWSI_MUX: |
| 346 | case IRQ_MMP2_MISC_MUX: |
| 347 | case IRQ_MMP2_MIPI_HSI1_MUX: |
| 348 | case IRQ_MMP2_MIPI_HSI0_MUX: |
| 349 | irq_set_chip(irq, &icu_irq_chip); |
| 350 | irq_set_chained_handler(irq, icu_mux_irq_demux); |
| 351 | break; |
| 352 | default: |
| 353 | irq_set_chip_and_handler(irq, &icu_irq_chip, |
| 354 | handle_level_irq); |
| 355 | break; |
| 356 | } |
| 357 | set_irq_flags(irq, IRQF_VALID); |
| 358 | } |
| 359 | irq_set_default_host(icu_data[0].domain); |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 360 | set_handle_irq(mmp2_handle_irq); |
Chao Xie | 87046f4 | 2012-05-07 11:22:23 +0800 | [diff] [blame] | 361 | #ifdef CONFIG_CPU_MMP2 |
| 362 | icu_irq_chip.irq_set_wake = mmp2_set_wake; |
| 363 | #endif |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 364 | } |
| 365 | |
| 366 | #ifdef CONFIG_OF |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 367 | static int __init mmp_init_bases(struct device_node *node) |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 368 | { |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 369 | int ret, nr_irqs, irq, i = 0; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 370 | |
| 371 | ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); |
| 372 | if (ret) { |
| 373 | pr_err("Not found mrvl,intc-nr-irqs property\n"); |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 374 | return ret; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | mmp_icu_base = of_iomap(node, 0); |
| 378 | if (!mmp_icu_base) { |
| 379 | pr_err("Failed to get interrupt controller register\n"); |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 380 | return -ENOMEM; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 381 | } |
| 382 | |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 383 | icu_data[0].virq_base = 0; |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 384 | icu_data[0].domain = irq_domain_add_linear(node, nr_irqs, |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 385 | &mmp_irq_domain_ops, |
| 386 | &icu_data[0]); |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 387 | for (irq = 0; irq < nr_irqs; irq++) { |
| 388 | ret = irq_create_mapping(icu_data[0].domain, irq); |
| 389 | if (!ret) { |
| 390 | pr_err("Failed to mapping hwirq\n"); |
| 391 | goto err; |
| 392 | } |
| 393 | if (!irq) |
| 394 | icu_data[0].virq_base = ret; |
| 395 | } |
| 396 | icu_data[0].nr_irqs = nr_irqs; |
| 397 | return 0; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 398 | err: |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 399 | if (icu_data[0].virq_base) { |
| 400 | for (i = 0; i < irq; i++) |
| 401 | irq_dispose_mapping(icu_data[0].virq_base + i); |
| 402 | } |
| 403 | irq_domain_remove(icu_data[0].domain); |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 404 | iounmap(mmp_icu_base); |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 405 | return -EINVAL; |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 406 | } |
Haojian Zhuang | 0f37456 | 2013-04-21 16:53:02 +0800 | [diff] [blame^] | 407 | |
| 408 | static int __init mmp_of_init(struct device_node *node, |
| 409 | struct device_node *parent) |
| 410 | { |
| 411 | int ret; |
| 412 | |
| 413 | ret = mmp_init_bases(node); |
| 414 | if (ret < 0) |
| 415 | return ret; |
| 416 | |
| 417 | icu_data[0].conf_enable = mmp_conf.conf_enable; |
| 418 | icu_data[0].conf_disable = mmp_conf.conf_disable; |
| 419 | icu_data[0].conf_mask = mmp_conf.conf_mask; |
| 420 | irq_set_default_host(icu_data[0].domain); |
| 421 | set_handle_irq(mmp_handle_irq); |
| 422 | max_icu_nr = 1; |
| 423 | return 0; |
| 424 | } |
| 425 | IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init); |
| 426 | |
| 427 | static int __init mmp2_of_init(struct device_node *node, |
| 428 | struct device_node *parent) |
| 429 | { |
| 430 | int ret; |
| 431 | |
| 432 | ret = mmp_init_bases(node); |
| 433 | if (ret < 0) |
| 434 | return ret; |
| 435 | |
| 436 | icu_data[0].conf_enable = mmp2_conf.conf_enable; |
| 437 | icu_data[0].conf_disable = mmp2_conf.conf_disable; |
| 438 | icu_data[0].conf_mask = mmp2_conf.conf_mask; |
| 439 | irq_set_default_host(icu_data[0].domain); |
| 440 | set_handle_irq(mmp2_handle_irq); |
| 441 | max_icu_nr = 1; |
| 442 | return 0; |
| 443 | } |
| 444 | IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init); |
| 445 | |
| 446 | static int __init mmp2_mux_of_init(struct device_node *node, |
| 447 | struct device_node *parent) |
| 448 | { |
| 449 | struct resource res; |
| 450 | int i, ret, irq, j = 0; |
| 451 | u32 nr_irqs, mfp_irq; |
| 452 | |
| 453 | if (!parent) |
| 454 | return -ENODEV; |
| 455 | |
| 456 | i = max_icu_nr; |
| 457 | ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", |
| 458 | &nr_irqs); |
| 459 | if (ret) { |
| 460 | pr_err("Not found mrvl,intc-nr-irqs property\n"); |
| 461 | return -EINVAL; |
| 462 | } |
| 463 | ret = of_address_to_resource(node, 0, &res); |
| 464 | if (ret < 0) { |
| 465 | pr_err("Not found reg property\n"); |
| 466 | return -EINVAL; |
| 467 | } |
| 468 | icu_data[i].reg_status = mmp_icu_base + res.start; |
| 469 | ret = of_address_to_resource(node, 1, &res); |
| 470 | if (ret < 0) { |
| 471 | pr_err("Not found reg property\n"); |
| 472 | return -EINVAL; |
| 473 | } |
| 474 | icu_data[i].reg_mask = mmp_icu_base + res.start; |
| 475 | icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0); |
| 476 | if (!icu_data[i].cascade_irq) |
| 477 | return -EINVAL; |
| 478 | |
| 479 | icu_data[i].virq_base = 0; |
| 480 | icu_data[i].domain = irq_domain_add_linear(node, nr_irqs, |
| 481 | &mmp_irq_domain_ops, |
| 482 | &icu_data[i]); |
| 483 | for (irq = 0; irq < nr_irqs; irq++) { |
| 484 | ret = irq_create_mapping(icu_data[i].domain, irq); |
| 485 | if (!ret) { |
| 486 | pr_err("Failed to mapping hwirq\n"); |
| 487 | goto err; |
| 488 | } |
| 489 | if (!irq) |
| 490 | icu_data[i].virq_base = ret; |
| 491 | } |
| 492 | icu_data[i].nr_irqs = nr_irqs; |
| 493 | if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", |
| 494 | &mfp_irq)) { |
| 495 | icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base; |
| 496 | icu_data[i].clr_mfp_hwirq = mfp_irq; |
| 497 | } |
| 498 | irq_set_chained_handler(icu_data[i].cascade_irq, |
| 499 | icu_mux_irq_demux); |
| 500 | max_icu_nr++; |
| 501 | return 0; |
| 502 | err: |
| 503 | if (icu_data[i].virq_base) { |
| 504 | for (j = 0; j < irq; j++) |
| 505 | irq_dispose_mapping(icu_data[i].virq_base + j); |
| 506 | } |
| 507 | irq_domain_remove(icu_data[i].domain); |
| 508 | return -EINVAL; |
| 509 | } |
| 510 | IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init); |
Haojian Zhuang | c24b311 | 2012-04-12 19:02:02 +0800 | [diff] [blame] | 511 | #endif |