blob: 66414cc8e6e38650da20a9447eaa34fd09b28b21 [file] [log] [blame]
Tony Lindgren92105bb2005-09-07 17:20:26 +01001/*
2 * linux/arch/arm/plat-omap/sram.S
3 *
4 * Functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/config.h>
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <asm/arch/io.h>
Russell King0a5709b2005-11-16 14:51:20 +000015#include <asm/hardware.h>
Tony Lindgren92105bb2005-09-07 17:20:26 +010016
17 .text
18
19/*
20 * Reprograms ULPD and CKCTL.
21 */
22ENTRY(sram_reprogram_clock)
23 stmfd sp!, {r0 - r12, lr} @ save registers on stack
24
25 mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #IO_ADDRESS(DPLL_CTL) & 0x0000ff00
28
29 mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
30 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
32
33 tst r0, #1 << 4 @ want lock mode?
34 beq newck @ nope
35 bic r0, r0, #1 << 4 @ else clear lock bit
36 strh r0, [r2] @ set dpll into bypass mode
37 orr r0, r0, #1 << 4 @ set lock bit again
38
39newck:
40 strh r1, [r3] @ write new ckctl value
41 strh r0, [r2] @ write new dpll value
42
43 mov r4, #0x0700 @ let the clocks settle
44 orr r4, r4, #0x00ff
45delay: sub r4, r4, #1
46 cmp r4, #0
47 bne delay
48
49lock: ldrh r4, [r2], #0 @ read back dpll value
50 tst r0, #1 << 4 @ want lock mode?
51 beq out @ nope
52 tst r4, #1 << 0 @ dpll rate locked?
53 beq lock @ try again
54
55out:
56 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
57ENTRY(sram_reprogram_clock_sz)
58 .word . - sram_reprogram_clock