Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Imagination Technologies |
| 3 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/io.h> |
| 12 | #include <linux/sched.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/smp.h> |
| 15 | #include <linux/types.h> |
| 16 | |
| 17 | #include <asm/cacheflush.h> |
| 18 | #include <asm/gic.h> |
| 19 | #include <asm/mips-cm.h> |
| 20 | #include <asm/mips-cpc.h> |
| 21 | #include <asm/mips_mt.h> |
| 22 | #include <asm/mipsregs.h> |
| 23 | #include <asm/smp-cps.h> |
| 24 | #include <asm/time.h> |
| 25 | #include <asm/uasm.h> |
| 26 | |
| 27 | static DECLARE_BITMAP(core_power, NR_CPUS); |
| 28 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 29 | struct core_boot_config *mips_cps_core_bootcfg; |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 30 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 31 | static unsigned core_vpe_count(unsigned core) |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 32 | { |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 33 | unsigned cfg; |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 34 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 35 | if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt) |
| 36 | return 1; |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 37 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 38 | write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); |
| 39 | cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK; |
| 40 | return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 41 | } |
| 42 | |
| 43 | static void __init cps_smp_setup(void) |
| 44 | { |
| 45 | unsigned int ncores, nvpes, core_vpes; |
| 46 | int c, v; |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 47 | |
| 48 | /* Detect & record VPE topology */ |
| 49 | ncores = mips_cm_numcores(); |
| 50 | pr_info("VPE topology "); |
| 51 | for (c = nvpes = 0; c < ncores; c++) { |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 52 | core_vpes = core_vpe_count(c); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 53 | pr_cont("%c%u", c ? ',' : '{', core_vpes); |
| 54 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 55 | /* Use the number of VPEs in core 0 for smp_num_siblings */ |
| 56 | if (!c) |
| 57 | smp_num_siblings = core_vpes; |
| 58 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 59 | for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { |
| 60 | cpu_data[nvpes + v].core = c; |
| 61 | #ifdef CONFIG_MIPS_MT_SMP |
| 62 | cpu_data[nvpes + v].vpe_id = v; |
| 63 | #endif |
| 64 | } |
| 65 | |
| 66 | nvpes += core_vpes; |
| 67 | } |
| 68 | pr_cont("} total %u\n", nvpes); |
| 69 | |
| 70 | /* Indicate present CPUs (CPU being synonymous with VPE) */ |
| 71 | for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { |
| 72 | set_cpu_possible(v, true); |
| 73 | set_cpu_present(v, true); |
| 74 | __cpu_number_map[v] = v; |
| 75 | __cpu_logical_map[v] = v; |
| 76 | } |
| 77 | |
| 78 | /* Core 0 is powered up (we're running on it) */ |
| 79 | bitmap_set(core_power, 0, 1); |
| 80 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 81 | /* Initialise core 0 */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 82 | mips_cps_core_init(); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 83 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 84 | /* Make core 0 coherent with everything */ |
| 85 | write_gcr_cl_coherence(0xff); |
| 86 | } |
| 87 | |
| 88 | static void __init cps_prepare_cpus(unsigned int max_cpus) |
| 89 | { |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 90 | unsigned ncores, core_vpes, c; |
Paul Burton | 0f4d3d1 | 2014-04-14 12:21:49 +0100 | [diff] [blame^] | 91 | u32 *entry_code; |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 92 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 93 | mips_mt_set_cpuoptions(); |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 94 | |
Paul Burton | 0f4d3d1 | 2014-04-14 12:21:49 +0100 | [diff] [blame^] | 95 | /* Patch the start of mips_cps_core_entry to provide the CM base */ |
| 96 | entry_code = (u32 *)&mips_cps_core_entry; |
| 97 | UASM_i_LA(&entry_code, 3, (long)mips_cm_base); |
| 98 | dma_cache_wback_inv((unsigned long)&mips_cps_core_entry, |
| 99 | (void *)entry_code - (void *)&mips_cps_core_entry); |
| 100 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 101 | /* Allocate core boot configuration structs */ |
| 102 | ncores = mips_cm_numcores(); |
| 103 | mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), |
| 104 | GFP_KERNEL); |
| 105 | if (!mips_cps_core_bootcfg) { |
| 106 | pr_err("Failed to allocate boot config for %u cores\n", ncores); |
| 107 | goto err_out; |
| 108 | } |
| 109 | |
| 110 | /* Allocate VPE boot configuration structs */ |
| 111 | for (c = 0; c < ncores; c++) { |
| 112 | core_vpes = core_vpe_count(c); |
| 113 | mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, |
| 114 | sizeof(*mips_cps_core_bootcfg[c].vpe_config), |
| 115 | GFP_KERNEL); |
| 116 | if (!mips_cps_core_bootcfg[c].vpe_config) { |
| 117 | pr_err("Failed to allocate %u VPE boot configs\n", |
| 118 | core_vpes); |
| 119 | goto err_out; |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | /* Mark this CPU as booted */ |
| 124 | atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask, |
| 125 | 1 << cpu_vpe_id(¤t_cpu_data)); |
| 126 | |
| 127 | return; |
| 128 | err_out: |
| 129 | /* Clean up allocations */ |
| 130 | if (mips_cps_core_bootcfg) { |
| 131 | for (c = 0; c < ncores; c++) |
| 132 | kfree(mips_cps_core_bootcfg[c].vpe_config); |
| 133 | kfree(mips_cps_core_bootcfg); |
| 134 | mips_cps_core_bootcfg = NULL; |
| 135 | } |
| 136 | |
| 137 | /* Effectively disable SMP by declaring CPUs not present */ |
| 138 | for_each_possible_cpu(c) { |
| 139 | if (c == 0) |
| 140 | continue; |
| 141 | set_cpu_present(c, false); |
| 142 | } |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 143 | } |
| 144 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 145 | static void boot_core(unsigned core) |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 146 | { |
| 147 | u32 access; |
| 148 | |
| 149 | /* Select the appropriate core */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 150 | write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 151 | |
| 152 | /* Set its reset vector */ |
| 153 | write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); |
| 154 | |
| 155 | /* Ensure its coherency is disabled */ |
| 156 | write_gcr_co_coherence(0); |
| 157 | |
| 158 | /* Ensure the core can access the GCRs */ |
| 159 | access = read_gcr_access(); |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 160 | access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 161 | write_gcr_access(access); |
| 162 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 163 | if (mips_cpc_present()) { |
| 164 | /* Select the appropriate core */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 165 | write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 166 | |
| 167 | /* Reset the core */ |
| 168 | write_cpc_co_cmd(CPC_Cx_CMD_RESET); |
| 169 | } else { |
| 170 | /* Take the core out of reset */ |
| 171 | write_gcr_co_reset_release(0); |
| 172 | } |
| 173 | |
| 174 | /* The core is now powered up */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 175 | bitmap_set(core_power, core, 1); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 176 | } |
| 177 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 178 | static void remote_vpe_boot(void *dummy) |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 179 | { |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 180 | mips_cps_boot_vpes(); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static void cps_boot_secondary(int cpu, struct task_struct *idle) |
| 184 | { |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 185 | unsigned core = cpu_data[cpu].core; |
| 186 | unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); |
| 187 | struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; |
| 188 | struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 189 | unsigned int remote; |
| 190 | int err; |
| 191 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 192 | vpe_cfg->pc = (unsigned long)&smp_bootstrap; |
| 193 | vpe_cfg->sp = __KSTK_TOS(idle); |
| 194 | vpe_cfg->gp = (unsigned long)task_thread_info(idle); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 195 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 196 | atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); |
| 197 | |
| 198 | if (!test_bit(core, core_power)) { |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 199 | /* Boot a VPE on a powered down core */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 200 | boot_core(core); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 201 | return; |
| 202 | } |
| 203 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 204 | if (core != current_cpu_data.core) { |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 205 | /* Boot a VPE on another powered up core */ |
| 206 | for (remote = 0; remote < NR_CPUS; remote++) { |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 207 | if (cpu_data[remote].core != core) |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 208 | continue; |
| 209 | if (cpu_online(remote)) |
| 210 | break; |
| 211 | } |
| 212 | BUG_ON(remote >= NR_CPUS); |
| 213 | |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 214 | err = smp_call_function_single(remote, remote_vpe_boot, |
| 215 | NULL, 1); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 216 | if (err) |
| 217 | panic("Failed to call remote CPU\n"); |
| 218 | return; |
| 219 | } |
| 220 | |
| 221 | BUG_ON(!cpu_has_mipsmt); |
| 222 | |
| 223 | /* Boot a VPE on this core */ |
Paul Burton | 245a786 | 2014-04-14 12:04:27 +0100 | [diff] [blame] | 224 | mips_cps_boot_vpes(); |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | static void cps_init_secondary(void) |
| 228 | { |
| 229 | /* Disable MT - we only want to run 1 TC per VPE */ |
| 230 | if (cpu_has_mipsmt) |
| 231 | dmt(); |
| 232 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 233 | change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | |
| 234 | STATUSF_IP6 | STATUSF_IP7); |
| 235 | } |
| 236 | |
| 237 | static void cps_smp_finish(void) |
| 238 | { |
| 239 | write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); |
| 240 | |
| 241 | #ifdef CONFIG_MIPS_MT_FPAFF |
| 242 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ |
| 243 | if (cpu_has_fpu) |
| 244 | cpu_set(smp_processor_id(), mt_fpu_cpumask); |
| 245 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
| 246 | |
| 247 | local_irq_enable(); |
| 248 | } |
| 249 | |
| 250 | static void cps_cpus_done(void) |
| 251 | { |
| 252 | } |
| 253 | |
| 254 | static struct plat_smp_ops cps_smp_ops = { |
| 255 | .smp_setup = cps_smp_setup, |
| 256 | .prepare_cpus = cps_prepare_cpus, |
| 257 | .boot_secondary = cps_boot_secondary, |
| 258 | .init_secondary = cps_init_secondary, |
| 259 | .smp_finish = cps_smp_finish, |
| 260 | .send_ipi_single = gic_send_ipi_single, |
| 261 | .send_ipi_mask = gic_send_ipi_mask, |
| 262 | .cpus_done = cps_cpus_done, |
| 263 | }; |
| 264 | |
Paul Burton | 68c1232 | 2014-03-14 16:06:16 +0000 | [diff] [blame] | 265 | bool mips_cps_smp_in_use(void) |
| 266 | { |
| 267 | extern struct plat_smp_ops *mp_ops; |
| 268 | return mp_ops == &cps_smp_ops; |
| 269 | } |
| 270 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 271 | int register_cps_smp_ops(void) |
| 272 | { |
| 273 | if (!mips_cm_present()) { |
| 274 | pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); |
| 275 | return -ENODEV; |
| 276 | } |
| 277 | |
| 278 | /* check we have a GIC - we need one for IPIs */ |
| 279 | if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) { |
| 280 | pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); |
| 281 | return -ENODEV; |
| 282 | } |
| 283 | |
| 284 | register_smp_ops(&cps_smp_ops); |
| 285 | return 0; |
| 286 | } |