Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2018 The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "QG-K: %s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/alarmtimer.h> |
| 16 | #include <linux/cdev.h> |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/ktime.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_irq.h> |
| 23 | #include <linux/of_batterydata.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/power_supply.h> |
| 26 | #include <linux/regmap.h> |
| 27 | #include <linux/uaccess.h> |
| 28 | #include <linux/pmic-voter.h> |
| 29 | #include <linux/qpnp/qpnp-adc.h> |
| 30 | #include <uapi/linux/qg.h> |
| 31 | #include "qg-sdam.h" |
| 32 | #include "qg-core.h" |
| 33 | #include "qg-reg.h" |
| 34 | #include "qg-util.h" |
| 35 | #include "qg-soc.h" |
| 36 | #include "qg-battery-profile.h" |
| 37 | #include "qg-defs.h" |
| 38 | |
| 39 | static int qg_debug_mask; |
| 40 | module_param_named( |
| 41 | debug_mask, qg_debug_mask, int, 0600 |
| 42 | ); |
| 43 | |
| 44 | static int qg_get_battery_temp(struct qpnp_qg *chip, int *batt_temp); |
| 45 | |
| 46 | static bool is_battery_present(struct qpnp_qg *chip) |
| 47 | { |
| 48 | u8 reg = 0; |
| 49 | int rc; |
| 50 | |
| 51 | rc = qg_read(chip, chip->qg_base + QG_STATUS1_REG, ®, 1); |
| 52 | if (rc < 0) |
| 53 | pr_err("Failed to read battery presence, rc=%d\n", rc); |
| 54 | |
| 55 | return !!(reg & BATTERY_PRESENT_BIT); |
| 56 | } |
| 57 | |
| 58 | #define DEBUG_BATT_ID_LOW 6000 |
| 59 | #define DEBUG_BATT_ID_HIGH 8500 |
| 60 | static bool is_debug_batt_id(struct qpnp_qg *chip) |
| 61 | { |
| 62 | if (is_between(DEBUG_BATT_ID_LOW, DEBUG_BATT_ID_HIGH, |
| 63 | chip->batt_id_ohm)) |
| 64 | return true; |
| 65 | |
| 66 | return false; |
| 67 | } |
| 68 | |
| 69 | static int qg_read_ocv(struct qpnp_qg *chip, u32 *ocv_uv, u8 type) |
| 70 | { |
| 71 | int rc, addr; |
| 72 | u64 temp = 0; |
| 73 | |
| 74 | switch (type) { |
| 75 | case GOOD_OCV: |
| 76 | addr = QG_S3_GOOD_OCV_V_DATA0_REG; |
| 77 | break; |
| 78 | case PON_OCV: |
| 79 | addr = QG_S7_PON_OCV_V_DATA0_REG; |
| 80 | break; |
| 81 | default: |
| 82 | pr_err("Invalid OCV type %d\n", type); |
| 83 | return -EINVAL; |
| 84 | } |
| 85 | |
| 86 | rc = qg_read(chip, chip->qg_base + addr, (u8 *)&temp, 2); |
| 87 | if (rc < 0) { |
| 88 | pr_err("Failed to read ocv, rc=%d\n", rc); |
| 89 | return rc; |
| 90 | } |
| 91 | |
| 92 | *ocv_uv = V_RAW_TO_UV(temp); |
| 93 | |
| 94 | pr_debug("%s: OCV=%duV\n", |
| 95 | type == GOOD_OCV ? "GOOD_OCV" : "PON_OCV", *ocv_uv); |
| 96 | |
| 97 | return rc; |
| 98 | } |
| 99 | |
| 100 | static int qg_update_fifo_length(struct qpnp_qg *chip, u8 length) |
| 101 | { |
| 102 | int rc; |
| 103 | |
| 104 | if (!length || length > 8) { |
| 105 | pr_err("Invalid FIFO length %d\n", length); |
| 106 | return -EINVAL; |
| 107 | } |
| 108 | |
| 109 | rc = qg_masked_write(chip, chip->qg_base + QG_S2_NORMAL_MEAS_CTL2_REG, |
| 110 | FIFO_LENGTH_MASK, (length - 1) << FIFO_LENGTH_SHIFT); |
| 111 | if (rc < 0) |
| 112 | pr_err("Failed to write S2 FIFO length, rc=%d\n", rc); |
| 113 | |
| 114 | return rc; |
| 115 | } |
| 116 | |
| 117 | static int qg_master_hold(struct qpnp_qg *chip, bool hold) |
| 118 | { |
| 119 | int rc; |
| 120 | |
| 121 | /* clear the master */ |
| 122 | rc = qg_masked_write(chip, chip->qg_base + QG_DATA_CTL1_REG, |
| 123 | MASTER_HOLD_OR_CLR_BIT, 0); |
| 124 | if (rc < 0) |
| 125 | return rc; |
| 126 | |
| 127 | if (hold) { |
| 128 | /* 0 -> 1, hold the master */ |
| 129 | rc = qg_masked_write(chip, chip->qg_base + QG_DATA_CTL1_REG, |
| 130 | MASTER_HOLD_OR_CLR_BIT, |
| 131 | MASTER_HOLD_OR_CLR_BIT); |
| 132 | if (rc < 0) |
| 133 | return rc; |
| 134 | } |
| 135 | |
| 136 | qg_dbg(chip, QG_DEBUG_STATUS, "Master hold = %d\n", hold); |
| 137 | |
| 138 | return rc; |
| 139 | } |
| 140 | |
| 141 | static void qg_notify_charger(struct qpnp_qg *chip) |
| 142 | { |
| 143 | union power_supply_propval prop = {0, }; |
| 144 | int rc; |
| 145 | |
| 146 | if (!chip->batt_psy) |
| 147 | return; |
| 148 | |
| 149 | if (is_debug_batt_id(chip)) { |
| 150 | prop.intval = 1; |
| 151 | power_supply_set_property(chip->batt_psy, |
| 152 | POWER_SUPPLY_PROP_DEBUG_BATTERY, &prop); |
| 153 | return; |
| 154 | } |
| 155 | |
| 156 | if (!chip->profile_loaded) |
| 157 | return; |
| 158 | |
| 159 | prop.intval = chip->bp.float_volt_uv; |
| 160 | rc = power_supply_set_property(chip->batt_psy, |
| 161 | POWER_SUPPLY_PROP_VOLTAGE_MAX, &prop); |
| 162 | if (rc < 0) { |
| 163 | pr_err("Failed to set voltage_max property on batt_psy, rc=%d\n", |
| 164 | rc); |
| 165 | return; |
| 166 | } |
| 167 | |
| 168 | prop.intval = chip->bp.fastchg_curr_ma * 1000; |
| 169 | rc = power_supply_set_property(chip->batt_psy, |
| 170 | POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, &prop); |
| 171 | if (rc < 0) { |
| 172 | pr_err("Failed to set constant_charge_current_max property on batt_psy, rc=%d\n", |
| 173 | rc); |
| 174 | return; |
| 175 | } |
| 176 | |
| 177 | pr_debug("Notified charger on float voltage and FCC\n"); |
| 178 | } |
| 179 | |
| 180 | static bool is_batt_available(struct qpnp_qg *chip) |
| 181 | { |
| 182 | if (chip->batt_psy) |
| 183 | return true; |
| 184 | |
| 185 | chip->batt_psy = power_supply_get_by_name("battery"); |
| 186 | if (!chip->batt_psy) |
| 187 | return false; |
| 188 | |
| 189 | /* batt_psy is initialized, set the fcc and fv */ |
| 190 | qg_notify_charger(chip); |
| 191 | |
| 192 | return true; |
| 193 | } |
| 194 | |
| 195 | static int qg_update_sdam_params(struct qpnp_qg *chip) |
| 196 | { |
| 197 | int rc, batt_temp = 0, i; |
| 198 | unsigned long rtc_sec = 0; |
| 199 | |
| 200 | rc = get_rtc_time(&rtc_sec); |
| 201 | if (rc < 0) |
| 202 | pr_err("Failed to get RTC time, rc=%d\n", rc); |
| 203 | else |
| 204 | chip->sdam_data[SDAM_TIME_SEC] = rtc_sec; |
| 205 | |
| 206 | rc = qg_get_battery_temp(chip, &batt_temp); |
| 207 | if (rc < 0) |
| 208 | pr_err("Failed to get battery-temp, rc = %d\n", rc); |
| 209 | else |
| 210 | chip->sdam_data[SDAM_TEMP] = (u32)batt_temp; |
| 211 | |
| 212 | rc = qg_sdam_write_all(chip->sdam_data); |
| 213 | if (rc < 0) |
| 214 | pr_err("Failed to write to SDAM rc=%d\n", rc); |
| 215 | |
| 216 | for (i = 0; i < SDAM_MAX; i++) |
| 217 | qg_dbg(chip, QG_DEBUG_STATUS, "SDAM write param %d value=%d\n", |
| 218 | i, chip->sdam_data[i]); |
| 219 | |
| 220 | return rc; |
| 221 | } |
| 222 | |
| 223 | static int qg_process_fifo(struct qpnp_qg *chip, u32 fifo_length) |
| 224 | { |
| 225 | int rc = 0, i, j = 0, temp; |
| 226 | u8 v_fifo[MAX_FIFO_LENGTH * 2], i_fifo[MAX_FIFO_LENGTH * 2]; |
| 227 | u32 sample_interval = 0, sample_count = 0, fifo_v = 0, fifo_i = 0; |
| 228 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 229 | chip->kdata.fifo_time = (u32)ktime_get_seconds(); |
| 230 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 231 | if (!fifo_length) { |
| 232 | pr_debug("No FIFO data\n"); |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO length=%d\n", fifo_length); |
| 237 | |
| 238 | rc = get_sample_interval(chip, &sample_interval); |
| 239 | if (rc < 0) { |
| 240 | pr_err("Failed to get FIFO sample interval, rc=%d\n", rc); |
| 241 | return rc; |
| 242 | } |
| 243 | |
| 244 | rc = get_sample_count(chip, &sample_count); |
| 245 | if (rc < 0) { |
| 246 | pr_err("Failed to get FIFO sample count, rc=%d\n", rc); |
| 247 | return rc; |
| 248 | } |
| 249 | |
| 250 | for (i = 0; i < fifo_length * 2; i = i + 2, j++) { |
| 251 | rc = qg_read(chip, chip->qg_base + QG_V_FIFO0_DATA0_REG + i, |
| 252 | &v_fifo[i], 2); |
| 253 | if (rc < 0) { |
| 254 | pr_err("Failed to read QG_V_FIFO, rc=%d\n", rc); |
| 255 | return rc; |
| 256 | } |
| 257 | rc = qg_read(chip, chip->qg_base + QG_I_FIFO0_DATA0_REG + i, |
| 258 | &i_fifo[i], 2); |
| 259 | if (rc < 0) { |
| 260 | pr_err("Failed to read QG_I_FIFO, rc=%d\n", rc); |
| 261 | return rc; |
| 262 | } |
| 263 | |
| 264 | fifo_v = v_fifo[i] | (v_fifo[i + 1] << 8); |
| 265 | fifo_i = i_fifo[i] | (i_fifo[i + 1] << 8); |
| 266 | |
| 267 | temp = sign_extend32(fifo_i, 15); |
| 268 | |
| 269 | chip->kdata.fifo[j].v = V_RAW_TO_UV(fifo_v); |
| 270 | chip->kdata.fifo[j].i = I_RAW_TO_UA(temp); |
| 271 | chip->kdata.fifo[j].interval = sample_interval; |
| 272 | chip->kdata.fifo[j].count = sample_count; |
| 273 | |
| 274 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO %d raw_v=%d uV=%d raw_i=%d uA=%d interval=%d count=%d\n", |
| 275 | j, fifo_v, |
| 276 | chip->kdata.fifo[j].v, |
| 277 | fifo_i, |
| 278 | (int)chip->kdata.fifo[j].i, |
| 279 | chip->kdata.fifo[j].interval, |
| 280 | chip->kdata.fifo[j].count); |
| 281 | } |
| 282 | |
| 283 | chip->kdata.fifo_length = fifo_length; |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 284 | chip->kdata.seq_no = chip->seq_no++ % U32_MAX; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 285 | |
| 286 | return rc; |
| 287 | } |
| 288 | |
| 289 | static int qg_process_accumulator(struct qpnp_qg *chip) |
| 290 | { |
| 291 | int rc, sample_interval = 0; |
| 292 | u8 count, index = chip->kdata.fifo_length; |
| 293 | u64 acc_v = 0, acc_i = 0; |
| 294 | s64 temp = 0; |
| 295 | |
| 296 | rc = qg_read(chip, chip->qg_base + QG_ACCUM_CNT_RT_REG, |
| 297 | &count, 1); |
| 298 | if (rc < 0) { |
| 299 | pr_err("Failed to read ACC count, rc=%d\n", rc); |
| 300 | return rc; |
| 301 | } |
| 302 | |
| 303 | if (!count) { |
| 304 | pr_debug("No ACCUMULATOR data!\n"); |
| 305 | return 0; |
| 306 | } |
| 307 | |
| 308 | rc = get_sample_interval(chip, &sample_interval); |
| 309 | if (rc < 0) { |
| 310 | pr_err("Failed to get ACC sample interval, rc=%d\n", rc); |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | rc = qg_read(chip, chip->qg_base + QG_V_ACCUM_DATA0_RT_REG, |
| 315 | (u8 *)&acc_v, 3); |
| 316 | if (rc < 0) { |
| 317 | pr_err("Failed to read ACC RT V data, rc=%d\n", rc); |
| 318 | return rc; |
| 319 | } |
| 320 | |
| 321 | rc = qg_read(chip, chip->qg_base + QG_I_ACCUM_DATA0_RT_REG, |
| 322 | (u8 *)&acc_i, 3); |
| 323 | if (rc < 0) { |
| 324 | pr_err("Failed to read ACC RT I data, rc=%d\n", rc); |
| 325 | return rc; |
| 326 | } |
| 327 | |
| 328 | temp = sign_extend64(acc_i, 23); |
| 329 | |
| 330 | chip->kdata.fifo[index].v = V_RAW_TO_UV(div_u64(acc_v, count)); |
| 331 | chip->kdata.fifo[index].i = I_RAW_TO_UA(div_s64(temp, count)); |
| 332 | chip->kdata.fifo[index].interval = sample_interval; |
| 333 | chip->kdata.fifo[index].count = count; |
| 334 | chip->kdata.fifo_length++; |
| 335 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 336 | if (chip->kdata.fifo_length == 1) /* Only accumulator data */ |
| 337 | chip->kdata.seq_no = chip->seq_no++ % U32_MAX; |
| 338 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 339 | qg_dbg(chip, QG_DEBUG_FIFO, "ACC v_avg=%duV i_avg=%duA interval=%d count=%d\n", |
| 340 | chip->kdata.fifo[index].v, |
| 341 | (int)chip->kdata.fifo[index].i, |
| 342 | chip->kdata.fifo[index].interval, |
| 343 | chip->kdata.fifo[index].count); |
| 344 | |
| 345 | return rc; |
| 346 | } |
| 347 | |
| 348 | static int qg_process_rt_fifo(struct qpnp_qg *chip) |
| 349 | { |
| 350 | int rc; |
| 351 | u32 fifo_length = 0; |
| 352 | |
| 353 | /* Get the real-time FIFO length */ |
| 354 | rc = get_fifo_length(chip, &fifo_length, true); |
| 355 | if (rc < 0) { |
| 356 | pr_err("Failed to read RT FIFO length, rc=%d\n", rc); |
| 357 | return rc; |
| 358 | } |
| 359 | |
| 360 | rc = qg_process_fifo(chip, fifo_length); |
| 361 | if (rc < 0) { |
| 362 | pr_err("Failed to process FIFO data, rc=%d\n", rc); |
| 363 | return rc; |
| 364 | } |
| 365 | |
| 366 | rc = qg_process_accumulator(chip); |
| 367 | if (rc < 0) { |
| 368 | pr_err("Failed to process ACC data, rc=%d\n", rc); |
| 369 | return rc; |
| 370 | } |
| 371 | |
| 372 | return rc; |
| 373 | } |
| 374 | |
| 375 | #define VBAT_LOW_HYST_UV 50000 /* 50mV */ |
| 376 | static int qg_vbat_low_wa(struct qpnp_qg *chip) |
| 377 | { |
| 378 | int rc, i; |
| 379 | u32 vbat_low_uv = chip->dt.vbatt_low_mv * 1000 + VBAT_LOW_HYST_UV; |
| 380 | |
| 381 | if (!(chip->wa_flags & QG_VBAT_LOW_WA) || !chip->vbat_low) |
| 382 | return 0; |
| 383 | |
| 384 | /* |
| 385 | * PMI632 1.0 does not generate a falling VBAT_LOW IRQ. |
| 386 | * To exit from VBAT_LOW config, check if any of the FIFO |
| 387 | * averages is > vbat_low threshold and reconfigure the |
| 388 | * FIFO length to normal. |
| 389 | */ |
| 390 | for (i = 0; i < chip->kdata.fifo_length; i++) { |
| 391 | if (chip->kdata.fifo[i].v > vbat_low_uv) { |
| 392 | rc = qg_master_hold(chip, true); |
| 393 | if (rc < 0) { |
| 394 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 395 | goto done; |
| 396 | } |
| 397 | rc = qg_update_fifo_length(chip, |
| 398 | chip->dt.s2_fifo_length); |
| 399 | if (rc < 0) |
| 400 | goto done; |
| 401 | |
| 402 | rc = qg_master_hold(chip, false); |
| 403 | if (rc < 0) { |
| 404 | pr_err("Failed to release master, rc=%d\n", rc); |
| 405 | goto done; |
| 406 | } |
| 407 | /* FIFOs restarted */ |
| 408 | chip->last_fifo_update_time = ktime_get(); |
| 409 | |
| 410 | chip->vbat_low = false; |
| 411 | pr_info("Exit VBAT_LOW vbat_avg=%duV vbat_low=%duV updated fifo_length=%d\n", |
| 412 | chip->kdata.fifo[i].v, vbat_low_uv, |
| 413 | chip->dt.s2_fifo_length); |
| 414 | break; |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | return 0; |
| 419 | |
| 420 | done: |
| 421 | qg_master_hold(chip, false); |
| 422 | return rc; |
| 423 | } |
| 424 | |
| 425 | #define MIN_FIFO_FULL_TIME_MS 12000 |
| 426 | static int process_rt_fifo_data(struct qpnp_qg *chip, |
| 427 | bool vbat_low, bool update_smb) |
| 428 | { |
| 429 | int rc = 0; |
| 430 | ktime_t now = ktime_get(); |
| 431 | s64 time_delta; |
| 432 | |
| 433 | /* |
| 434 | * Reject the FIFO read event if there are back-to-back requests |
| 435 | * This is done to gaurantee that there is always a minimum FIFO |
| 436 | * data to be processed, ignore this if vbat_low is set. |
| 437 | */ |
| 438 | time_delta = ktime_ms_delta(now, chip->last_user_update_time); |
| 439 | |
| 440 | qg_dbg(chip, QG_DEBUG_FIFO, "time_delta=%lld ms vbat_low=%d\n", |
| 441 | time_delta, vbat_low); |
| 442 | |
| 443 | if (time_delta > MIN_FIFO_FULL_TIME_MS || vbat_low || update_smb) { |
| 444 | rc = qg_master_hold(chip, true); |
| 445 | if (rc < 0) { |
| 446 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 447 | goto done; |
| 448 | } |
| 449 | |
| 450 | rc = qg_process_rt_fifo(chip); |
| 451 | if (rc < 0) { |
| 452 | pr_err("Failed to process FIFO real-time, rc=%d\n", rc); |
| 453 | goto done; |
| 454 | } |
| 455 | |
| 456 | if (vbat_low) { |
| 457 | /* change FIFO length */ |
| 458 | rc = qg_update_fifo_length(chip, |
| 459 | chip->dt.s2_vbat_low_fifo_length); |
| 460 | if (rc < 0) |
| 461 | goto done; |
| 462 | |
| 463 | qg_dbg(chip, QG_DEBUG_STATUS, |
| 464 | "FIFO length updated to %d vbat_low=%d\n", |
| 465 | chip->dt.s2_vbat_low_fifo_length, |
| 466 | vbat_low); |
| 467 | } |
| 468 | |
| 469 | if (update_smb) { |
| 470 | rc = qg_masked_write(chip, chip->qg_base + |
| 471 | QG_MODE_CTL1_REG, PARALLEL_IBAT_SENSE_EN_BIT, |
| 472 | chip->parallel_enabled ? |
| 473 | PARALLEL_IBAT_SENSE_EN_BIT : 0); |
| 474 | if (rc < 0) { |
| 475 | pr_err("Failed to update SMB_EN, rc=%d\n", rc); |
| 476 | goto done; |
| 477 | } |
| 478 | qg_dbg(chip, QG_DEBUG_STATUS, "Parallel SENSE %d\n", |
| 479 | chip->parallel_enabled); |
| 480 | } |
| 481 | |
| 482 | rc = qg_master_hold(chip, false); |
| 483 | if (rc < 0) { |
| 484 | pr_err("Failed to release master, rc=%d\n", rc); |
| 485 | goto done; |
| 486 | } |
| 487 | /* FIFOs restarted */ |
| 488 | chip->last_fifo_update_time = ktime_get(); |
| 489 | |
| 490 | /* signal the read thread */ |
| 491 | chip->data_ready = true; |
| 492 | wake_up_interruptible(&chip->qg_wait_q); |
| 493 | chip->last_user_update_time = now; |
| 494 | |
| 495 | /* vote to stay awake until userspace reads data */ |
| 496 | vote(chip->awake_votable, FIFO_RT_DONE_VOTER, true, 0); |
| 497 | } else { |
| 498 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO processing too early time_delta=%lld\n", |
| 499 | time_delta); |
| 500 | } |
| 501 | done: |
| 502 | qg_master_hold(chip, false); |
| 503 | return rc; |
| 504 | } |
| 505 | |
| 506 | static void process_udata_work(struct work_struct *work) |
| 507 | { |
| 508 | struct qpnp_qg *chip = container_of(work, |
| 509 | struct qpnp_qg, udata_work); |
| 510 | int rc; |
| 511 | |
| 512 | if (chip->udata.param[QG_SOC].valid) { |
| 513 | qg_dbg(chip, QG_DEBUG_SOC, "udata SOC=%d last SOC=%d\n", |
| 514 | chip->udata.param[QG_SOC].data, chip->catch_up_soc); |
| 515 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 516 | chip->catch_up_soc = chip->udata.param[QG_SOC].data; |
| 517 | qg_scale_soc(chip, false); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 518 | |
| 519 | /* update parameters to SDAM */ |
| 520 | chip->sdam_data[SDAM_SOC] = |
| 521 | chip->udata.param[QG_SOC].data; |
| 522 | chip->sdam_data[SDAM_OCV_UV] = |
| 523 | chip->udata.param[QG_OCV_UV].data; |
| 524 | chip->sdam_data[SDAM_RBAT_MOHM] = |
| 525 | chip->udata.param[QG_RBAT_MOHM].data; |
| 526 | chip->sdam_data[SDAM_VALID] = 1; |
| 527 | |
| 528 | rc = qg_update_sdam_params(chip); |
| 529 | if (rc < 0) |
| 530 | pr_err("Failed to update SDAM params, rc=%d\n", rc); |
| 531 | } |
| 532 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 533 | if (chip->udata.param[QG_CHARGE_COUNTER].valid) |
| 534 | chip->charge_counter_uah = |
| 535 | chip->udata.param[QG_CHARGE_COUNTER].data; |
| 536 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 537 | vote(chip->awake_votable, UDATA_READY_VOTER, false, 0); |
| 538 | } |
| 539 | |
| 540 | static irqreturn_t qg_default_irq_handler(int irq, void *data) |
| 541 | { |
| 542 | struct qpnp_qg *chip = data; |
| 543 | |
| 544 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 545 | |
| 546 | return IRQ_HANDLED; |
| 547 | } |
| 548 | |
| 549 | #define MAX_FIFO_DELTA_PERCENT 10 |
| 550 | static irqreturn_t qg_fifo_update_done_handler(int irq, void *data) |
| 551 | { |
| 552 | ktime_t now = ktime_get(); |
| 553 | int rc, hw_delta_ms = 0, margin_ms = 0; |
| 554 | u32 fifo_length = 0; |
| 555 | s64 time_delta_ms = 0; |
| 556 | struct qpnp_qg *chip = data; |
| 557 | |
| 558 | time_delta_ms = ktime_ms_delta(now, chip->last_fifo_update_time); |
| 559 | chip->last_fifo_update_time = now; |
| 560 | |
| 561 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 562 | mutex_lock(&chip->data_lock); |
| 563 | |
| 564 | rc = get_fifo_length(chip, &fifo_length, false); |
| 565 | if (rc < 0) { |
| 566 | pr_err("Failed to get FIFO length, rc=%d\n", rc); |
| 567 | goto done; |
| 568 | } |
| 569 | |
| 570 | rc = qg_process_fifo(chip, fifo_length); |
| 571 | if (rc < 0) { |
| 572 | pr_err("Failed to process QG FIFO, rc=%d\n", rc); |
| 573 | goto done; |
| 574 | } |
| 575 | |
| 576 | rc = qg_vbat_low_wa(chip); |
| 577 | if (rc < 0) { |
| 578 | pr_err("Failed to apply VBAT LOW WA, rc=%d\n", rc); |
| 579 | goto done; |
| 580 | } |
| 581 | |
| 582 | rc = get_fifo_done_time(chip, false, &hw_delta_ms); |
| 583 | if (rc < 0) |
| 584 | hw_delta_ms = 0; |
| 585 | else |
| 586 | margin_ms = (hw_delta_ms * MAX_FIFO_DELTA_PERCENT) / 100; |
| 587 | |
| 588 | if (abs(hw_delta_ms - time_delta_ms) < margin_ms) { |
| 589 | chip->kdata.param[QG_FIFO_TIME_DELTA].data = time_delta_ms; |
| 590 | chip->kdata.param[QG_FIFO_TIME_DELTA].valid = true; |
| 591 | qg_dbg(chip, QG_DEBUG_FIFO, "FIFO_done time_delta_ms=%lld\n", |
| 592 | time_delta_ms); |
| 593 | } |
| 594 | |
| 595 | /* signal the read thread */ |
| 596 | chip->data_ready = true; |
| 597 | wake_up_interruptible(&chip->qg_wait_q); |
| 598 | |
| 599 | /* vote to stay awake until userspace reads data */ |
| 600 | vote(chip->awake_votable, FIFO_DONE_VOTER, true, 0); |
| 601 | |
| 602 | done: |
| 603 | mutex_unlock(&chip->data_lock); |
| 604 | return IRQ_HANDLED; |
| 605 | } |
| 606 | |
| 607 | static irqreturn_t qg_vbat_low_handler(int irq, void *data) |
| 608 | { |
| 609 | int rc; |
| 610 | struct qpnp_qg *chip = data; |
| 611 | u8 status = 0; |
| 612 | |
| 613 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 614 | mutex_lock(&chip->data_lock); |
| 615 | |
| 616 | rc = qg_read(chip, chip->qg_base + QG_INT_RT_STS_REG, &status, 1); |
| 617 | if (rc < 0) { |
| 618 | pr_err("Failed to read RT status, rc=%d\n", rc); |
| 619 | goto done; |
| 620 | } |
| 621 | chip->vbat_low = !!(status & VBAT_LOW_INT_RT_STS_BIT); |
| 622 | |
| 623 | rc = process_rt_fifo_data(chip, chip->vbat_low, false); |
| 624 | if (rc < 0) |
| 625 | pr_err("Failed to process RT FIFO data, rc=%d\n", rc); |
| 626 | |
| 627 | qg_dbg(chip, QG_DEBUG_IRQ, "VBAT_LOW = %d\n", chip->vbat_low); |
| 628 | done: |
| 629 | mutex_unlock(&chip->data_lock); |
| 630 | return IRQ_HANDLED; |
| 631 | } |
| 632 | |
| 633 | static irqreturn_t qg_vbat_empty_handler(int irq, void *data) |
| 634 | { |
| 635 | struct qpnp_qg *chip = data; |
| 636 | u32 ocv_uv = 0; |
| 637 | |
| 638 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 639 | pr_warn("VBATT EMPTY SOC = 0\n"); |
| 640 | |
| 641 | chip->catch_up_soc = 0; |
| 642 | qg_scale_soc(chip, true); |
| 643 | |
| 644 | qg_sdam_read(SDAM_OCV_UV, &ocv_uv); |
| 645 | chip->sdam_data[SDAM_SOC] = 0; |
| 646 | chip->sdam_data[SDAM_OCV_UV] = ocv_uv; |
| 647 | chip->sdam_data[SDAM_VALID] = 1; |
| 648 | |
| 649 | qg_update_sdam_params(chip); |
| 650 | |
| 651 | if (chip->qg_psy) |
| 652 | power_supply_changed(chip->qg_psy); |
| 653 | |
| 654 | return IRQ_HANDLED; |
| 655 | } |
| 656 | |
| 657 | static irqreturn_t qg_good_ocv_handler(int irq, void *data) |
| 658 | { |
| 659 | int rc; |
| 660 | u32 ocv_uv; |
| 661 | struct qpnp_qg *chip = data; |
| 662 | |
| 663 | qg_dbg(chip, QG_DEBUG_IRQ, "IRQ triggered\n"); |
| 664 | |
| 665 | mutex_lock(&chip->data_lock); |
| 666 | |
| 667 | rc = qg_read_ocv(chip, &ocv_uv, GOOD_OCV); |
| 668 | if (rc < 0) { |
| 669 | pr_err("Failed to read good_ocv, rc=%d\n", rc); |
| 670 | goto done; |
| 671 | } |
| 672 | |
| 673 | chip->kdata.param[QG_GOOD_OCV_UV].data = ocv_uv; |
| 674 | chip->kdata.param[QG_GOOD_OCV_UV].valid = true; |
| 675 | |
| 676 | vote(chip->awake_votable, GOOD_OCV_VOTER, true, 0); |
| 677 | |
| 678 | /* signal the readd thread */ |
| 679 | chip->data_ready = true; |
| 680 | wake_up_interruptible(&chip->qg_wait_q); |
| 681 | done: |
| 682 | mutex_unlock(&chip->data_lock); |
| 683 | return IRQ_HANDLED; |
| 684 | } |
| 685 | |
| 686 | static struct qg_irq_info qg_irqs[] = { |
| 687 | [QG_BATT_MISSING_IRQ] = { |
| 688 | .name = "qg-batt-missing", |
| 689 | .handler = qg_default_irq_handler, |
| 690 | }, |
| 691 | [QG_VBATT_LOW_IRQ] = { |
| 692 | .name = "qg-vbat-low", |
| 693 | .handler = qg_vbat_low_handler, |
| 694 | .wake = true, |
| 695 | }, |
| 696 | [QG_VBATT_EMPTY_IRQ] = { |
| 697 | .name = "qg-vbat-empty", |
| 698 | .handler = qg_vbat_empty_handler, |
| 699 | .wake = true, |
| 700 | }, |
| 701 | [QG_FIFO_UPDATE_DONE_IRQ] = { |
| 702 | .name = "qg-fifo-done", |
| 703 | .handler = qg_fifo_update_done_handler, |
| 704 | .wake = true, |
| 705 | }, |
| 706 | [QG_GOOD_OCV_IRQ] = { |
| 707 | .name = "qg-good-ocv", |
| 708 | .handler = qg_good_ocv_handler, |
| 709 | .wake = true, |
| 710 | }, |
| 711 | [QG_FSM_STAT_CHG_IRQ] = { |
| 712 | .name = "qg-fsm-state-chg", |
| 713 | .handler = qg_default_irq_handler, |
| 714 | }, |
| 715 | [QG_EVENT_IRQ] = { |
| 716 | .name = "qg-event", |
| 717 | .handler = qg_default_irq_handler, |
| 718 | }, |
| 719 | }; |
| 720 | |
| 721 | static int qg_awake_cb(struct votable *votable, void *data, int awake, |
| 722 | const char *client) |
| 723 | { |
| 724 | struct qpnp_qg *chip = data; |
| 725 | |
| 726 | if (awake) |
| 727 | pm_stay_awake(chip->dev); |
| 728 | else |
| 729 | pm_relax(chip->dev); |
| 730 | |
| 731 | pr_debug("client: %s awake: %d\n", client, awake); |
| 732 | return 0; |
| 733 | } |
| 734 | |
| 735 | static int qg_fifo_irq_disable_cb(struct votable *votable, void *data, |
| 736 | int disable, const char *client) |
| 737 | { |
| 738 | if (disable) { |
| 739 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].wake) |
| 740 | disable_irq_wake( |
| 741 | qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 742 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq) |
| 743 | disable_irq_nosync( |
| 744 | qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 745 | } else { |
| 746 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq) |
| 747 | enable_irq(qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 748 | if (qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].wake) |
| 749 | enable_irq_wake( |
| 750 | qg_irqs[QG_FIFO_UPDATE_DONE_IRQ].irq); |
| 751 | } |
| 752 | |
| 753 | return 0; |
| 754 | } |
| 755 | |
| 756 | static int qg_vbatt_irq_disable_cb(struct votable *votable, void *data, |
| 757 | int disable, const char *client) |
| 758 | { |
| 759 | if (disable) { |
| 760 | if (qg_irqs[QG_VBATT_LOW_IRQ].wake) |
| 761 | disable_irq_wake(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 762 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].wake) |
| 763 | disable_irq_wake(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 764 | if (qg_irqs[QG_VBATT_LOW_IRQ].irq) |
| 765 | disable_irq_nosync(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 766 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].irq) |
| 767 | disable_irq_nosync(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 768 | } else { |
| 769 | if (qg_irqs[QG_VBATT_LOW_IRQ].irq) |
| 770 | enable_irq(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 771 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].irq) |
| 772 | enable_irq(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 773 | if (qg_irqs[QG_VBATT_LOW_IRQ].wake) |
| 774 | enable_irq_wake(qg_irqs[QG_VBATT_LOW_IRQ].irq); |
| 775 | if (qg_irqs[QG_VBATT_EMPTY_IRQ].wake) |
| 776 | enable_irq_wake(qg_irqs[QG_VBATT_EMPTY_IRQ].irq); |
| 777 | } |
| 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | |
| 782 | static int qg_good_ocv_irq_disable_cb(struct votable *votable, void *data, |
| 783 | int disable, const char *client) |
| 784 | { |
| 785 | if (disable) { |
| 786 | if (qg_irqs[QG_GOOD_OCV_IRQ].wake) |
| 787 | disable_irq_wake(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 788 | if (qg_irqs[QG_GOOD_OCV_IRQ].irq) |
| 789 | disable_irq_nosync(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 790 | } else { |
| 791 | if (qg_irqs[QG_GOOD_OCV_IRQ].irq) |
| 792 | enable_irq(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 793 | if (qg_irqs[QG_GOOD_OCV_IRQ].wake) |
| 794 | enable_irq_wake(qg_irqs[QG_GOOD_OCV_IRQ].irq); |
| 795 | } |
| 796 | |
| 797 | return 0; |
| 798 | } |
| 799 | |
| 800 | #define DEFAULT_BATT_TYPE "Unknown Battery" |
| 801 | #define MISSING_BATT_TYPE "Missing Battery" |
| 802 | #define DEBUG_BATT_TYPE "Debug Board" |
| 803 | static const char *qg_get_battery_type(struct qpnp_qg *chip) |
| 804 | { |
| 805 | if (chip->battery_missing) |
| 806 | return MISSING_BATT_TYPE; |
| 807 | |
| 808 | if (is_debug_batt_id(chip)) |
| 809 | return DEBUG_BATT_TYPE; |
| 810 | |
| 811 | if (chip->bp.batt_type_str) { |
| 812 | if (chip->profile_loaded) |
| 813 | return chip->bp.batt_type_str; |
| 814 | } |
| 815 | |
| 816 | return DEFAULT_BATT_TYPE; |
| 817 | } |
| 818 | |
| 819 | static int qg_get_battery_current(struct qpnp_qg *chip, int *ibat_ua) |
| 820 | { |
| 821 | int rc = 0, last_ibat = 0; |
| 822 | |
| 823 | if (chip->battery_missing) { |
| 824 | *ibat_ua = 0; |
| 825 | return 0; |
| 826 | } |
| 827 | |
| 828 | rc = qg_read(chip, chip->qg_base + QG_LAST_ADC_I_DATA0_REG, |
| 829 | (u8 *)&last_ibat, 2); |
| 830 | if (rc < 0) { |
| 831 | pr_err("Failed to read LAST_ADV_I reg, rc=%d\n", rc); |
| 832 | return rc; |
| 833 | } |
| 834 | |
| 835 | last_ibat = sign_extend32(last_ibat, 15); |
| 836 | *ibat_ua = I_RAW_TO_UA(last_ibat); |
| 837 | |
| 838 | return rc; |
| 839 | } |
| 840 | |
| 841 | static int qg_get_battery_voltage(struct qpnp_qg *chip, int *vbat_uv) |
| 842 | { |
| 843 | int rc = 0; |
| 844 | u64 last_vbat = 0; |
| 845 | |
| 846 | if (chip->battery_missing) { |
| 847 | *vbat_uv = 3700000; |
| 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | rc = qg_read(chip, chip->qg_base + QG_LAST_ADC_V_DATA0_REG, |
| 852 | (u8 *)&last_vbat, 2); |
| 853 | if (rc < 0) { |
| 854 | pr_err("Failed to read LAST_ADV_V reg, rc=%d\n", rc); |
| 855 | return rc; |
| 856 | } |
| 857 | |
| 858 | *vbat_uv = V_RAW_TO_UV(last_vbat); |
| 859 | |
| 860 | return rc; |
| 861 | } |
| 862 | |
| 863 | #define DEBUG_BATT_SOC 67 |
| 864 | #define BATT_MISSING_SOC 50 |
| 865 | #define EMPTY_SOC 0 |
| 866 | static int qg_get_battery_capacity(struct qpnp_qg *chip, int *soc) |
| 867 | { |
| 868 | if (is_debug_batt_id(chip)) { |
| 869 | *soc = DEBUG_BATT_SOC; |
| 870 | return 0; |
| 871 | } |
| 872 | |
| 873 | if (chip->battery_missing || !chip->profile_loaded) { |
| 874 | *soc = BATT_MISSING_SOC; |
| 875 | return 0; |
| 876 | } |
| 877 | |
| 878 | *soc = chip->msoc; |
| 879 | |
| 880 | return 0; |
| 881 | } |
| 882 | |
| 883 | static int qg_get_battery_temp(struct qpnp_qg *chip, int *temp) |
| 884 | { |
| 885 | int rc = 0; |
| 886 | struct qpnp_vadc_result result; |
| 887 | |
| 888 | if (chip->battery_missing) { |
| 889 | *temp = 250; |
| 890 | return 0; |
| 891 | } |
| 892 | |
| 893 | rc = qpnp_vadc_read(chip->vadc_dev, VADC_BAT_THERM_PU2, &result); |
| 894 | if (rc) { |
| 895 | pr_err("Failed reading adc channel=%d, rc=%d\n", |
| 896 | VADC_BAT_THERM_PU2, rc); |
| 897 | return rc; |
| 898 | } |
| 899 | pr_debug("batt_temp = %lld meas = 0x%llx\n", |
| 900 | result.physical, result.measurement); |
| 901 | |
| 902 | *temp = (int)result.physical; |
| 903 | |
| 904 | return rc; |
| 905 | } |
| 906 | |
| 907 | static int qg_psy_set_property(struct power_supply *psy, |
| 908 | enum power_supply_property psp, |
| 909 | const union power_supply_propval *pval) |
| 910 | { |
| 911 | return 0; |
| 912 | } |
| 913 | |
| 914 | static int qg_psy_get_property(struct power_supply *psy, |
| 915 | enum power_supply_property psp, |
| 916 | union power_supply_propval *pval) |
| 917 | { |
| 918 | struct qpnp_qg *chip = power_supply_get_drvdata(psy); |
| 919 | int rc = 0; |
| 920 | |
| 921 | pval->intval = 0; |
| 922 | |
| 923 | switch (psp) { |
| 924 | case POWER_SUPPLY_PROP_CAPACITY: |
| 925 | rc = qg_get_battery_capacity(chip, &pval->intval); |
| 926 | break; |
| 927 | case POWER_SUPPLY_PROP_VOLTAGE_NOW: |
| 928 | rc = qg_get_battery_voltage(chip, &pval->intval); |
| 929 | break; |
| 930 | case POWER_SUPPLY_PROP_CURRENT_NOW: |
| 931 | rc = qg_get_battery_current(chip, &pval->intval); |
| 932 | break; |
| 933 | case POWER_SUPPLY_PROP_VOLTAGE_OCV: |
| 934 | rc = qg_sdam_read(SDAM_OCV_UV, &pval->intval); |
| 935 | break; |
| 936 | case POWER_SUPPLY_PROP_TEMP: |
| 937 | rc = qg_get_battery_temp(chip, &pval->intval); |
| 938 | break; |
| 939 | case POWER_SUPPLY_PROP_RESISTANCE_ID: |
| 940 | pval->intval = chip->batt_id_ohm; |
| 941 | break; |
| 942 | case POWER_SUPPLY_PROP_DEBUG_BATTERY: |
| 943 | pval->intval = is_debug_batt_id(chip); |
| 944 | break; |
| 945 | case POWER_SUPPLY_PROP_RESISTANCE: |
| 946 | rc = qg_sdam_read(SDAM_RBAT_MOHM, &pval->intval); |
| 947 | if (!rc) |
| 948 | pval->intval *= 1000; |
| 949 | break; |
| 950 | case POWER_SUPPLY_PROP_RESISTANCE_CAPACITIVE: |
| 951 | pval->intval = chip->dt.rbat_conn_mohm; |
| 952 | break; |
| 953 | case POWER_SUPPLY_PROP_BATTERY_TYPE: |
| 954 | pval->strval = qg_get_battery_type(chip); |
| 955 | break; |
| 956 | case POWER_SUPPLY_PROP_VOLTAGE_MIN: |
| 957 | pval->intval = chip->dt.vbatt_cutoff_mv * 1000; |
| 958 | break; |
| 959 | case POWER_SUPPLY_PROP_VOLTAGE_MAX: |
| 960 | pval->intval = chip->bp.float_volt_uv; |
| 961 | break; |
| 962 | case POWER_SUPPLY_PROP_BATT_FULL_CURRENT: |
| 963 | pval->intval = chip->dt.iterm_ma * 1000; |
| 964 | break; |
| 965 | case POWER_SUPPLY_PROP_BATT_PROFILE_VERSION: |
| 966 | pval->intval = chip->bp.qg_profile_version; |
| 967 | break; |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 968 | case POWER_SUPPLY_PROP_CHARGE_COUNTER: |
| 969 | pval->intval = chip->charge_counter_uah; |
| 970 | break; |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 971 | default: |
| 972 | pr_debug("Unsupported property %d\n", psp); |
| 973 | break; |
| 974 | } |
| 975 | |
| 976 | return rc; |
| 977 | } |
| 978 | |
| 979 | static int qg_property_is_writeable(struct power_supply *psy, |
| 980 | enum power_supply_property psp) |
| 981 | { |
| 982 | return 0; |
| 983 | } |
| 984 | |
| 985 | static enum power_supply_property qg_psy_props[] = { |
| 986 | POWER_SUPPLY_PROP_CAPACITY, |
| 987 | POWER_SUPPLY_PROP_TEMP, |
| 988 | POWER_SUPPLY_PROP_VOLTAGE_NOW, |
| 989 | POWER_SUPPLY_PROP_VOLTAGE_OCV, |
| 990 | POWER_SUPPLY_PROP_CURRENT_NOW, |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 991 | POWER_SUPPLY_PROP_CHARGE_COUNTER, |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 992 | POWER_SUPPLY_PROP_RESISTANCE, |
| 993 | POWER_SUPPLY_PROP_RESISTANCE_ID, |
| 994 | POWER_SUPPLY_PROP_RESISTANCE_CAPACITIVE, |
| 995 | POWER_SUPPLY_PROP_DEBUG_BATTERY, |
| 996 | POWER_SUPPLY_PROP_BATTERY_TYPE, |
| 997 | POWER_SUPPLY_PROP_VOLTAGE_MIN, |
| 998 | POWER_SUPPLY_PROP_VOLTAGE_MAX, |
| 999 | POWER_SUPPLY_PROP_BATT_FULL_CURRENT, |
| 1000 | POWER_SUPPLY_PROP_BATT_PROFILE_VERSION, |
| 1001 | }; |
| 1002 | |
| 1003 | static const struct power_supply_desc qg_psy_desc = { |
| 1004 | .name = "bms", |
| 1005 | .type = POWER_SUPPLY_TYPE_BMS, |
| 1006 | .properties = qg_psy_props, |
| 1007 | .num_properties = ARRAY_SIZE(qg_psy_props), |
| 1008 | .get_property = qg_psy_get_property, |
| 1009 | .set_property = qg_psy_set_property, |
| 1010 | .property_is_writeable = qg_property_is_writeable, |
| 1011 | }; |
| 1012 | |
| 1013 | static int qg_charge_full_update(struct qpnp_qg *chip) |
| 1014 | { |
| 1015 | |
| 1016 | vote(chip->good_ocv_irq_disable_votable, |
| 1017 | QG_INIT_STATE_IRQ_DISABLE, !chip->charge_done, 0); |
| 1018 | |
| 1019 | /* TODO: add hold-soc-at-full logic */ |
| 1020 | return 0; |
| 1021 | } |
| 1022 | |
| 1023 | static int qg_parallel_status_update(struct qpnp_qg *chip) |
| 1024 | { |
| 1025 | int rc; |
| 1026 | bool parallel_enabled = is_parallel_enabled(chip); |
| 1027 | |
| 1028 | if (parallel_enabled == chip->parallel_enabled) |
| 1029 | return 0; |
| 1030 | |
| 1031 | chip->parallel_enabled = parallel_enabled; |
| 1032 | qg_dbg(chip, QG_DEBUG_STATUS, |
| 1033 | "Parallel status changed Enabled=%d\n", parallel_enabled); |
| 1034 | |
| 1035 | mutex_lock(&chip->data_lock); |
| 1036 | |
| 1037 | rc = process_rt_fifo_data(chip, false, true); |
| 1038 | if (rc < 0) |
| 1039 | pr_err("Failed to process RT FIFO data, rc=%d\n", rc); |
| 1040 | |
| 1041 | mutex_unlock(&chip->data_lock); |
| 1042 | |
| 1043 | return 0; |
| 1044 | } |
| 1045 | |
| 1046 | static int qg_usb_status_update(struct qpnp_qg *chip) |
| 1047 | { |
| 1048 | bool usb_present = is_usb_present(chip); |
| 1049 | |
| 1050 | if (chip->usb_present != usb_present) { |
| 1051 | qg_dbg(chip, QG_DEBUG_STATUS, |
| 1052 | "USB status changed Present=%d\n", |
| 1053 | usb_present); |
| 1054 | qg_scale_soc(chip, false); |
| 1055 | } |
| 1056 | |
| 1057 | chip->usb_present = usb_present; |
| 1058 | |
| 1059 | return 0; |
| 1060 | } |
| 1061 | |
| 1062 | static void qg_status_change_work(struct work_struct *work) |
| 1063 | { |
| 1064 | struct qpnp_qg *chip = container_of(work, |
| 1065 | struct qpnp_qg, qg_status_change_work); |
| 1066 | union power_supply_propval prop = {0, }; |
| 1067 | int rc = 0; |
| 1068 | |
| 1069 | if (!is_batt_available(chip)) { |
| 1070 | pr_debug("batt-psy not available\n"); |
| 1071 | goto out; |
| 1072 | } |
| 1073 | |
| 1074 | rc = power_supply_get_property(chip->batt_psy, |
| 1075 | POWER_SUPPLY_PROP_STATUS, &prop); |
| 1076 | if (rc < 0) |
| 1077 | pr_err("Failed to get charger status, rc=%d\n", rc); |
| 1078 | else |
| 1079 | chip->charge_status = prop.intval; |
| 1080 | |
| 1081 | rc = power_supply_get_property(chip->batt_psy, |
| 1082 | POWER_SUPPLY_PROP_CHARGE_DONE, &prop); |
| 1083 | if (rc < 0) |
| 1084 | pr_err("Failed to get charge done status, rc=%d\n", rc); |
| 1085 | else |
| 1086 | chip->charge_done = prop.intval; |
| 1087 | |
| 1088 | rc = qg_parallel_status_update(chip); |
| 1089 | if (rc < 0) |
| 1090 | pr_err("Failed to update parallel-status, rc=%d\n", rc); |
| 1091 | |
| 1092 | rc = qg_usb_status_update(chip); |
| 1093 | if (rc < 0) |
| 1094 | pr_err("Failed to update usb status, rc=%d\n", rc); |
| 1095 | |
| 1096 | rc = qg_charge_full_update(chip); |
| 1097 | if (rc < 0) |
| 1098 | pr_err("Failed in charge_full_update, rc=%d\n", rc); |
| 1099 | out: |
| 1100 | pm_relax(chip->dev); |
| 1101 | } |
| 1102 | |
| 1103 | static int qg_notifier_cb(struct notifier_block *nb, |
| 1104 | unsigned long event, void *data) |
| 1105 | { |
| 1106 | struct power_supply *psy = data; |
| 1107 | struct qpnp_qg *chip = container_of(nb, struct qpnp_qg, nb); |
| 1108 | |
| 1109 | if (event != PSY_EVENT_PROP_CHANGED) |
| 1110 | return NOTIFY_OK; |
| 1111 | |
| 1112 | if (work_pending(&chip->qg_status_change_work)) |
| 1113 | return NOTIFY_OK; |
| 1114 | |
| 1115 | if ((strcmp(psy->desc->name, "battery") == 0) |
| 1116 | || (strcmp(psy->desc->name, "parallel") == 0) |
| 1117 | || (strcmp(psy->desc->name, "usb") == 0)) { |
| 1118 | /* |
| 1119 | * We cannot vote for awake votable here as that takes |
| 1120 | * a mutex lock and this is executed in an atomic context. |
| 1121 | */ |
| 1122 | pm_stay_awake(chip->dev); |
| 1123 | schedule_work(&chip->qg_status_change_work); |
| 1124 | } |
| 1125 | |
| 1126 | return NOTIFY_OK; |
| 1127 | } |
| 1128 | |
| 1129 | static int qg_init_psy(struct qpnp_qg *chip) |
| 1130 | { |
| 1131 | struct power_supply_config qg_psy_cfg; |
| 1132 | int rc; |
| 1133 | |
| 1134 | qg_psy_cfg.drv_data = chip; |
| 1135 | qg_psy_cfg.of_node = NULL; |
| 1136 | qg_psy_cfg.supplied_to = NULL; |
| 1137 | qg_psy_cfg.num_supplicants = 0; |
| 1138 | chip->qg_psy = devm_power_supply_register(chip->dev, |
| 1139 | &qg_psy_desc, &qg_psy_cfg); |
| 1140 | if (IS_ERR_OR_NULL(chip->qg_psy)) { |
| 1141 | pr_err("Failed to register qg_psy rc = %ld\n", |
| 1142 | PTR_ERR(chip->qg_psy)); |
| 1143 | return -ENODEV; |
| 1144 | } |
| 1145 | |
| 1146 | chip->nb.notifier_call = qg_notifier_cb; |
| 1147 | rc = power_supply_reg_notifier(&chip->nb); |
| 1148 | if (rc < 0) |
| 1149 | pr_err("Failed register psy notifier rc = %d\n", rc); |
| 1150 | |
| 1151 | return rc; |
| 1152 | } |
| 1153 | |
| 1154 | static ssize_t qg_device_read(struct file *file, char __user *buf, size_t count, |
| 1155 | loff_t *ppos) |
| 1156 | { |
| 1157 | int rc; |
| 1158 | struct qpnp_qg *chip = file->private_data; |
| 1159 | unsigned long data_size = sizeof(chip->kdata); |
| 1160 | |
| 1161 | /* non-blocking access, return */ |
| 1162 | if (!chip->data_ready && (file->f_flags & O_NONBLOCK)) |
| 1163 | return -EAGAIN; |
| 1164 | |
| 1165 | /* blocking access wait on data_ready */ |
| 1166 | if (!(file->f_flags & O_NONBLOCK)) { |
| 1167 | rc = wait_event_interruptible(chip->qg_wait_q, |
| 1168 | chip->data_ready); |
| 1169 | if (rc < 0) { |
| 1170 | pr_debug("Failed wait! rc=%d\n", rc); |
| 1171 | return rc; |
| 1172 | } |
| 1173 | } |
| 1174 | |
| 1175 | mutex_lock(&chip->data_lock); |
| 1176 | |
| 1177 | if (!chip->data_ready) { |
| 1178 | pr_debug("No Data, false wakeup\n"); |
| 1179 | rc = -EFAULT; |
| 1180 | goto fail_read; |
| 1181 | } |
| 1182 | |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 1183 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1184 | if (copy_to_user(buf, &chip->kdata, data_size)) { |
| 1185 | pr_err("Failed in copy_to_user\n"); |
| 1186 | rc = -EFAULT; |
| 1187 | goto fail_read; |
| 1188 | } |
| 1189 | chip->data_ready = false; |
| 1190 | |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1191 | /* release all wake sources */ |
| 1192 | vote(chip->awake_votable, GOOD_OCV_VOTER, false, 0); |
| 1193 | vote(chip->awake_votable, FIFO_DONE_VOTER, false, 0); |
| 1194 | vote(chip->awake_votable, FIFO_RT_DONE_VOTER, false, 0); |
| 1195 | vote(chip->awake_votable, SUSPEND_DATA_VOTER, false, 0); |
| 1196 | |
| 1197 | qg_dbg(chip, QG_DEBUG_DEVICE, |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 1198 | "QG device read complete Seq_no=%u Size=%ld\n", |
| 1199 | chip->kdata.seq_no, data_size); |
| 1200 | |
| 1201 | /* clear data */ |
| 1202 | memset(&chip->kdata, 0, sizeof(chip->kdata)); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1203 | |
| 1204 | mutex_unlock(&chip->data_lock); |
| 1205 | |
| 1206 | return data_size; |
| 1207 | |
| 1208 | fail_read: |
| 1209 | mutex_unlock(&chip->data_lock); |
| 1210 | return rc; |
| 1211 | } |
| 1212 | |
| 1213 | static ssize_t qg_device_write(struct file *file, const char __user *buf, |
| 1214 | size_t count, loff_t *ppos) |
| 1215 | { |
| 1216 | int rc = -EINVAL; |
| 1217 | struct qpnp_qg *chip = file->private_data; |
| 1218 | unsigned long data_size = sizeof(chip->udata); |
| 1219 | |
| 1220 | mutex_lock(&chip->data_lock); |
| 1221 | if (count == 0) { |
| 1222 | pr_err("No data!\n"); |
| 1223 | goto fail; |
| 1224 | } |
| 1225 | |
| 1226 | if (count != 0 && count < data_size) { |
Kiran Gunda | 0f5de04 | 2018-03-02 13:02:22 +0530 | [diff] [blame^] | 1227 | pr_err("Invalid datasize %zu expected %lu\n", count, data_size); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1228 | goto fail; |
| 1229 | } |
| 1230 | |
| 1231 | if (copy_from_user(&chip->udata, buf, data_size)) { |
| 1232 | pr_err("Failed in copy_from_user\n"); |
| 1233 | rc = -EFAULT; |
| 1234 | goto fail; |
| 1235 | } |
| 1236 | |
| 1237 | rc = data_size; |
| 1238 | vote(chip->awake_votable, UDATA_READY_VOTER, true, 0); |
| 1239 | schedule_work(&chip->udata_work); |
| 1240 | qg_dbg(chip, QG_DEBUG_DEVICE, "QG write complete size=%d\n", rc); |
| 1241 | fail: |
| 1242 | mutex_unlock(&chip->data_lock); |
| 1243 | return rc; |
| 1244 | } |
| 1245 | |
| 1246 | static unsigned int qg_device_poll(struct file *file, poll_table *wait) |
| 1247 | { |
| 1248 | struct qpnp_qg *chip = file->private_data; |
| 1249 | unsigned int mask; |
| 1250 | |
| 1251 | poll_wait(file, &chip->qg_wait_q, wait); |
| 1252 | |
| 1253 | if (chip->data_ready) |
| 1254 | mask = POLLIN | POLLRDNORM; |
| 1255 | else |
| 1256 | mask = POLLERR; |
| 1257 | |
| 1258 | return mask; |
| 1259 | } |
| 1260 | |
| 1261 | static int qg_device_open(struct inode *inode, struct file *file) |
| 1262 | { |
| 1263 | struct qpnp_qg *chip = container_of(inode->i_cdev, |
| 1264 | struct qpnp_qg, qg_cdev); |
| 1265 | |
| 1266 | file->private_data = chip; |
| 1267 | qg_dbg(chip, QG_DEBUG_DEVICE, "QG device opened!\n"); |
| 1268 | |
| 1269 | return 0; |
| 1270 | } |
| 1271 | |
| 1272 | static const struct file_operations qg_fops = { |
| 1273 | .owner = THIS_MODULE, |
| 1274 | .open = qg_device_open, |
| 1275 | .read = qg_device_read, |
| 1276 | .write = qg_device_write, |
| 1277 | .poll = qg_device_poll, |
| 1278 | }; |
| 1279 | |
| 1280 | static int qg_register_device(struct qpnp_qg *chip) |
| 1281 | { |
| 1282 | int rc; |
| 1283 | |
| 1284 | rc = alloc_chrdev_region(&chip->dev_no, 0, 1, "qg"); |
| 1285 | if (rc < 0) { |
| 1286 | pr_err("Failed to allocate chardev rc=%d\n", rc); |
| 1287 | return rc; |
| 1288 | } |
| 1289 | |
| 1290 | cdev_init(&chip->qg_cdev, &qg_fops); |
| 1291 | rc = cdev_add(&chip->qg_cdev, chip->dev_no, 1); |
| 1292 | if (rc < 0) { |
| 1293 | pr_err("Failed to cdev_add rc=%d\n", rc); |
| 1294 | goto unregister_chrdev; |
| 1295 | } |
| 1296 | |
| 1297 | chip->qg_class = class_create(THIS_MODULE, "qg"); |
| 1298 | if (IS_ERR_OR_NULL(chip->qg_class)) { |
| 1299 | pr_err("Failed to create qg class\n"); |
| 1300 | rc = -EINVAL; |
| 1301 | goto delete_cdev; |
| 1302 | } |
| 1303 | chip->qg_device = device_create(chip->qg_class, NULL, chip->dev_no, |
| 1304 | NULL, "qg"); |
| 1305 | if (IS_ERR(chip->qg_device)) { |
| 1306 | pr_err("Failed to create qg_device\n"); |
| 1307 | rc = -EINVAL; |
| 1308 | goto destroy_class; |
| 1309 | } |
| 1310 | |
| 1311 | qg_dbg(chip, QG_DEBUG_DEVICE, "'/dev/qg' successfully created\n"); |
| 1312 | |
| 1313 | return 0; |
| 1314 | |
| 1315 | destroy_class: |
| 1316 | class_destroy(chip->qg_class); |
| 1317 | delete_cdev: |
| 1318 | cdev_del(&chip->qg_cdev); |
| 1319 | unregister_chrdev: |
| 1320 | unregister_chrdev_region(chip->dev_no, 1); |
| 1321 | return rc; |
| 1322 | } |
| 1323 | |
| 1324 | #define BID_RPULL_OHM 100000 |
| 1325 | #define BID_VREF_MV 1875 |
| 1326 | static int get_batt_id_ohm(struct qpnp_qg *chip, u32 *batt_id_ohm) |
| 1327 | { |
| 1328 | int rc, batt_id_mv; |
| 1329 | int64_t denom; |
| 1330 | struct qpnp_vadc_result result; |
| 1331 | |
| 1332 | /* Read battery-id */ |
| 1333 | rc = qpnp_vadc_read(chip->vadc_dev, VADC_BAT_ID_PU2, &result); |
| 1334 | if (rc) { |
| 1335 | pr_err("Failed to read BATT_ID over vadc, rc=%d\n", rc); |
| 1336 | return rc; |
| 1337 | } |
| 1338 | |
Kiran Gunda | 0f5de04 | 2018-03-02 13:02:22 +0530 | [diff] [blame^] | 1339 | batt_id_mv = div_s64(result.physical, 1000); |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1340 | if (batt_id_mv == 0) { |
| 1341 | pr_debug("batt_id_mv = 0 from ADC\n"); |
| 1342 | return 0; |
| 1343 | } |
| 1344 | |
| 1345 | denom = div64_s64(BID_VREF_MV * 1000, batt_id_mv) - 1000; |
| 1346 | if (denom <= 0) { |
| 1347 | /* batt id connector might be open, return 0 kohms */ |
| 1348 | return 0; |
| 1349 | } |
| 1350 | |
| 1351 | *batt_id_ohm = div64_u64(BID_RPULL_OHM * 1000 + denom / 2, denom); |
| 1352 | |
| 1353 | qg_dbg(chip, QG_DEBUG_PROFILE, "batt_id_mv=%d, batt_id_ohm=%d\n", |
| 1354 | batt_id_mv, *batt_id_ohm); |
| 1355 | |
| 1356 | return 0; |
| 1357 | } |
| 1358 | |
| 1359 | static int qg_load_battery_profile(struct qpnp_qg *chip) |
| 1360 | { |
| 1361 | struct device_node *node = chip->dev->of_node; |
| 1362 | struct device_node *batt_node, *profile_node; |
| 1363 | int rc; |
| 1364 | |
| 1365 | batt_node = of_find_node_by_name(node, "qcom,battery-data"); |
| 1366 | if (!batt_node) { |
| 1367 | pr_err("Batterydata not available\n"); |
| 1368 | return -ENXIO; |
| 1369 | } |
| 1370 | |
| 1371 | profile_node = of_batterydata_get_best_profile(batt_node, |
| 1372 | chip->batt_id_ohm / 1000, NULL); |
| 1373 | if (IS_ERR(profile_node)) { |
| 1374 | rc = PTR_ERR(profile_node); |
| 1375 | pr_err("Failed to detect valid QG battery profile %d\n", rc); |
| 1376 | return rc; |
| 1377 | } |
| 1378 | |
| 1379 | rc = of_property_read_string(profile_node, "qcom,battery-type", |
| 1380 | &chip->bp.batt_type_str); |
| 1381 | if (rc < 0) { |
| 1382 | pr_err("Failed to detect battery type rc:%d\n", rc); |
| 1383 | return rc; |
| 1384 | } |
| 1385 | |
| 1386 | rc = qg_batterydata_init(profile_node); |
| 1387 | if (rc < 0) { |
| 1388 | pr_err("Failed to initialize battery-profile rc=%d\n", rc); |
| 1389 | return rc; |
| 1390 | } |
| 1391 | |
| 1392 | rc = of_property_read_u32(profile_node, "qcom,max-voltage-uv", |
| 1393 | &chip->bp.float_volt_uv); |
| 1394 | if (rc < 0) { |
| 1395 | pr_err("Failed to read battery float-voltage rc:%d\n", rc); |
| 1396 | chip->bp.float_volt_uv = -EINVAL; |
| 1397 | } |
| 1398 | |
| 1399 | rc = of_property_read_u32(profile_node, "qcom,fastchg-current-ma", |
| 1400 | &chip->bp.fastchg_curr_ma); |
| 1401 | if (rc < 0) { |
| 1402 | pr_err("Failed to read battery fastcharge current rc:%d\n", rc); |
| 1403 | chip->bp.fastchg_curr_ma = -EINVAL; |
| 1404 | } |
| 1405 | |
| 1406 | rc = of_property_read_u32(profile_node, "qcom,qg-batt-profile-ver", |
| 1407 | &chip->bp.qg_profile_version); |
| 1408 | if (rc < 0) { |
| 1409 | pr_err("Failed to read QG profile version rc:%d\n", rc); |
| 1410 | chip->bp.qg_profile_version = -EINVAL; |
| 1411 | } |
| 1412 | |
| 1413 | qg_dbg(chip, QG_DEBUG_PROFILE, "profile=%s FV=%duV FCC=%dma\n", |
| 1414 | chip->bp.batt_type_str, chip->bp.float_volt_uv, |
| 1415 | chip->bp.fastchg_curr_ma); |
| 1416 | |
| 1417 | return 0; |
| 1418 | } |
| 1419 | |
| 1420 | static int qg_setup_battery(struct qpnp_qg *chip) |
| 1421 | { |
| 1422 | int rc; |
| 1423 | |
| 1424 | if (!is_battery_present(chip)) { |
| 1425 | qg_dbg(chip, QG_DEBUG_PROFILE, "Battery Missing!\n"); |
| 1426 | chip->battery_missing = true; |
| 1427 | chip->profile_loaded = false; |
| 1428 | } else { |
| 1429 | /* battery present */ |
| 1430 | rc = get_batt_id_ohm(chip, &chip->batt_id_ohm); |
| 1431 | if (rc < 0) { |
| 1432 | pr_err("Failed to detect batt_id rc=%d\n", rc); |
| 1433 | chip->profile_loaded = false; |
| 1434 | } else { |
| 1435 | rc = qg_load_battery_profile(chip); |
| 1436 | if (rc < 0) |
| 1437 | pr_err("Failed to load battery-profile rc=%d\n", |
| 1438 | rc); |
| 1439 | else |
| 1440 | chip->profile_loaded = true; |
| 1441 | } |
| 1442 | } |
| 1443 | |
| 1444 | qg_dbg(chip, QG_DEBUG_PROFILE, "battery_missing=%d batt_id_ohm=%d Ohm profile_loaded=%d profile=%s\n", |
| 1445 | chip->battery_missing, chip->batt_id_ohm, |
| 1446 | chip->profile_loaded, chip->bp.batt_type_str); |
| 1447 | |
| 1448 | return 0; |
| 1449 | } |
| 1450 | |
| 1451 | static int qg_determine_pon_soc(struct qpnp_qg *chip) |
| 1452 | { |
| 1453 | u8 status; |
| 1454 | int rc, batt_temp = 0; |
| 1455 | bool use_pon_ocv = false; |
| 1456 | unsigned long rtc_sec = 0; |
| 1457 | u32 ocv_uv = 0, soc = 0, shutdown[SDAM_MAX] = {0}; |
| 1458 | |
| 1459 | if (!chip->profile_loaded) { |
| 1460 | qg_dbg(chip, QG_DEBUG_PON, "No Profile, skipping PON soc\n"); |
| 1461 | return 0; |
| 1462 | } |
| 1463 | |
| 1464 | rc = qg_get_battery_temp(chip, &batt_temp); |
| 1465 | if (rc) { |
| 1466 | pr_err("Failed to read BATT_TEMP at PON rc=%d\n", rc); |
| 1467 | return rc; |
| 1468 | } |
| 1469 | |
| 1470 | rc = qg_read(chip, chip->qg_base + QG_STATUS2_REG, |
| 1471 | &status, 1); |
| 1472 | if (rc < 0) { |
| 1473 | pr_err("Failed to read status2 register rc=%d\n", rc); |
| 1474 | return rc; |
| 1475 | } |
| 1476 | |
| 1477 | if (status & GOOD_OCV_BIT) { |
| 1478 | qg_dbg(chip, QG_DEBUG_PON, "Using GOOD_OCV @ PON\n"); |
| 1479 | rc = qg_read_ocv(chip, &ocv_uv, GOOD_OCV); |
| 1480 | if (rc < 0) { |
| 1481 | pr_err("Failed to read good_ocv rc=%d\n", rc); |
| 1482 | use_pon_ocv = true; |
| 1483 | } else { |
| 1484 | rc = lookup_soc_ocv(&soc, ocv_uv, batt_temp, false); |
| 1485 | if (rc < 0) { |
| 1486 | pr_err("Failed to lookup SOC (GOOD_OCV) @ PON rc=%d\n", |
| 1487 | rc); |
| 1488 | use_pon_ocv = true; |
| 1489 | } |
| 1490 | } |
| 1491 | } else { |
| 1492 | rc = get_rtc_time(&rtc_sec); |
| 1493 | if (rc < 0) { |
| 1494 | pr_err("Failed to read RTC time rc=%d\n", rc); |
| 1495 | use_pon_ocv = true; |
| 1496 | goto done; |
| 1497 | } |
| 1498 | |
| 1499 | rc = qg_sdam_read_all(shutdown); |
| 1500 | if (rc < 0) { |
| 1501 | pr_err("Failed to read shutdown params rc=%d\n", rc); |
| 1502 | use_pon_ocv = true; |
| 1503 | goto done; |
| 1504 | } |
Anirudh Ghayal | 07fbf79 | 2018-02-26 11:38:33 +0530 | [diff] [blame] | 1505 | qg_dbg(chip, QG_DEBUG_PON, "Shutdown: Valid=%d SOC=%d OCV=%duV time=%dsecs, time_now=%ldsecs\n", |
| 1506 | shutdown[SDAM_VALID], |
Anirudh Ghayal | e6b2f4a | 2018-01-02 19:35:40 +0530 | [diff] [blame] | 1507 | shutdown[SDAM_SOC], |
| 1508 | shutdown[SDAM_OCV_UV], |
| 1509 | shutdown[SDAM_TIME_SEC], |
| 1510 | rtc_sec); |
| 1511 | /* |
| 1512 | * Use the shutdown SOC if |
| 1513 | * 1. The device was powered off for < 180 seconds |
| 1514 | * 2. SDAM read is a success & SDAM data is valid |
| 1515 | */ |
| 1516 | use_pon_ocv = true; |
| 1517 | if (!rc && shutdown[SDAM_VALID] && |
| 1518 | ((rtc_sec - shutdown[SDAM_TIME_SEC]) < 180)) { |
| 1519 | use_pon_ocv = false; |
| 1520 | ocv_uv = shutdown[SDAM_OCV_UV]; |
| 1521 | soc = shutdown[SDAM_SOC]; |
| 1522 | qg_dbg(chip, QG_DEBUG_PON, "Using SHUTDOWN_SOC @ PON\n"); |
| 1523 | } |
| 1524 | } |
| 1525 | done: |
| 1526 | /* |
| 1527 | * Use PON OCV if |
| 1528 | * OCV_UV is not set or shutdown SOC is invalid. |
| 1529 | */ |
| 1530 | if (use_pon_ocv || !ocv_uv || !rtc_sec) { |
| 1531 | qg_dbg(chip, QG_DEBUG_PON, "Using PON_OCV @ PON\n"); |
| 1532 | rc = qg_read_ocv(chip, &ocv_uv, PON_OCV); |
| 1533 | if (rc < 0) { |
| 1534 | pr_err("Failed to read HW PON ocv rc=%d\n", rc); |
| 1535 | return rc; |
| 1536 | } |
| 1537 | rc = lookup_soc_ocv(&soc, ocv_uv, batt_temp, false); |
| 1538 | if (rc < 0) { |
| 1539 | pr_err("Failed to lookup SOC @ PON rc=%d\n", rc); |
| 1540 | soc = 50; |
| 1541 | } |
| 1542 | } |
| 1543 | |
| 1544 | chip->pon_soc = chip->catch_up_soc = chip->msoc = soc; |
| 1545 | chip->kdata.param[QG_PON_OCV_UV].data = ocv_uv; |
| 1546 | chip->kdata.param[QG_PON_OCV_UV].valid = true; |
| 1547 | |
| 1548 | /* write back to SDAM */ |
| 1549 | chip->sdam_data[SDAM_SOC] = soc; |
| 1550 | chip->sdam_data[SDAM_OCV_UV] = ocv_uv; |
| 1551 | chip->sdam_data[SDAM_VALID] = 1; |
| 1552 | |
| 1553 | rc = qg_write_monotonic_soc(chip, chip->msoc); |
| 1554 | if (rc < 0) |
| 1555 | pr_err("Failed to update MSOC register rc=%d\n", rc); |
| 1556 | |
| 1557 | rc = qg_update_sdam_params(chip); |
| 1558 | if (rc < 0) |
| 1559 | pr_err("Failed to update sdam params rc=%d\n", rc); |
| 1560 | |
| 1561 | pr_info("use_pon_ocv=%d good_ocv=%d ocv_uv=%duV temp=%d soc=%d\n", |
| 1562 | use_pon_ocv, !!(status & GOOD_OCV_BIT), |
| 1563 | ocv_uv, batt_temp, chip->msoc); |
| 1564 | |
| 1565 | return 0; |
| 1566 | } |
| 1567 | |
| 1568 | static int qg_set_wa_flags(struct qpnp_qg *chip) |
| 1569 | { |
| 1570 | switch (chip->pmic_rev_id->pmic_subtype) { |
| 1571 | case PMI632_SUBTYPE: |
| 1572 | if (chip->pmic_rev_id->rev4 == PMI632_V1P0_REV4) |
| 1573 | chip->wa_flags |= QG_VBAT_LOW_WA; |
| 1574 | break; |
| 1575 | default: |
| 1576 | pr_err("Unsupported PMIC subtype %d\n", |
| 1577 | chip->pmic_rev_id->pmic_subtype); |
| 1578 | return -EINVAL; |
| 1579 | } |
| 1580 | |
| 1581 | qg_dbg(chip, QG_DEBUG_PON, "wa_flags = %x\n", chip->wa_flags); |
| 1582 | |
| 1583 | return 0; |
| 1584 | } |
| 1585 | |
| 1586 | static int qg_hw_init(struct qpnp_qg *chip) |
| 1587 | { |
| 1588 | int rc, temp; |
| 1589 | u8 reg; |
| 1590 | |
| 1591 | rc = qg_set_wa_flags(chip); |
| 1592 | if (rc < 0) { |
| 1593 | pr_err("Failed to update PMIC type flags, rc=%d\n", rc); |
| 1594 | return rc; |
| 1595 | } |
| 1596 | |
| 1597 | rc = qg_master_hold(chip, true); |
| 1598 | if (rc < 0) { |
| 1599 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 1600 | goto done_fifo; |
| 1601 | } |
| 1602 | |
| 1603 | rc = qg_process_rt_fifo(chip); |
| 1604 | if (rc < 0) { |
| 1605 | pr_err("Failed to process FIFO real-time, rc=%d\n", rc); |
| 1606 | goto done_fifo; |
| 1607 | } |
| 1608 | |
| 1609 | /* update the changed S2 fifo DT parameters */ |
| 1610 | if (chip->dt.s2_fifo_length > 0) { |
| 1611 | rc = qg_update_fifo_length(chip, chip->dt.s2_fifo_length); |
| 1612 | if (rc < 0) |
| 1613 | goto done_fifo; |
| 1614 | } |
| 1615 | |
| 1616 | if (chip->dt.s2_acc_length > 0) { |
| 1617 | reg = ilog2(chip->dt.s2_acc_length) - 1; |
| 1618 | rc = qg_masked_write(chip, chip->qg_base + |
| 1619 | QG_S2_NORMAL_MEAS_CTL2_REG, |
| 1620 | NUM_OF_ACCUM_MASK, reg); |
| 1621 | if (rc < 0) { |
| 1622 | pr_err("Failed to write S2 ACC length, rc=%d\n", rc); |
| 1623 | goto done_fifo; |
| 1624 | } |
| 1625 | } |
| 1626 | |
| 1627 | if (chip->dt.s2_acc_intvl_ms > 0) { |
| 1628 | reg = chip->dt.s2_acc_intvl_ms / 10; |
| 1629 | rc = qg_write(chip, chip->qg_base + |
| 1630 | QG_S2_NORMAL_MEAS_CTL3_REG, |
| 1631 | ®, 1); |
| 1632 | if (rc < 0) { |
| 1633 | pr_err("Failed to write S2 ACC intrvl, rc=%d\n", rc); |
| 1634 | goto done_fifo; |
| 1635 | } |
| 1636 | } |
| 1637 | |
| 1638 | /* signal the read thread */ |
| 1639 | chip->data_ready = true; |
| 1640 | wake_up_interruptible(&chip->qg_wait_q); |
| 1641 | |
| 1642 | done_fifo: |
| 1643 | rc = qg_master_hold(chip, false); |
| 1644 | if (rc < 0) { |
| 1645 | pr_err("Failed to release master, rc=%d\n", rc); |
| 1646 | return rc; |
| 1647 | } |
| 1648 | chip->last_fifo_update_time = ktime_get(); |
| 1649 | |
| 1650 | if (chip->dt.ocv_timer_expiry_min != -EINVAL) { |
| 1651 | if (chip->dt.ocv_timer_expiry_min < 2) |
| 1652 | chip->dt.ocv_timer_expiry_min = 2; |
| 1653 | else if (chip->dt.ocv_timer_expiry_min > 30) |
| 1654 | chip->dt.ocv_timer_expiry_min = 30; |
| 1655 | |
| 1656 | reg = (chip->dt.ocv_timer_expiry_min - 2) / 4; |
| 1657 | rc = qg_masked_write(chip, |
| 1658 | chip->qg_base + QG_S3_SLEEP_OCV_MEAS_CTL4_REG, |
| 1659 | SLEEP_IBAT_QUALIFIED_LENGTH_MASK, reg); |
| 1660 | if (rc < 0) { |
| 1661 | pr_err("Failed to write OCV timer, rc=%d\n", rc); |
| 1662 | return rc; |
| 1663 | } |
| 1664 | } |
| 1665 | |
| 1666 | if (chip->dt.ocv_tol_threshold_uv != -EINVAL) { |
| 1667 | if (chip->dt.ocv_tol_threshold_uv < 0) |
| 1668 | chip->dt.ocv_tol_threshold_uv = 0; |
| 1669 | else if (chip->dt.ocv_tol_threshold_uv > 12262) |
| 1670 | chip->dt.ocv_tol_threshold_uv = 12262; |
| 1671 | |
| 1672 | reg = chip->dt.ocv_tol_threshold_uv / 195; |
| 1673 | rc = qg_masked_write(chip, |
| 1674 | chip->qg_base + QG_S3_SLEEP_OCV_TREND_CTL2_REG, |
| 1675 | TREND_TOL_MASK, reg); |
| 1676 | if (rc < 0) { |
| 1677 | pr_err("Failed to write OCV tol-thresh, rc=%d\n", rc); |
| 1678 | return rc; |
| 1679 | } |
| 1680 | } |
| 1681 | |
| 1682 | if (chip->dt.s3_entry_fifo_length != -EINVAL) { |
| 1683 | if (chip->dt.s3_entry_fifo_length < 1) |
| 1684 | chip->dt.s3_entry_fifo_length = 1; |
| 1685 | else if (chip->dt.s3_entry_fifo_length > 8) |
| 1686 | chip->dt.s3_entry_fifo_length = 8; |
| 1687 | |
| 1688 | reg = chip->dt.s3_entry_fifo_length - 1; |
| 1689 | rc = qg_masked_write(chip, |
| 1690 | chip->qg_base + QG_S3_SLEEP_OCV_IBAT_CTL1_REG, |
| 1691 | SLEEP_IBAT_QUALIFIED_LENGTH_MASK, reg); |
| 1692 | if (rc < 0) { |
| 1693 | pr_err("Failed to write S3-entry fifo-length, rc=%d\n", |
| 1694 | rc); |
| 1695 | return rc; |
| 1696 | } |
| 1697 | } |
| 1698 | |
| 1699 | if (chip->dt.s3_entry_ibat_ua != -EINVAL) { |
| 1700 | if (chip->dt.s3_entry_ibat_ua < 0) |
| 1701 | chip->dt.s3_entry_ibat_ua = 0; |
| 1702 | else if (chip->dt.s3_entry_ibat_ua > 155550) |
| 1703 | chip->dt.s3_entry_ibat_ua = 155550; |
| 1704 | |
| 1705 | reg = chip->dt.s3_entry_ibat_ua / 610; |
| 1706 | rc = qg_write(chip, chip->qg_base + |
| 1707 | QG_S3_ENTRY_IBAT_THRESHOLD_REG, |
| 1708 | ®, 1); |
| 1709 | if (rc < 0) { |
| 1710 | pr_err("Failed to write S3-entry ibat-uA, rc=%d\n", rc); |
| 1711 | return rc; |
| 1712 | } |
| 1713 | } |
| 1714 | |
| 1715 | if (chip->dt.s3_exit_ibat_ua != -EINVAL) { |
| 1716 | if (chip->dt.s3_exit_ibat_ua < 0) |
| 1717 | chip->dt.s3_exit_ibat_ua = 0; |
| 1718 | else if (chip->dt.s3_exit_ibat_ua > 155550) |
| 1719 | chip->dt.s3_exit_ibat_ua = 155550; |
| 1720 | |
| 1721 | rc = qg_read(chip, chip->qg_base + |
| 1722 | QG_S3_ENTRY_IBAT_THRESHOLD_REG, |
| 1723 | ®, 1); |
| 1724 | if (rc < 0) { |
| 1725 | pr_err("Failed to read S3-entry ibat-uA, rc=%d", rc); |
| 1726 | return rc; |
| 1727 | } |
| 1728 | temp = reg * 610; |
| 1729 | if (chip->dt.s3_exit_ibat_ua < temp) |
| 1730 | chip->dt.s3_exit_ibat_ua = temp; |
| 1731 | else |
| 1732 | chip->dt.s3_exit_ibat_ua -= temp; |
| 1733 | |
| 1734 | reg = chip->dt.s3_exit_ibat_ua / 610; |
| 1735 | rc = qg_write(chip, |
| 1736 | chip->qg_base + QG_S3_EXIT_IBAT_THRESHOLD_REG, |
| 1737 | ®, 1); |
| 1738 | if (rc < 0) { |
| 1739 | pr_err("Failed to write S3-entry ibat-uA, rc=%d\n", rc); |
| 1740 | return rc; |
| 1741 | } |
| 1742 | } |
| 1743 | |
| 1744 | /* vbat low */ |
| 1745 | if (chip->dt.vbatt_low_mv < 0) |
| 1746 | chip->dt.vbatt_low_mv = 0; |
| 1747 | else if (chip->dt.vbatt_low_mv > 12750) |
| 1748 | chip->dt.vbatt_low_mv = 12750; |
| 1749 | |
| 1750 | reg = chip->dt.vbatt_low_mv / 50; |
| 1751 | rc = qg_write(chip, chip->qg_base + QG_VBAT_LOW_THRESHOLD_REG, |
| 1752 | ®, 1); |
| 1753 | if (rc < 0) { |
| 1754 | pr_err("Failed to write vbat-low, rc=%d\n", rc); |
| 1755 | return rc; |
| 1756 | } |
| 1757 | |
| 1758 | /* vbat empty */ |
| 1759 | if (chip->dt.vbatt_empty_mv < 0) |
| 1760 | chip->dt.vbatt_empty_mv = 0; |
| 1761 | else if (chip->dt.vbatt_empty_mv > 12750) |
| 1762 | chip->dt.vbatt_empty_mv = 12750; |
| 1763 | |
| 1764 | reg = chip->dt.vbatt_empty_mv / 50; |
| 1765 | rc = qg_write(chip, chip->qg_base + QG_VBAT_EMPTY_THRESHOLD_REG, |
| 1766 | ®, 1); |
| 1767 | if (rc < 0) { |
| 1768 | pr_err("Failed to write vbat-empty, rc=%d\n", rc); |
| 1769 | return rc; |
| 1770 | } |
| 1771 | |
| 1772 | return 0; |
| 1773 | } |
| 1774 | |
| 1775 | static int qg_post_init(struct qpnp_qg *chip) |
| 1776 | { |
| 1777 | /* disable all IRQs if profile is not loaded */ |
| 1778 | if (!chip->profile_loaded) { |
| 1779 | vote(chip->vbatt_irq_disable_votable, |
| 1780 | PROFILE_IRQ_DISABLE, true, 0); |
| 1781 | vote(chip->fifo_irq_disable_votable, |
| 1782 | PROFILE_IRQ_DISABLE, true, 0); |
| 1783 | vote(chip->good_ocv_irq_disable_votable, |
| 1784 | PROFILE_IRQ_DISABLE, true, 0); |
| 1785 | } else { |
| 1786 | /* disable GOOD_OCV IRQ at init */ |
| 1787 | vote(chip->good_ocv_irq_disable_votable, |
| 1788 | QG_INIT_STATE_IRQ_DISABLE, true, 0); |
| 1789 | } |
| 1790 | |
| 1791 | return 0; |
| 1792 | } |
| 1793 | |
| 1794 | static int qg_get_irq_index_byname(const char *irq_name) |
| 1795 | { |
| 1796 | int i; |
| 1797 | |
| 1798 | for (i = 0; i < ARRAY_SIZE(qg_irqs); i++) { |
| 1799 | if (strcmp(qg_irqs[i].name, irq_name) == 0) |
| 1800 | return i; |
| 1801 | } |
| 1802 | |
| 1803 | return -ENOENT; |
| 1804 | } |
| 1805 | |
| 1806 | static int qg_request_interrupt(struct qpnp_qg *chip, |
| 1807 | struct device_node *node, const char *irq_name) |
| 1808 | { |
| 1809 | int rc, irq, irq_index; |
| 1810 | |
| 1811 | irq = of_irq_get_byname(node, irq_name); |
| 1812 | if (irq < 0) { |
| 1813 | pr_err("Failed to get irq %s byname\n", irq_name); |
| 1814 | return irq; |
| 1815 | } |
| 1816 | |
| 1817 | irq_index = qg_get_irq_index_byname(irq_name); |
| 1818 | if (irq_index < 0) { |
| 1819 | pr_err("%s is not a defined irq\n", irq_name); |
| 1820 | return irq_index; |
| 1821 | } |
| 1822 | |
| 1823 | if (!qg_irqs[irq_index].handler) |
| 1824 | return 0; |
| 1825 | |
| 1826 | rc = devm_request_threaded_irq(chip->dev, irq, NULL, |
| 1827 | qg_irqs[irq_index].handler, |
| 1828 | IRQF_ONESHOT, irq_name, chip); |
| 1829 | if (rc < 0) { |
| 1830 | pr_err("Failed to request irq %d\n", irq); |
| 1831 | return rc; |
| 1832 | } |
| 1833 | |
| 1834 | qg_irqs[irq_index].irq = irq; |
| 1835 | if (qg_irqs[irq_index].wake) |
| 1836 | enable_irq_wake(irq); |
| 1837 | |
| 1838 | qg_dbg(chip, QG_DEBUG_PON, "IRQ %s registered wakeable=%d\n", |
| 1839 | qg_irqs[irq_index].name, qg_irqs[irq_index].wake); |
| 1840 | |
| 1841 | return 0; |
| 1842 | } |
| 1843 | |
| 1844 | static int qg_request_irqs(struct qpnp_qg *chip) |
| 1845 | { |
| 1846 | struct device_node *node = chip->dev->of_node; |
| 1847 | struct device_node *child; |
| 1848 | const char *name; |
| 1849 | struct property *prop; |
| 1850 | int rc = 0; |
| 1851 | |
| 1852 | for_each_available_child_of_node(node, child) { |
| 1853 | of_property_for_each_string(child, "interrupt-names", |
| 1854 | prop, name) { |
| 1855 | rc = qg_request_interrupt(chip, child, name); |
| 1856 | if (rc < 0) |
| 1857 | return rc; |
| 1858 | } |
| 1859 | } |
| 1860 | |
| 1861 | |
| 1862 | return 0; |
| 1863 | } |
| 1864 | |
| 1865 | #define DEFAULT_VBATT_EMPTY_MV 3200 |
| 1866 | #define DEFAULT_VBATT_CUTOFF_MV 3400 |
| 1867 | #define DEFAULT_VBATT_LOW_MV 3500 |
| 1868 | #define DEFAULT_ITERM_MA 100 |
| 1869 | #define DEFAULT_S2_FIFO_LENGTH 5 |
| 1870 | #define DEFAULT_S2_VBAT_LOW_LENGTH 2 |
| 1871 | #define DEFAULT_S2_ACC_LENGTH 128 |
| 1872 | #define DEFAULT_S2_ACC_INTVL_MS 100 |
| 1873 | #define DEFAULT_DELTA_SOC 1 |
| 1874 | static int qg_parse_dt(struct qpnp_qg *chip) |
| 1875 | { |
| 1876 | int rc = 0; |
| 1877 | struct device_node *revid_node, *child, *node = chip->dev->of_node; |
| 1878 | u32 base, temp; |
| 1879 | u8 type; |
| 1880 | |
| 1881 | if (!node) { |
| 1882 | pr_err("Failed to find device-tree node\n"); |
| 1883 | return -ENXIO; |
| 1884 | } |
| 1885 | |
| 1886 | revid_node = of_parse_phandle(node, "qcom,pmic-revid", 0); |
| 1887 | if (!revid_node) { |
| 1888 | pr_err("Missing qcom,pmic-revid property - driver failed\n"); |
| 1889 | return -EINVAL; |
| 1890 | } |
| 1891 | |
| 1892 | chip->pmic_rev_id = get_revid_data(revid_node); |
| 1893 | of_node_put(revid_node); |
| 1894 | if (IS_ERR_OR_NULL(chip->pmic_rev_id)) { |
| 1895 | pr_err("Failed to get pmic_revid, rc=%ld\n", |
| 1896 | PTR_ERR(chip->pmic_rev_id)); |
| 1897 | /* |
| 1898 | * the revid peripheral must be registered, any failure |
| 1899 | * here only indicates that the rev-id module has not |
| 1900 | * probed yet. |
| 1901 | */ |
| 1902 | return -EPROBE_DEFER; |
| 1903 | } |
| 1904 | |
| 1905 | qg_dbg(chip, QG_DEBUG_PON, "PMIC subtype %d Digital major %d\n", |
| 1906 | chip->pmic_rev_id->pmic_subtype, chip->pmic_rev_id->rev4); |
| 1907 | |
| 1908 | for_each_available_child_of_node(node, child) { |
| 1909 | rc = of_property_read_u32(child, "reg", &base); |
| 1910 | if (rc < 0) { |
| 1911 | pr_err("Failed to read base address, rc=%d\n", rc); |
| 1912 | return rc; |
| 1913 | } |
| 1914 | |
| 1915 | rc = qg_read(chip, base + PERPH_TYPE_REG, &type, 1); |
| 1916 | if (rc < 0) { |
| 1917 | pr_err("Failed to read type, rc=%d\n", rc); |
| 1918 | return rc; |
| 1919 | } |
| 1920 | |
| 1921 | switch (type) { |
| 1922 | case QG_TYPE: |
| 1923 | chip->qg_base = base; |
| 1924 | break; |
| 1925 | default: |
| 1926 | break; |
| 1927 | } |
| 1928 | } |
| 1929 | |
| 1930 | if (!chip->qg_base) { |
| 1931 | pr_err("QG device node missing\n"); |
| 1932 | return -EINVAL; |
| 1933 | } |
| 1934 | |
| 1935 | /* S2 state params */ |
| 1936 | rc = of_property_read_u32(node, "qcom,s2-fifo-length", &temp); |
| 1937 | if (rc < 0) |
| 1938 | chip->dt.s2_fifo_length = DEFAULT_S2_FIFO_LENGTH; |
| 1939 | else |
| 1940 | chip->dt.s2_fifo_length = temp; |
| 1941 | |
| 1942 | rc = of_property_read_u32(node, "qcom,s2-vbat-low-fifo-length", &temp); |
| 1943 | if (rc < 0) |
| 1944 | chip->dt.s2_vbat_low_fifo_length = DEFAULT_S2_VBAT_LOW_LENGTH; |
| 1945 | else |
| 1946 | chip->dt.s2_vbat_low_fifo_length = temp; |
| 1947 | |
| 1948 | rc = of_property_read_u32(node, "qcom,s2-acc-length", &temp); |
| 1949 | if (rc < 0) |
| 1950 | chip->dt.s2_acc_length = DEFAULT_S2_ACC_LENGTH; |
| 1951 | else |
| 1952 | chip->dt.s2_acc_length = temp; |
| 1953 | |
| 1954 | rc = of_property_read_u32(node, "qcom,s2-acc-interval-ms", &temp); |
| 1955 | if (rc < 0) |
| 1956 | chip->dt.s2_acc_intvl_ms = DEFAULT_S2_ACC_INTVL_MS; |
| 1957 | else |
| 1958 | chip->dt.s2_acc_intvl_ms = temp; |
| 1959 | |
| 1960 | qg_dbg(chip, QG_DEBUG_PON, "DT: S2 FIFO length=%d low_vbat_length=%d acc_length=%d acc_interval=%d\n", |
| 1961 | chip->dt.s2_fifo_length, chip->dt.s2_vbat_low_fifo_length, |
| 1962 | chip->dt.s2_acc_length, chip->dt.s2_acc_intvl_ms); |
| 1963 | |
| 1964 | /* OCV params */ |
| 1965 | rc = of_property_read_u32(node, "qcom,ocv-timer-expiry-min", &temp); |
| 1966 | if (rc < 0) |
| 1967 | chip->dt.ocv_timer_expiry_min = -EINVAL; |
| 1968 | else |
| 1969 | chip->dt.ocv_timer_expiry_min = temp; |
| 1970 | |
| 1971 | rc = of_property_read_u32(node, "qcom,ocv-tol-threshold-uv", &temp); |
| 1972 | if (rc < 0) |
| 1973 | chip->dt.ocv_tol_threshold_uv = -EINVAL; |
| 1974 | else |
| 1975 | chip->dt.ocv_tol_threshold_uv = temp; |
| 1976 | |
| 1977 | qg_dbg(chip, QG_DEBUG_PON, "DT: OCV timer_expiry =%dmin ocv_tol_threshold=%duV\n", |
| 1978 | chip->dt.ocv_timer_expiry_min, chip->dt.ocv_tol_threshold_uv); |
| 1979 | |
| 1980 | /* S3 sleep configuration */ |
| 1981 | rc = of_property_read_u32(node, "qcom,s3-entry-fifo-length", &temp); |
| 1982 | if (rc < 0) |
| 1983 | chip->dt.s3_entry_fifo_length = -EINVAL; |
| 1984 | else |
| 1985 | chip->dt.s3_entry_fifo_length = temp; |
| 1986 | |
| 1987 | rc = of_property_read_u32(node, "qcom,s3-entry-ibat-ua", &temp); |
| 1988 | if (rc < 0) |
| 1989 | chip->dt.s3_entry_ibat_ua = -EINVAL; |
| 1990 | else |
| 1991 | chip->dt.s3_entry_ibat_ua = temp; |
| 1992 | |
| 1993 | rc = of_property_read_u32(node, "qcom,s3-entry-ibat-ua", &temp); |
| 1994 | if (rc < 0) |
| 1995 | chip->dt.s3_exit_ibat_ua = -EINVAL; |
| 1996 | else |
| 1997 | chip->dt.s3_exit_ibat_ua = temp; |
| 1998 | |
| 1999 | /* VBAT thresholds */ |
| 2000 | rc = of_property_read_u32(node, "qcom,vbatt-empty-mv", &temp); |
| 2001 | if (rc < 0) |
| 2002 | chip->dt.vbatt_empty_mv = DEFAULT_VBATT_EMPTY_MV; |
| 2003 | else |
| 2004 | chip->dt.vbatt_empty_mv = temp; |
| 2005 | |
| 2006 | rc = of_property_read_u32(node, "qcom,vbatt-low-mv", &temp); |
| 2007 | if (rc < 0) |
| 2008 | chip->dt.vbatt_low_mv = DEFAULT_VBATT_LOW_MV; |
| 2009 | else |
| 2010 | chip->dt.vbatt_low_mv = temp; |
| 2011 | |
| 2012 | rc = of_property_read_u32(node, "qcom,vbatt-cutoff-mv", &temp); |
| 2013 | if (rc < 0) |
| 2014 | chip->dt.vbatt_cutoff_mv = DEFAULT_VBATT_CUTOFF_MV; |
| 2015 | else |
| 2016 | chip->dt.vbatt_cutoff_mv = temp; |
| 2017 | |
| 2018 | /* IBAT thresholds */ |
| 2019 | rc = of_property_read_u32(node, "qcom,qg-iterm-ma", &temp); |
| 2020 | if (rc < 0) |
| 2021 | chip->dt.iterm_ma = DEFAULT_ITERM_MA; |
| 2022 | else |
| 2023 | chip->dt.iterm_ma = temp; |
| 2024 | |
| 2025 | rc = of_property_read_u32(node, "qcom,delta-soc", &temp); |
| 2026 | if (rc < 0) |
| 2027 | chip->dt.delta_soc = DEFAULT_DELTA_SOC; |
| 2028 | else |
| 2029 | chip->dt.delta_soc = temp; |
| 2030 | |
| 2031 | rc = of_property_read_u32(node, "qcom,rbat-conn-mohm", &temp); |
| 2032 | if (rc < 0) |
| 2033 | chip->dt.rbat_conn_mohm = 0; |
| 2034 | else |
| 2035 | chip->dt.rbat_conn_mohm = temp; |
| 2036 | |
| 2037 | qg_dbg(chip, QG_DEBUG_PON, "DT: vbatt_empty_mv=%dmV vbatt_low_mv=%dmV delta_soc=%d\n", |
| 2038 | chip->dt.vbatt_empty_mv, chip->dt.vbatt_low_mv, |
| 2039 | chip->dt.delta_soc); |
| 2040 | |
| 2041 | return 0; |
| 2042 | } |
| 2043 | |
| 2044 | static int process_suspend(struct qpnp_qg *chip) |
| 2045 | { |
| 2046 | int rc; |
| 2047 | u32 fifo_rt_length = 0, sleep_fifo_length = 0; |
| 2048 | |
| 2049 | /* ignore any suspend processing if we are charging */ |
| 2050 | if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING) { |
| 2051 | qg_dbg(chip, QG_DEBUG_PM, "Charging @ suspend - ignore processing\n"); |
| 2052 | return 0; |
| 2053 | } |
| 2054 | |
| 2055 | rc = get_fifo_length(chip, &fifo_rt_length, true); |
| 2056 | if (rc < 0) { |
| 2057 | pr_err("Failed to read FIFO RT count, rc=%d\n", rc); |
| 2058 | return rc; |
| 2059 | } |
| 2060 | |
| 2061 | rc = qg_read(chip, chip->qg_base + QG_S3_SLEEP_OCV_IBAT_CTL1_REG, |
| 2062 | (u8 *)&sleep_fifo_length, 1); |
| 2063 | if (rc < 0) { |
| 2064 | pr_err("Failed to read sleep FIFO count, rc=%d\n", rc); |
| 2065 | return rc; |
| 2066 | } |
| 2067 | sleep_fifo_length &= SLEEP_IBAT_QUALIFIED_LENGTH_MASK; |
| 2068 | /* |
| 2069 | * If the real-time FIFO count is greater than |
| 2070 | * the the #fifo to enter sleep, save the FIFO data |
| 2071 | * and reset the fifo count. |
| 2072 | */ |
| 2073 | if (fifo_rt_length >= (chip->dt.s2_fifo_length - sleep_fifo_length)) { |
| 2074 | rc = qg_master_hold(chip, true); |
| 2075 | if (rc < 0) { |
| 2076 | pr_err("Failed to hold master, rc=%d\n", rc); |
| 2077 | return rc; |
| 2078 | } |
| 2079 | |
| 2080 | rc = qg_process_rt_fifo(chip); |
| 2081 | if (rc < 0) { |
| 2082 | pr_err("Failed to process FIFO real-time, rc=%d\n", rc); |
| 2083 | qg_master_hold(chip, false); |
| 2084 | return rc; |
| 2085 | } |
| 2086 | |
| 2087 | rc = qg_master_hold(chip, false); |
| 2088 | if (rc < 0) { |
| 2089 | pr_err("Failed to release master, rc=%d\n", rc); |
| 2090 | return rc; |
| 2091 | } |
| 2092 | /* FIFOs restarted */ |
| 2093 | chip->last_fifo_update_time = ktime_get(); |
| 2094 | |
| 2095 | chip->suspend_data = true; |
| 2096 | } |
| 2097 | |
| 2098 | qg_dbg(chip, QG_DEBUG_PM, "FIFO rt_length=%d sleep_fifo_length=%d default_s2_count=%d suspend_data=%d\n", |
| 2099 | fifo_rt_length, sleep_fifo_length, |
| 2100 | chip->dt.s2_fifo_length, chip->suspend_data); |
| 2101 | |
| 2102 | return rc; |
| 2103 | } |
| 2104 | |
| 2105 | static int process_resume(struct qpnp_qg *chip) |
| 2106 | { |
| 2107 | int rc, batt_temp = 0; |
| 2108 | u8 status2 = 0, rt_status = 0; |
| 2109 | u32 ocv_uv = 0, soc = 0; |
| 2110 | |
| 2111 | rc = qg_read(chip, chip->qg_base + QG_STATUS2_REG, &status2, 1); |
| 2112 | if (rc < 0) { |
| 2113 | pr_err("Failed to read status2 register, rc=%d\n", rc); |
| 2114 | return rc; |
| 2115 | } |
| 2116 | |
| 2117 | if (status2 & GOOD_OCV_BIT) { |
| 2118 | rc = qg_read_ocv(chip, &ocv_uv, GOOD_OCV); |
| 2119 | if (rc < 0) { |
| 2120 | pr_err("Failed to read good_ocv, rc=%d\n", rc); |
| 2121 | return rc; |
| 2122 | } |
| 2123 | rc = qg_get_battery_temp(chip, &batt_temp); |
| 2124 | if (rc < 0) { |
| 2125 | pr_err("Failed to read BATT_TEMP, rc=%d\n", rc); |
| 2126 | return rc; |
| 2127 | } |
| 2128 | |
| 2129 | chip->kdata.param[QG_GOOD_OCV_UV].data = ocv_uv; |
| 2130 | chip->kdata.param[QG_GOOD_OCV_UV].valid = true; |
| 2131 | chip->suspend_data = false; |
| 2132 | rc = lookup_soc_ocv(&soc, ocv_uv, batt_temp, false); |
| 2133 | if (rc < 0) { |
| 2134 | pr_err("Failed to lookup OCV, rc=%d\n", rc); |
| 2135 | return rc; |
| 2136 | } |
| 2137 | chip->catch_up_soc = soc; |
| 2138 | /* update the SOC immediately */ |
| 2139 | qg_scale_soc(chip, true); |
| 2140 | |
| 2141 | qg_dbg(chip, QG_DEBUG_PM, "GOOD OCV @ resume good_ocv=%d uV soc=%d\n", |
| 2142 | ocv_uv, soc); |
| 2143 | } |
| 2144 | /* |
| 2145 | * If the wakeup was not because of FIFO_DONE |
| 2146 | * send the pending data collected during suspend. |
| 2147 | */ |
| 2148 | rc = qg_read(chip, chip->qg_base + QG_INT_LATCHED_STS_REG, |
| 2149 | &rt_status, 1); |
| 2150 | if (rc < 0) { |
| 2151 | pr_err("Failed to read latched status register, rc=%d\n", rc); |
| 2152 | return rc; |
| 2153 | } |
| 2154 | rt_status &= FIFO_UPDATE_DONE_INT_LAT_STS_BIT; |
| 2155 | |
| 2156 | if (!rt_status && chip->suspend_data) { |
| 2157 | vote(chip->awake_votable, SUSPEND_DATA_VOTER, true, 0); |
| 2158 | /* signal the read thread */ |
| 2159 | chip->data_ready = true; |
| 2160 | wake_up_interruptible(&chip->qg_wait_q); |
| 2161 | } |
| 2162 | |
| 2163 | qg_dbg(chip, QG_DEBUG_PM, "fifo_done rt_status=%d suspend_data=%d data_ready=%d\n", |
| 2164 | !!rt_status, chip->suspend_data, chip->data_ready); |
| 2165 | |
| 2166 | chip->suspend_data = false; |
| 2167 | |
| 2168 | return rc; |
| 2169 | } |
| 2170 | |
| 2171 | static int qpnp_qg_suspend_noirq(struct device *dev) |
| 2172 | { |
| 2173 | int rc; |
| 2174 | struct qpnp_qg *chip = dev_get_drvdata(dev); |
| 2175 | |
| 2176 | mutex_lock(&chip->data_lock); |
| 2177 | |
| 2178 | rc = process_suspend(chip); |
| 2179 | if (rc < 0) |
| 2180 | pr_err("Failed to process QG suspend, rc=%d\n", rc); |
| 2181 | |
| 2182 | mutex_unlock(&chip->data_lock); |
| 2183 | |
| 2184 | return 0; |
| 2185 | } |
| 2186 | |
| 2187 | static int qpnp_qg_resume_noirq(struct device *dev) |
| 2188 | { |
| 2189 | int rc; |
| 2190 | struct qpnp_qg *chip = dev_get_drvdata(dev); |
| 2191 | |
| 2192 | mutex_lock(&chip->data_lock); |
| 2193 | |
| 2194 | rc = process_resume(chip); |
| 2195 | if (rc < 0) |
| 2196 | pr_err("Failed to process QG resume, rc=%d\n", rc); |
| 2197 | |
| 2198 | mutex_unlock(&chip->data_lock); |
| 2199 | |
| 2200 | return 0; |
| 2201 | } |
| 2202 | |
| 2203 | static const struct dev_pm_ops qpnp_qg_pm_ops = { |
| 2204 | .suspend_noirq = qpnp_qg_suspend_noirq, |
| 2205 | .resume_noirq = qpnp_qg_resume_noirq, |
| 2206 | }; |
| 2207 | |
| 2208 | static int qpnp_qg_probe(struct platform_device *pdev) |
| 2209 | { |
| 2210 | int rc = 0, soc = 0; |
| 2211 | struct qpnp_qg *chip; |
| 2212 | |
| 2213 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
| 2214 | if (!chip) |
| 2215 | return -ENOMEM; |
| 2216 | |
| 2217 | chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 2218 | if (!chip->regmap) { |
| 2219 | pr_err("Parent regmap is unavailable\n"); |
| 2220 | return -ENXIO; |
| 2221 | } |
| 2222 | |
| 2223 | /* VADC for BID */ |
| 2224 | chip->vadc_dev = qpnp_get_vadc(&pdev->dev, "qg"); |
| 2225 | if (IS_ERR(chip->vadc_dev)) { |
| 2226 | rc = PTR_ERR(chip->vadc_dev); |
| 2227 | if (rc != -EPROBE_DEFER) |
| 2228 | pr_err("Failed to find VADC node, rc=%d\n", rc); |
| 2229 | |
| 2230 | return rc; |
| 2231 | } |
| 2232 | |
| 2233 | chip->dev = &pdev->dev; |
| 2234 | chip->debug_mask = &qg_debug_mask; |
| 2235 | platform_set_drvdata(pdev, chip); |
| 2236 | INIT_WORK(&chip->udata_work, process_udata_work); |
| 2237 | INIT_WORK(&chip->qg_status_change_work, qg_status_change_work); |
| 2238 | mutex_init(&chip->bus_lock); |
| 2239 | mutex_init(&chip->soc_lock); |
| 2240 | mutex_init(&chip->data_lock); |
| 2241 | init_waitqueue_head(&chip->qg_wait_q); |
| 2242 | |
| 2243 | rc = qg_parse_dt(chip); |
| 2244 | if (rc < 0) { |
| 2245 | pr_err("Failed to parse DT, rc=%d\n", rc); |
| 2246 | return rc; |
| 2247 | } |
| 2248 | |
| 2249 | rc = qg_hw_init(chip); |
| 2250 | if (rc < 0) { |
| 2251 | pr_err("Failed to hw_init, rc=%d\n", rc); |
| 2252 | return rc; |
| 2253 | } |
| 2254 | |
| 2255 | rc = qg_setup_battery(chip); |
| 2256 | if (rc < 0) { |
| 2257 | pr_err("Failed to setup battery, rc=%d\n", rc); |
| 2258 | return rc; |
| 2259 | } |
| 2260 | |
| 2261 | rc = qg_register_device(chip); |
| 2262 | if (rc < 0) { |
| 2263 | pr_err("Failed to register QG char device, rc=%d\n", rc); |
| 2264 | return rc; |
| 2265 | } |
| 2266 | |
| 2267 | rc = qg_sdam_init(chip->dev); |
| 2268 | if (rc < 0) { |
| 2269 | pr_err("Failed to initialize QG SDAM, rc=%d\n", rc); |
| 2270 | return rc; |
| 2271 | } |
| 2272 | |
| 2273 | rc = qg_soc_init(chip); |
| 2274 | if (rc < 0) { |
| 2275 | pr_err("Failed to initialize SOC scaling init rc=%d\n", rc); |
| 2276 | return rc; |
| 2277 | } |
| 2278 | |
| 2279 | rc = qg_determine_pon_soc(chip); |
| 2280 | if (rc < 0) { |
| 2281 | pr_err("Failed to determine initial state, rc=%d\n", rc); |
| 2282 | goto fail_device; |
| 2283 | } |
| 2284 | |
| 2285 | chip->awake_votable = create_votable("QG_WS", VOTE_SET_ANY, |
| 2286 | qg_awake_cb, chip); |
| 2287 | if (IS_ERR(chip->awake_votable)) { |
| 2288 | rc = PTR_ERR(chip->awake_votable); |
| 2289 | chip->awake_votable = NULL; |
| 2290 | goto fail_device; |
| 2291 | } |
| 2292 | |
| 2293 | chip->vbatt_irq_disable_votable = create_votable("QG_VBATT_IRQ_DISABLE", |
| 2294 | VOTE_SET_ANY, qg_vbatt_irq_disable_cb, chip); |
| 2295 | if (IS_ERR(chip->vbatt_irq_disable_votable)) { |
| 2296 | rc = PTR_ERR(chip->vbatt_irq_disable_votable); |
| 2297 | chip->vbatt_irq_disable_votable = NULL; |
| 2298 | goto fail_device; |
| 2299 | } |
| 2300 | |
| 2301 | chip->fifo_irq_disable_votable = create_votable("QG_FIFO_IRQ_DISABLE", |
| 2302 | VOTE_SET_ANY, qg_fifo_irq_disable_cb, chip); |
| 2303 | if (IS_ERR(chip->fifo_irq_disable_votable)) { |
| 2304 | rc = PTR_ERR(chip->fifo_irq_disable_votable); |
| 2305 | chip->fifo_irq_disable_votable = NULL; |
| 2306 | goto fail_device; |
| 2307 | } |
| 2308 | |
| 2309 | chip->good_ocv_irq_disable_votable = |
| 2310 | create_votable("QG_GOOD_IRQ_DISABLE", |
| 2311 | VOTE_SET_ANY, qg_good_ocv_irq_disable_cb, chip); |
| 2312 | if (IS_ERR(chip->good_ocv_irq_disable_votable)) { |
| 2313 | rc = PTR_ERR(chip->good_ocv_irq_disable_votable); |
| 2314 | chip->good_ocv_irq_disable_votable = NULL; |
| 2315 | goto fail_device; |
| 2316 | } |
| 2317 | |
| 2318 | rc = qg_init_psy(chip); |
| 2319 | if (rc < 0) { |
| 2320 | pr_err("Failed to initialize QG psy, rc=%d\n", rc); |
| 2321 | goto fail_votable; |
| 2322 | } |
| 2323 | |
| 2324 | rc = qg_request_irqs(chip); |
| 2325 | if (rc < 0) { |
| 2326 | pr_err("Failed to register QG interrupts, rc=%d\n", rc); |
| 2327 | goto fail_votable; |
| 2328 | } |
| 2329 | |
| 2330 | rc = qg_post_init(chip); |
| 2331 | if (rc < 0) { |
| 2332 | pr_err("Failed in qg_post_init rc=%d\n", rc); |
| 2333 | goto fail_votable; |
| 2334 | } |
| 2335 | |
| 2336 | qg_get_battery_capacity(chip, &soc); |
| 2337 | pr_info("QG initialized! battery_profile=%s SOC=%d\n", |
| 2338 | qg_get_battery_type(chip), soc); |
| 2339 | |
| 2340 | return rc; |
| 2341 | |
| 2342 | fail_votable: |
| 2343 | destroy_votable(chip->awake_votable); |
| 2344 | fail_device: |
| 2345 | device_destroy(chip->qg_class, chip->dev_no); |
| 2346 | cdev_del(&chip->qg_cdev); |
| 2347 | unregister_chrdev_region(chip->dev_no, 1); |
| 2348 | return rc; |
| 2349 | } |
| 2350 | |
| 2351 | static int qpnp_qg_remove(struct platform_device *pdev) |
| 2352 | { |
| 2353 | struct qpnp_qg *chip = platform_get_drvdata(pdev); |
| 2354 | |
| 2355 | qg_batterydata_exit(); |
| 2356 | qg_soc_exit(chip); |
| 2357 | |
| 2358 | cancel_work_sync(&chip->udata_work); |
| 2359 | cancel_work_sync(&chip->qg_status_change_work); |
| 2360 | device_destroy(chip->qg_class, chip->dev_no); |
| 2361 | cdev_del(&chip->qg_cdev); |
| 2362 | unregister_chrdev_region(chip->dev_no, 1); |
| 2363 | mutex_destroy(&chip->bus_lock); |
| 2364 | mutex_destroy(&chip->data_lock); |
| 2365 | mutex_destroy(&chip->soc_lock); |
| 2366 | if (chip->awake_votable) |
| 2367 | destroy_votable(chip->awake_votable); |
| 2368 | |
| 2369 | return 0; |
| 2370 | } |
| 2371 | |
| 2372 | static const struct of_device_id match_table[] = { |
| 2373 | { .compatible = "qcom,qpnp-qg", }, |
| 2374 | { }, |
| 2375 | }; |
| 2376 | |
| 2377 | static struct platform_driver qpnp_qg_driver = { |
| 2378 | .driver = { |
| 2379 | .name = "qcom,qpnp-qg", |
| 2380 | .owner = THIS_MODULE, |
| 2381 | .of_match_table = match_table, |
| 2382 | .pm = &qpnp_qg_pm_ops, |
| 2383 | }, |
| 2384 | .probe = qpnp_qg_probe, |
| 2385 | .remove = qpnp_qg_remove, |
| 2386 | }; |
| 2387 | module_platform_driver(qpnp_qg_driver); |
| 2388 | |
| 2389 | MODULE_DESCRIPTION("QPNP QG Driver"); |
| 2390 | MODULE_LICENSE("GPL v2"); |