Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
Reinette Chatre | eb7ae89 | 2008-03-11 16:17:17 -0700 | [diff] [blame] | 8 | * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved. |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
Ian Schram | 01ebd06 | 2007-10-25 17:15:22 +0800 | [diff] [blame] | 11 | * it under the terms of version 2 of the GNU General Public License as |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but |
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, |
| 22 | * USA |
| 23 | * |
| 24 | * The full GNU General Public License is included in this distribution |
| 25 | * in the file called LICENSE.GPL. |
| 26 | * |
| 27 | * Contact Information: |
| 28 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> |
| 29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 30 | * |
| 31 | * BSD LICENSE |
| 32 | * |
Reinette Chatre | eb7ae89 | 2008-03-11 16:17:17 -0700 | [diff] [blame] | 33 | * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved. |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 34 | * All rights reserved. |
| 35 | * |
| 36 | * Redistribution and use in source and binary forms, with or without |
| 37 | * modification, are permitted provided that the following conditions |
| 38 | * are met: |
| 39 | * |
| 40 | * * Redistributions of source code must retain the above copyright |
| 41 | * notice, this list of conditions and the following disclaimer. |
| 42 | * * Redistributions in binary form must reproduce the above copyright |
| 43 | * notice, this list of conditions and the following disclaimer in |
| 44 | * the documentation and/or other materials provided with the |
| 45 | * distribution. |
| 46 | * * Neither the name Intel Corporation nor the names of its |
| 47 | * contributors may be used to endorse or promote products derived |
| 48 | * from this software without specific prior written permission. |
| 49 | * |
| 50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 61 | * |
| 62 | *****************************************************************************/ |
Ben Cahill | fcd427b | 2007-11-29 11:10:00 +0800 | [diff] [blame] | 63 | /* |
| 64 | * Please use this file (iwl-3945-hw.h) only for hardware-related definitions. |
| 65 | * Please use iwl-3945-commands.h for uCode API definitions. |
| 66 | * Please use iwl-3945.h for driver implementation definitions. |
| 67 | */ |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 68 | |
| 69 | #ifndef __iwl_3945_hw__ |
| 70 | #define __iwl_3945_hw__ |
| 71 | |
Ben Cahill | 1fea8e8 | 2007-11-29 11:09:52 +0800 | [diff] [blame] | 72 | /* |
| 73 | * uCode queue management definitions ... |
| 74 | * Queue #4 is the command queue for 3945 and 4965. |
| 75 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 76 | #define IWL_CMD_QUEUE_NUM 4 |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 77 | |
| 78 | /* Tx rates */ |
| 79 | #define IWL_CCK_RATES 4 |
| 80 | #define IWL_OFDM_RATES 8 |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 81 | #define IWL_HT_RATES 0 |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 82 | #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES) |
| 83 | |
| 84 | /* Time constants */ |
| 85 | #define SHORT_SLOT_TIME 9 |
| 86 | #define LONG_SLOT_TIME 20 |
| 87 | |
| 88 | /* RSSI to dBm */ |
| 89 | #define IWL_RSSI_OFFSET 95 |
| 90 | |
| 91 | /* |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 92 | * EEPROM related constants, enums, and structures. |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 93 | */ |
| 94 | |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 95 | /* |
| 96 | * EEPROM access time values: |
| 97 | * |
| 98 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG, |
| 99 | * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit |
| 100 | * CSR_EEPROM_REG_BIT_CMD (0x2). |
| 101 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). |
| 102 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. |
| 103 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. |
| 104 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 105 | #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ |
| 106 | #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 107 | |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 108 | /* |
| 109 | * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags. |
| 110 | * |
| 111 | * IBSS and/or AP operation is allowed *only* on those channels with |
| 112 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because |
| 113 | * RADAR detection is not supported by the 3945 driver, but is a |
| 114 | * requirement for establishing a new network for legal operation on channels |
| 115 | * requiring RADAR detection or restricting ACTIVE scanning. |
| 116 | * |
| 117 | * NOTE: "WIDE" flag indicates that 20 MHz channel is supported; |
| 118 | * 3945 does not support FAT 40 MHz-wide channels. |
| 119 | * |
| 120 | * NOTE: Using a channel inappropriately will result in a uCode error! |
| 121 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 122 | enum { |
| 123 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 124 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 125 | /* Bit 2 Reserved */ |
| 126 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ |
| 127 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 128 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ |
Guy Cohen | fe7c404 | 2008-04-21 15:41:56 -0700 | [diff] [blame] | 129 | /* Bit 6 Reserved (was Narrow Channel) */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 130 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ |
| 131 | }; |
| 132 | |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 133 | /* SKU Capabilities */ |
| 134 | #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) |
| 135 | #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) |
| 136 | #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) |
| 137 | |
| 138 | /* *regulatory* channel data from eeprom, one for each channel */ |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 139 | struct iwl3945_eeprom_channel { |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 140 | u8 flags; /* flags copied from EEPROM */ |
| 141 | s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ |
| 142 | } __attribute__ ((packed)); |
| 143 | |
| 144 | /* |
| 145 | * Mapping of a Tx power level, at factory calibration temperature, |
| 146 | * to a radio/DSP gain table index. |
| 147 | * One for each of 5 "sample" power levels in each band. |
| 148 | * v_det is measured at the factory, using the 3945's built-in power amplifier |
| 149 | * (PA) output voltage detector. This same detector is used during Tx of |
| 150 | * long packets in normal operation to provide feedback as to proper output |
| 151 | * level. |
| 152 | * Data copied from EEPROM. |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 153 | * DO NOT ALTER THIS STRUCTURE!!! |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 154 | */ |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 155 | struct iwl3945_eeprom_txpower_sample { |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 156 | u8 gain_index; /* index into power (gain) setup table ... */ |
| 157 | s8 power; /* ... for this pwr level for this chnl group */ |
| 158 | u16 v_det; /* PA output voltage */ |
| 159 | } __attribute__ ((packed)); |
| 160 | |
| 161 | /* |
| 162 | * Mappings of Tx power levels -> nominal radio/DSP gain table indexes. |
| 163 | * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). |
| 164 | * Tx power setup code interpolates between the 5 "sample" power levels |
| 165 | * to determine the nominal setup for a requested power level. |
| 166 | * Data copied from EEPROM. |
| 167 | * DO NOT ALTER THIS STRUCTURE!!! |
| 168 | */ |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 169 | struct iwl3945_eeprom_txpower_group { |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 170 | struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 171 | s32 a, b, c, d, e; /* coefficients for voltage->power |
| 172 | * formula (signed) */ |
| 173 | s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 174 | * frequency (signed) */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 175 | s8 saturation_power; /* highest power possible by h/w in this |
| 176 | * band */ |
| 177 | u8 group_channel; /* "representative" channel # in this band */ |
| 178 | s16 temperature; /* h/w temperature at factory calib this band |
| 179 | * (signed) */ |
| 180 | } __attribute__ ((packed)); |
| 181 | |
| 182 | /* |
| 183 | * Temperature-based Tx-power compensation data, not band-specific. |
| 184 | * These coefficients are use to modify a/b/c/d/e coeffs based on |
| 185 | * difference between current temperature and factory calib temperature. |
| 186 | * Data copied from EEPROM. |
| 187 | */ |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 188 | struct iwl3945_eeprom_temperature_corr { |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 189 | u32 Ta; |
| 190 | u32 Tb; |
| 191 | u32 Tc; |
| 192 | u32 Td; |
| 193 | u32 Te; |
| 194 | } __attribute__ ((packed)); |
| 195 | |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 196 | /* |
| 197 | * EEPROM map |
| 198 | */ |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 199 | struct iwl3945_eeprom { |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 200 | u8 reserved0[16]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 201 | u16 device_id; /* abs.ofs: 16 */ |
| 202 | u8 reserved1[2]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 203 | u16 pmc; /* abs.ofs: 20 */ |
| 204 | u8 reserved2[20]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 205 | u8 mac_address[6]; /* abs.ofs: 42 */ |
| 206 | u8 reserved3[58]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 207 | u16 board_revision; /* abs.ofs: 106 */ |
| 208 | u8 reserved4[11]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 209 | u8 board_pba_number[9]; /* abs.ofs: 119 */ |
| 210 | u8 reserved5[8]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 211 | u16 version; /* abs.ofs: 136 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 212 | u8 sku_cap; /* abs.ofs: 138 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 213 | u8 leds_mode; /* abs.ofs: 139 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 214 | u16 oem_mode; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 215 | u16 wowlan_mode; /* abs.ofs: 142 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 216 | u16 leds_time_interval; /* abs.ofs: 144 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 217 | u8 leds_off_time; /* abs.ofs: 146 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 218 | u8 leds_on_time; /* abs.ofs: 147 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 219 | u8 almgor_m_version; /* abs.ofs: 148 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 220 | u8 antenna_switch_type; /* abs.ofs: 149 */ |
| 221 | u8 reserved6[42]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 222 | u8 sku_id[4]; /* abs.ofs: 192 */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 223 | |
| 224 | /* |
| 225 | * Per-channel regulatory data. |
| 226 | * |
| 227 | * Each channel that *might* be supported by 3945 or 4965 has a fixed location |
| 228 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory |
| 229 | * txpower (MSB). |
| 230 | * |
| 231 | * Entries immediately below are for 20 MHz channel width. FAT (40 MHz) |
| 232 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. |
| 233 | * |
| 234 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 |
| 235 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 236 | u16 band_1_count; /* abs.ofs: 196 */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 237 | struct iwl3945_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ |
| 238 | |
| 239 | /* |
| 240 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, |
| 241 | * 5.0 GHz channels 7, 8, 11, 12, 16 |
| 242 | * (4915-5080MHz) (none of these is ever supported) |
| 243 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 244 | u16 band_2_count; /* abs.ofs: 226 */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 245 | struct iwl3945_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ |
| 246 | |
| 247 | /* |
| 248 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 |
| 249 | * (5170-5320MHz) |
| 250 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 251 | u16 band_3_count; /* abs.ofs: 254 */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 252 | struct iwl3945_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ |
| 253 | |
| 254 | /* |
| 255 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 |
| 256 | * (5500-5700MHz) |
| 257 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 258 | u16 band_4_count; /* abs.ofs: 280 */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 259 | struct iwl3945_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ |
| 260 | |
| 261 | /* |
| 262 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 |
| 263 | * (5725-5825MHz) |
| 264 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 265 | u16 band_5_count; /* abs.ofs: 304 */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 266 | struct iwl3945_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 267 | |
| 268 | u8 reserved9[194]; |
| 269 | |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 270 | /* |
| 271 | * 3945 Txpower calibration data. |
| 272 | */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 273 | #define IWL_NUM_TX_CALIB_GROUPS 5 |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 274 | struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS]; |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 275 | /* abs.ofs: 512 */ |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 276 | struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 277 | u8 reserved16[172]; /* fill out to full 1024 byte block */ |
| 278 | } __attribute__ ((packed)); |
| 279 | |
| 280 | #define IWL_EEPROM_IMAGE_SIZE 1024 |
| 281 | |
Ben Cahill | 796083c | 2007-11-29 11:09:45 +0800 | [diff] [blame] | 282 | /* End of EEPROM */ |
| 283 | |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 284 | |
| 285 | #include "iwl-3945-commands.h" |
| 286 | |
| 287 | #define PCI_LINK_CTRL 0x0F0 |
| 288 | #define PCI_POWER_SOURCE 0x0C8 |
| 289 | #define PCI_REG_WUM8 0x0E8 |
| 290 | #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) |
| 291 | |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 292 | /*=== FH (data Flow Handler) ===*/ |
| 293 | #define FH_BASE (0x800) |
| 294 | |
| 295 | #define FH_CBCC_TABLE (FH_BASE+0x140) |
| 296 | #define FH_TFDB_TABLE (FH_BASE+0x180) |
| 297 | #define FH_RCSR_TABLE (FH_BASE+0x400) |
| 298 | #define FH_RSSR_TABLE (FH_BASE+0x4c0) |
| 299 | #define FH_TCSR_TABLE (FH_BASE+0x500) |
| 300 | #define FH_TSSR_TABLE (FH_BASE+0x680) |
| 301 | |
| 302 | /* TFDB (Transmit Frame Buffer Descriptor) */ |
| 303 | #define FH_TFDB(_channel, buf) \ |
| 304 | (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28) |
| 305 | #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \ |
| 306 | (FH_TFDB_TABLE + 0x50 * _channel) |
| 307 | /* CBCC _channel is [0,2] */ |
| 308 | #define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8) |
| 309 | #define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00) |
| 310 | #define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04) |
| 311 | |
| 312 | /* RCSR _channel is [0,2] */ |
| 313 | #define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40) |
| 314 | #define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00) |
| 315 | #define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04) |
| 316 | #define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20) |
| 317 | #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24) |
| 318 | |
| 319 | #define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0)) |
| 320 | |
| 321 | /* RSSR */ |
| 322 | #define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000) |
| 323 | #define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004) |
| 324 | /* TCSR */ |
| 325 | #define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20) |
| 326 | #define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00) |
| 327 | #define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04) |
| 328 | #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08) |
| 329 | /* TSSR */ |
| 330 | #define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000) |
| 331 | #define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008) |
| 332 | #define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010) |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 333 | |
| 334 | |
| 335 | /* DBM */ |
| 336 | |
| 337 | #define ALM_FH_SRVC_CHNL (6) |
| 338 | |
| 339 | #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) |
| 340 | #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) |
| 341 | |
| 342 | #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) |
| 343 | |
| 344 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) |
| 345 | |
| 346 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) |
| 347 | |
| 348 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) |
| 349 | |
| 350 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) |
| 351 | |
| 352 | #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) |
| 353 | |
| 354 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) |
| 355 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) |
| 356 | |
| 357 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) |
| 358 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) |
| 359 | |
| 360 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) |
| 361 | |
| 362 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) |
| 363 | |
| 364 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) |
| 365 | #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) |
| 366 | |
| 367 | #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) |
| 368 | |
| 369 | #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) |
| 370 | |
| 371 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) |
| 372 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) |
| 373 | |
| 374 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) |
| 375 | |
| 376 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) |
| 377 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) |
| 378 | |
| 379 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) |
| 380 | #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) |
| 381 | |
| 382 | #define ALM_TB_MAX_BYTES_COUNT (0xFFF0) |
| 383 | |
| 384 | #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \ |
| 385 | ((1LU << _channel) << 24) |
| 386 | #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \ |
| 387 | ((1LU << _channel) << 16) |
| 388 | |
| 389 | #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \ |
| 390 | (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \ |
| 391 | ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel)) |
| 392 | #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ |
| 393 | #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ |
| 394 | |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 395 | #define TFD_QUEUE_MIN 0 |
| 396 | #define TFD_QUEUE_MAX 6 |
| 397 | #define TFD_QUEUE_SIZE_MAX (256) |
| 398 | |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 399 | #define IWL_NUM_SCAN_RATES (2) |
| 400 | |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 401 | #define IWL_DEFAULT_TX_RETRY 15 |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 402 | |
| 403 | /*********************************************/ |
| 404 | |
| 405 | #define RFD_SIZE 4 |
| 406 | #define NUM_TFD_CHUNKS 4 |
| 407 | |
| 408 | #define RX_QUEUE_SIZE 256 |
| 409 | #define RX_QUEUE_MASK 255 |
| 410 | #define RX_QUEUE_SIZE_LOG 8 |
| 411 | |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 412 | #define U32_PAD(n) ((4-(n))&0x3) |
| 413 | |
Reinette Chatre | 8a1b024 | 2008-01-14 17:46:25 -0800 | [diff] [blame] | 414 | #define TFD_CTL_COUNT_SET(n) (n << 24) |
| 415 | #define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7) |
| 416 | #define TFD_CTL_PAD_SET(n) (n << 28) |
| 417 | #define TFD_CTL_PAD_GET(ctl) (ctl >> 28) |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 418 | |
| 419 | #define TFD_TX_CMD_SLOTS 256 |
| 420 | #define TFD_CMD_SLOTS 32 |
| 421 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 422 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl3945_cmd) - \ |
| 423 | sizeof(struct iwl3945_cmd_meta)) |
Christoph Hellwig | 5d08cd1 | 2007-10-25 17:15:50 +0800 | [diff] [blame] | 424 | |
| 425 | /* |
| 426 | * RX related structures and functions |
| 427 | */ |
| 428 | #define RX_FREE_BUFFERS 64 |
| 429 | #define RX_LOW_WATERMARK 8 |
| 430 | |
Ben Cahill | fcd427b | 2007-11-29 11:10:00 +0800 | [diff] [blame] | 431 | /* Sizes and addresses for instruction and data memory (SRAM) in |
| 432 | * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ |
| 433 | #define RTC_INST_LOWER_BOUND (0x000000) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 434 | #define ALM_RTC_INST_UPPER_BOUND (0x014000) |
Ben Cahill | fcd427b | 2007-11-29 11:10:00 +0800 | [diff] [blame] | 435 | |
| 436 | #define RTC_DATA_LOWER_BOUND (0x800000) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 437 | #define ALM_RTC_DATA_UPPER_BOUND (0x808000) |
| 438 | |
| 439 | #define ALM_RTC_INST_SIZE (ALM_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) |
| 440 | #define ALM_RTC_DATA_SIZE (ALM_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND) |
| 441 | |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 442 | #define IWL_MAX_INST_SIZE ALM_RTC_INST_SIZE |
| 443 | #define IWL_MAX_DATA_SIZE ALM_RTC_DATA_SIZE |
Ben Cahill | fcd427b | 2007-11-29 11:10:00 +0800 | [diff] [blame] | 444 | |
| 445 | /* Size of uCode instruction memory in bootstrap state machine */ |
| 446 | #define IWL_MAX_BSM_SIZE ALM_RTC_INST_SIZE |
| 447 | |
Ron Rindjunsky | dfe7d45 | 2008-04-15 16:01:45 -0700 | [diff] [blame] | 448 | #define IWL39_MAX_NUM_QUEUES 8 |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 449 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 450 | static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 451 | { |
| 452 | return (addr >= RTC_DATA_LOWER_BOUND) && |
| 453 | (addr < ALM_RTC_DATA_UPPER_BOUND); |
| 454 | } |
| 455 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 456 | /* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE |
| 457 | * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */ |
| 458 | struct iwl3945_shared { |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 459 | __le32 tx_base_ptr[8]; |
| 460 | __le32 rx_read_ptr[3]; |
| 461 | } __attribute__ ((packed)); |
| 462 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 463 | struct iwl3945_tfd_frame_data { |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 464 | __le32 addr; |
| 465 | __le32 len; |
| 466 | } __attribute__ ((packed)); |
| 467 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 468 | struct iwl3945_tfd_frame { |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 469 | __le32 control_flags; |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 470 | struct iwl3945_tfd_frame_data pa[4]; |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 471 | u8 reserved[28]; |
| 472 | } __attribute__ ((packed)); |
| 473 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 474 | static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 475 | { |
| 476 | return le16_to_cpu(rate_n_flags) & 0xFF; |
| 477 | } |
| 478 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 479 | static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 480 | { |
| 481 | return le16_to_cpu(rate_n_flags); |
| 482 | } |
| 483 | |
Christoph Hellwig | bb8c093 | 2008-01-27 16:41:47 -0800 | [diff] [blame] | 484 | static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags) |
Zhu Yi | b481de9 | 2007-09-25 17:54:57 -0700 | [diff] [blame] | 485 | { |
| 486 | return cpu_to_le16((u16)rate|flags); |
| 487 | } |
| 488 | #endif |