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Zhu Yib481de92007-09-25 17:54:57 -07001/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
Reinette Chatreeb7ae892008-03-11 16:17:17 -07008 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
Zhu Yib481de92007-09-25 17:54:57 -07009 *
10 * This program is free software; you can redistribute it and/or modify
Ian Schram01ebd062007-10-25 17:15:22 +080011 * it under the terms of version 2 of the GNU General Public License as
Zhu Yib481de92007-09-25 17:54:57 -070012 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
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28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
Reinette Chatreeb7ae892008-03-11 16:17:17 -070033 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
Zhu Yib481de92007-09-25 17:54:57 -070034 * All rights reserved.
35 *
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37 * modification, are permitted provided that the following conditions
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39 *
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44 * the documentation and/or other materials provided with the
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50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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62 *****************************************************************************/
Ben Cahillfcd427b2007-11-29 11:10:00 +080063/*
64 * Please use this file (iwl-4965-hw.h) only for hardware-related definitions.
Tomas Winkler5a36ba02008-04-24 11:55:37 -070065 * Use iwl-commands.h for uCode API definitions.
Tomas Winkler3e0d4cb2008-04-24 11:55:38 -070066 * Use iwl-dev.h for driver implementation definitions.
Ben Cahillfcd427b2007-11-29 11:10:00 +080067 */
Zhu Yib481de92007-09-25 17:54:57 -070068
69#ifndef __iwl_4965_hw_h__
70#define __iwl_4965_hw_h__
71
Emmanuel Grumbach4b52c392008-04-23 17:15:07 -070072#include "iwl-fh.h"
73
Tomas Winklera96a27f2008-10-23 23:48:56 -070074/* EEPROM */
Tomas Winkler073d3f52008-04-21 15:41:52 -070075#define IWL4965_EEPROM_IMG_SIZE 1024
76
Ben Cahill1fea8e82007-11-29 11:09:52 +080077/*
78 * uCode queue management definitions ...
79 * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4.
80 * The first queue used for block-ack aggregation is #7 (4965 only).
81 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
82 */
Christoph Hellwig5d08cd12007-10-25 17:15:50 +080083#define IWL_CMD_QUEUE_NUM 4
84#define IWL_CMD_FIFO_NUM 4
Ron Rindjunsky7f3e4bb2008-06-12 09:46:55 +080085#define IWL49_FIRST_AMPDU_QUEUE 7
Christoph Hellwig5d08cd12007-10-25 17:15:50 +080086
87/* Tx rates */
88#define IWL_CCK_RATES 4
89#define IWL_OFDM_RATES 8
Christoph Hellwig5d08cd12007-10-25 17:15:50 +080090#define IWL_HT_RATES 16
Christoph Hellwig5d08cd12007-10-25 17:15:50 +080091#define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
92
93/* Time constants */
94#define SHORT_SLOT_TIME 9
95#define LONG_SLOT_TIME 20
96
97/* RSSI to dBm */
98#define IWL_RSSI_OFFSET 44
99
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800100
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800101
Tomas Winkler8f061892008-05-29 16:34:56 +0800102/* PCI registers */
Tomas Winklere7b63582008-09-03 11:26:49 +0800103#define PCI_CFG_RETRY_TIMEOUT 0x041
104#define PCI_CFG_POWER_SOURCE 0x0C8
105#define PCI_REG_WUM8 0x0E8
106#define PCI_CFG_LINK_CTRL 0x0F0
Tomas Winkler8f061892008-05-29 16:34:56 +0800107
108/* PCI register values */
Tomas Winklere7b63582008-09-03 11:26:49 +0800109#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
110#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
111#define PCI_CFG_CMD_REG_INT_DIS_MSK 0x04
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800112#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
113
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800114
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800115#define IWL_NUM_SCAN_RATES (2)
116
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800117#define IWL_DEFAULT_TX_RETRY 15
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800118
119#define RX_QUEUE_SIZE 256
120#define RX_QUEUE_MASK 255
121#define RX_QUEUE_SIZE_LOG 8
122
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800123#define TFD_TX_CMD_SLOTS 256
124#define TFD_CMD_SLOTS 32
125
Christoph Hellwig5d08cd12007-10-25 17:15:50 +0800126/*
127 * RX related structures and functions
128 */
129#define RX_FREE_BUFFERS 64
130#define RX_LOW_WATERMARK 8
131
Ben Cahillfcd427b2007-11-29 11:10:00 +0800132/* Size of one Rx buffer in host DRAM */
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +0200133#define IWL_RX_BUF_SIZE_4K (4 * 1024)
134#define IWL_RX_BUF_SIZE_8K (8 * 1024)
Ben Cahillfcd427b2007-11-29 11:10:00 +0800135
136/* Sizes and addresses for instruction and data memory (SRAM) in
137 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
138#define RTC_INST_LOWER_BOUND (0x000000)
Tomas Winkler12a81f62008-04-03 16:05:20 -0700139#define IWL49_RTC_INST_UPPER_BOUND (0x018000)
Ben Cahillfcd427b2007-11-29 11:10:00 +0800140
141#define RTC_DATA_LOWER_BOUND (0x800000)
Tomas Winkler12a81f62008-04-03 16:05:20 -0700142#define IWL49_RTC_DATA_UPPER_BOUND (0x80A000)
Ben Cahillfcd427b2007-11-29 11:10:00 +0800143
Ron Rindjunsky099b40b2008-04-21 15:41:53 -0700144#define IWL49_RTC_INST_SIZE (IWL49_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
145#define IWL49_RTC_DATA_SIZE (IWL49_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
Zhu Yib481de92007-09-25 17:54:57 -0700146
Tomas Winkler12a81f62008-04-03 16:05:20 -0700147#define IWL_MAX_INST_SIZE IWL49_RTC_INST_SIZE
148#define IWL_MAX_DATA_SIZE IWL49_RTC_DATA_SIZE
Zhu Yib481de92007-09-25 17:54:57 -0700149
Ben Cahillfcd427b2007-11-29 11:10:00 +0800150/* Size of uCode instruction memory in bootstrap state machine */
151#define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
152
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800153static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr)
Zhu Yib481de92007-09-25 17:54:57 -0700154{
155 return (addr >= RTC_DATA_LOWER_BOUND) &&
Tomas Winkler12a81f62008-04-03 16:05:20 -0700156 (addr < IWL49_RTC_DATA_UPPER_BOUND);
Zhu Yib481de92007-09-25 17:54:57 -0700157}
158
Ben Cahill5991b412007-11-29 11:10:01 +0800159/********************* START TEMPERATURE *************************************/
160
Ben Cahill0c434c52007-11-29 11:10:02 +0800161/**
Ben Cahill5991b412007-11-29 11:10:01 +0800162 * 4965 temperature calculation.
163 *
164 * The driver must calculate the device temperature before calculating
165 * a txpower setting (amplifier gain is temperature dependent). The
166 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
167 * values used for the life of the driver, and one of which (R4) is the
168 * real-time temperature indicator.
169 *
170 * uCode provides all 4 values to the driver via the "initialize alive"
171 * notification (see struct iwl4965_init_alive_resp). After the runtime uCode
172 * image loads, uCode updates the R4 value via statistics notifications
173 * (see STATISTICS_NOTIFICATION), which occur after each received beacon
174 * when associated, or can be requested via REPLY_STATISTICS_CMD.
175 *
176 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
177 * must sign-extend to 32 bits before applying formula below.
178 *
179 * Formula:
180 *
181 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
182 *
183 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
184 * an additional correction, which should be centered around 0 degrees
185 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
186 * centering the 97/100 correction around 0 degrees K.
187 *
188 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
189 * temperature with factory-measured temperatures when calculating txpower
190 * settings.
191 */
192#define TEMPERATURE_CALIB_KELVIN_OFFSET 8
193#define TEMPERATURE_CALIB_A_VAL 259
194
195/* Limit range of calculated temperature to be between these Kelvin values */
196#define IWL_TX_POWER_TEMPERATURE_MIN (263)
197#define IWL_TX_POWER_TEMPERATURE_MAX (410)
198
199#define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
200 (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
201 ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
202
203/********************* END TEMPERATURE ***************************************/
204
Zhu Yib481de92007-09-25 17:54:57 -0700205/********************* START TXPOWER *****************************************/
Zhu Yib481de92007-09-25 17:54:57 -0700206
Ben Cahill0c434c52007-11-29 11:10:02 +0800207/**
208 * 4965 txpower calculations rely on information from three sources:
209 *
210 * 1) EEPROM
211 * 2) "initialize" alive notification
212 * 3) statistics notifications
213 *
214 * EEPROM data consists of:
215 *
216 * 1) Regulatory information (max txpower and channel usage flags) is provided
217 * separately for each channel that can possibly supported by 4965.
218 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz
219 * (legacy) channels.
220 *
221 * See struct iwl4965_eeprom_channel for format, and struct iwl4965_eeprom
222 * for locations in EEPROM.
223 *
224 * 2) Factory txpower calibration information is provided separately for
225 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
226 * but 5 GHz has several sub-bands.
227 *
228 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
229 *
230 * See struct iwl4965_eeprom_calib_info (and the tree of structures
231 * contained within it) for format, and struct iwl4965_eeprom for
232 * locations in EEPROM.
233 *
234 * "Initialization alive" notification (see struct iwl4965_init_alive_resp)
235 * consists of:
236 *
237 * 1) Temperature calculation parameters.
238 *
239 * 2) Power supply voltage measurement.
240 *
241 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
242 *
243 * Statistics notifications deliver:
244 *
245 * 1) Current values for temperature param R4.
246 */
247
248/**
249 * To calculate a txpower setting for a given desired target txpower, channel,
250 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
251 * support MIMO and transmit diversity), driver must do the following:
252 *
253 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
254 * Do not exceed regulatory limit; reduce target txpower if necessary.
255 *
256 * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
257 * 2 transmitters will be used simultaneously; driver must reduce the
258 * regulatory limit by 3 dB (half-power) for each transmitter, so the
259 * combined total output of the 2 transmitters is within regulatory limits.
260 *
261 *
262 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
263 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
264 * reduce target txpower if necessary.
265 *
266 * Backoff values below are in 1/2 dB units (equivalent to steps in
267 * txpower gain tables):
268 *
269 * OFDM 6 - 36 MBit: 10 steps (5 dB)
270 * OFDM 48 MBit: 15 steps (7.5 dB)
271 * OFDM 54 MBit: 17 steps (8.5 dB)
272 * OFDM 60 MBit: 20 steps (10 dB)
273 * CCK all rates: 10 steps (5 dB)
274 *
275 * Backoff values apply to saturation txpower on a per-transmitter basis;
276 * when using MIMO (2 transmitters), each transmitter uses the same
277 * saturation level provided in EEPROM, and the same backoff values;
278 * no reduction (such as with regulatory txpower limits) is required.
279 *
280 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
281 * widths and 40 Mhz (.11n fat) channel widths; there is no separate
282 * factory measurement for fat channels.
283 *
284 * The result of this step is the final target txpower. The rest of
285 * the steps figure out the proper settings for the device to achieve
286 * that target txpower.
287 *
288 *
Tomas Winklera96a27f2008-10-23 23:48:56 -0700289 * 3) Determine (EEPROM) calibration sub band for the target channel, by
290 * comparing against first and last channels in each sub band
Ben Cahill0c434c52007-11-29 11:10:02 +0800291 * (see struct iwl4965_eeprom_calib_subband_info).
292 *
293 *
294 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
Tomas Winklera96a27f2008-10-23 23:48:56 -0700295 * referencing the 2 factory-measured (sample) channels within the sub band.
Ben Cahill0c434c52007-11-29 11:10:02 +0800296 *
297 * Interpolation is based on difference between target channel's frequency
298 * and the sample channels' frequencies. Since channel numbers are based
299 * on frequency (5 MHz between each channel number), this is equivalent
300 * to interpolating based on channel number differences.
301 *
302 * Note that the sample channels may or may not be the channels at the
Tomas Winklera96a27f2008-10-23 23:48:56 -0700303 * edges of the sub band. The target channel may be "outside" of the
Ben Cahill0c434c52007-11-29 11:10:02 +0800304 * span of the sampled channels.
305 *
306 * Driver may choose the pair (for 2 Tx chains) of measurements (see
307 * struct iwl4965_eeprom_calib_ch_info) for which the actual measured
308 * txpower comes closest to the desired txpower. Usually, though,
309 * the middle set of measurements is closest to the regulatory limits,
310 * and is therefore a good choice for all txpower calculations (this
311 * assumes that high accuracy is needed for maximizing legal txpower,
312 * while lower txpower configurations do not need as much accuracy).
313 *
314 * Driver should interpolate both members of the chosen measurement pair,
315 * i.e. for both Tx chains (radio transmitters), unless the driver knows
316 * that only one of the chains will be used (e.g. only one tx antenna
317 * connected, but this should be unusual). The rate scaling algorithm
318 * switches antennas to find best performance, so both Tx chains will
319 * be used (although only one at a time) even for non-MIMO transmissions.
320 *
321 * Driver should interpolate factory values for temperature, gain table
322 * index, and actual power. The power amplifier detector values are
323 * not used by the driver.
324 *
325 * Sanity check: If the target channel happens to be one of the sample
326 * channels, the results should agree with the sample channel's
327 * measurements!
328 *
329 *
330 * 5) Find difference between desired txpower and (interpolated)
331 * factory-measured txpower. Using (interpolated) factory gain table index
332 * (shown elsewhere) as a starting point, adjust this index lower to
333 * increase txpower, or higher to decrease txpower, until the target
334 * txpower is reached. Each step in the gain table is 1/2 dB.
335 *
336 * For example, if factory measured txpower is 16 dBm, and target txpower
337 * is 13 dBm, add 6 steps to the factory gain index to reduce txpower
338 * by 3 dB.
339 *
340 *
341 * 6) Find difference between current device temperature and (interpolated)
342 * factory-measured temperature for sub-band. Factory values are in
343 * degrees Celsius. To calculate current temperature, see comments for
344 * "4965 temperature calculation".
345 *
346 * If current temperature is higher than factory temperature, driver must
Tomas Winklera96a27f2008-10-23 23:48:56 -0700347 * increase gain (lower gain table index), and vice verse.
Ben Cahill0c434c52007-11-29 11:10:02 +0800348 *
349 * Temperature affects gain differently for different channels:
350 *
351 * 2.4 GHz all channels: 3.5 degrees per half-dB step
352 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
353 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
354 *
355 * NOTE: Temperature can increase rapidly when transmitting, especially
356 * with heavy traffic at high txpowers. Driver should update
357 * temperature calculations often under these conditions to
358 * maintain strong txpower in the face of rising temperature.
359 *
360 *
361 * 7) Find difference between current power supply voltage indicator
362 * (from "initialize alive") and factory-measured power supply voltage
363 * indicator (EEPROM).
364 *
365 * If the current voltage is higher (indicator is lower) than factory
366 * voltage, gain should be reduced (gain table index increased) by:
367 *
368 * (eeprom - current) / 7
369 *
370 * If the current voltage is lower (indicator is higher) than factory
371 * voltage, gain should be increased (gain table index decreased) by:
372 *
373 * 2 * (current - eeprom) / 7
374 *
375 * If number of index steps in either direction turns out to be > 2,
376 * something is wrong ... just use 0.
377 *
378 * NOTE: Voltage compensation is independent of band/channel.
379 *
380 * NOTE: "Initialize" uCode measures current voltage, which is assumed
381 * to be constant after this initial measurement. Voltage
382 * compensation for txpower (number of steps in gain table)
383 * may be calculated once and used until the next uCode bootload.
384 *
385 *
386 * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31),
387 * adjust txpower for each transmitter chain, so txpower is balanced
388 * between the two chains. There are 5 pairs of tx_atten[group][chain]
389 * values in "initialize alive", one pair for each of 5 channel ranges:
390 *
391 * Group 0: 5 GHz channel 34-43
392 * Group 1: 5 GHz channel 44-70
393 * Group 2: 5 GHz channel 71-124
394 * Group 3: 5 GHz channel 125-200
395 * Group 4: 2.4 GHz all channels
396 *
397 * Add the tx_atten[group][chain] value to the index for the target chain.
398 * The values are signed, but are in pairs of 0 and a non-negative number,
399 * so as to reduce gain (if necessary) of the "hotter" channel. This
400 * avoids any need to double-check for regulatory compliance after
401 * this step.
402 *
403 *
404 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
405 * value to the index:
406 *
407 * Hardware rev B: 9 steps (4.5 dB)
408 * Hardware rev C: 5 steps (2.5 dB)
409 *
410 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
411 * bits [3:2], 1 = B, 2 = C.
412 *
413 * NOTE: This compensation is in addition to any saturation backoff that
414 * might have been applied in an earlier step.
415 *
416 *
417 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
418 *
419 * Limit the adjusted index to stay within the table!
420 *
421 *
422 * 11) Read gain table entries for DSP and radio gain, place into appropriate
423 * location(s) in command (struct iwl4965_txpowertable_cmd).
424 */
425
426/* Limit range of txpower output target to be between these values */
427#define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
428#define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
429
430/**
431 * When MIMO is used (2 transmitters operating simultaneously), driver should
432 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
433 * for the device. That is, use half power for each transmitter, so total
434 * txpower is within regulatory limits.
435 *
436 * The value "6" represents number of steps in gain table to reduce power 3 dB.
437 * Each step is 1/2 dB.
438 */
439#define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
440
441/**
442 * CCK gain compensation.
443 *
444 * When calculating txpowers for CCK, after making sure that the target power
445 * is within regulatory and saturation limits, driver must additionally
446 * back off gain by adding these values to the gain table index.
447 *
448 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
449 * bits [3:2], 1 = B, 2 = C.
450 */
451#define IWL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
452#define IWL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
453
454/*
455 * 4965 power supply voltage compensation for txpower
456 */
457#define TX_POWER_IWL_VOLTAGE_CODES_PER_03V (7)
458
459/**
460 * Gain tables.
461 *
462 * The following tables contain pair of values for setting txpower, i.e.
463 * gain settings for the output of the device's digital signal processor (DSP),
464 * and for the analog gain structure of the transmitter.
465 *
466 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
467 * are *relative* steps, not indications of absolute output power. Output
468 * power varies with temperature, voltage, and channel frequency, and also
469 * requires consideration of average power (to satisfy regulatory constraints),
470 * and peak power (to avoid distortion of the output signal).
471 *
472 * Each entry contains two values:
473 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
474 * linear value that multiplies the output of the digital signal processor,
475 * before being sent to the analog radio.
476 * 2) Radio gain. This sets the analog gain of the radio Tx path.
477 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
478 *
479 * EEPROM contains factory calibration data for txpower. This maps actual
480 * measured txpower levels to gain settings in the "well known" tables
481 * below ("well-known" means here that both factory calibration *and* the
482 * driver work with the same table).
483 *
484 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
485 * has an extension (into negative indexes), in case the driver needs to
486 * boost power setting for high device temperatures (higher than would be
487 * present during factory calibration). A 5 Ghz EEPROM index of "40"
488 * corresponds to the 49th entry in the table used by the driver.
489 */
490#define MIN_TX_GAIN_INDEX (0) /* highest gain, lowest idx, 2.4 */
491#define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
492
493/**
494 * 2.4 GHz gain table
495 *
496 * Index Dsp gain Radio gain
497 * 0 110 0x3f (highest gain)
498 * 1 104 0x3f
499 * 2 98 0x3f
500 * 3 110 0x3e
501 * 4 104 0x3e
502 * 5 98 0x3e
503 * 6 110 0x3d
504 * 7 104 0x3d
505 * 8 98 0x3d
506 * 9 110 0x3c
507 * 10 104 0x3c
508 * 11 98 0x3c
509 * 12 110 0x3b
510 * 13 104 0x3b
511 * 14 98 0x3b
512 * 15 110 0x3a
513 * 16 104 0x3a
514 * 17 98 0x3a
515 * 18 110 0x39
516 * 19 104 0x39
517 * 20 98 0x39
518 * 21 110 0x38
519 * 22 104 0x38
520 * 23 98 0x38
521 * 24 110 0x37
522 * 25 104 0x37
523 * 26 98 0x37
524 * 27 110 0x36
525 * 28 104 0x36
526 * 29 98 0x36
527 * 30 110 0x35
528 * 31 104 0x35
529 * 32 98 0x35
530 * 33 110 0x34
531 * 34 104 0x34
532 * 35 98 0x34
533 * 36 110 0x33
534 * 37 104 0x33
535 * 38 98 0x33
536 * 39 110 0x32
537 * 40 104 0x32
538 * 41 98 0x32
539 * 42 110 0x31
540 * 43 104 0x31
541 * 44 98 0x31
542 * 45 110 0x30
543 * 46 104 0x30
544 * 47 98 0x30
545 * 48 110 0x6
546 * 49 104 0x6
547 * 50 98 0x6
548 * 51 110 0x5
549 * 52 104 0x5
550 * 53 98 0x5
551 * 54 110 0x4
552 * 55 104 0x4
553 * 56 98 0x4
554 * 57 110 0x3
555 * 58 104 0x3
556 * 59 98 0x3
557 * 60 110 0x2
558 * 61 104 0x2
559 * 62 98 0x2
560 * 63 110 0x1
561 * 64 104 0x1
562 * 65 98 0x1
563 * 66 110 0x0
564 * 67 104 0x0
565 * 68 98 0x0
566 * 69 97 0
567 * 70 96 0
568 * 71 95 0
569 * 72 94 0
570 * 73 93 0
571 * 74 92 0
572 * 75 91 0
573 * 76 90 0
574 * 77 89 0
575 * 78 88 0
576 * 79 87 0
577 * 80 86 0
578 * 81 85 0
579 * 82 84 0
580 * 83 83 0
581 * 84 82 0
582 * 85 81 0
583 * 86 80 0
584 * 87 79 0
585 * 88 78 0
586 * 89 77 0
587 * 90 76 0
588 * 91 75 0
589 * 92 74 0
590 * 93 73 0
591 * 94 72 0
592 * 95 71 0
593 * 96 70 0
594 * 97 69 0
595 * 98 68 0
596 */
597
598/**
599 * 5 GHz gain table
600 *
601 * Index Dsp gain Radio gain
602 * -9 123 0x3F (highest gain)
603 * -8 117 0x3F
604 * -7 110 0x3F
605 * -6 104 0x3F
606 * -5 98 0x3F
607 * -4 110 0x3E
608 * -3 104 0x3E
609 * -2 98 0x3E
610 * -1 110 0x3D
611 * 0 104 0x3D
612 * 1 98 0x3D
613 * 2 110 0x3C
614 * 3 104 0x3C
615 * 4 98 0x3C
616 * 5 110 0x3B
617 * 6 104 0x3B
618 * 7 98 0x3B
619 * 8 110 0x3A
620 * 9 104 0x3A
621 * 10 98 0x3A
622 * 11 110 0x39
623 * 12 104 0x39
624 * 13 98 0x39
625 * 14 110 0x38
626 * 15 104 0x38
627 * 16 98 0x38
628 * 17 110 0x37
629 * 18 104 0x37
630 * 19 98 0x37
631 * 20 110 0x36
632 * 21 104 0x36
633 * 22 98 0x36
634 * 23 110 0x35
635 * 24 104 0x35
636 * 25 98 0x35
637 * 26 110 0x34
638 * 27 104 0x34
639 * 28 98 0x34
640 * 29 110 0x33
641 * 30 104 0x33
642 * 31 98 0x33
643 * 32 110 0x32
644 * 33 104 0x32
645 * 34 98 0x32
646 * 35 110 0x31
647 * 36 104 0x31
648 * 37 98 0x31
649 * 38 110 0x30
650 * 39 104 0x30
651 * 40 98 0x30
652 * 41 110 0x25
653 * 42 104 0x25
654 * 43 98 0x25
655 * 44 110 0x24
656 * 45 104 0x24
657 * 46 98 0x24
658 * 47 110 0x23
659 * 48 104 0x23
660 * 49 98 0x23
661 * 50 110 0x22
662 * 51 104 0x18
663 * 52 98 0x18
664 * 53 110 0x17
665 * 54 104 0x17
666 * 55 98 0x17
667 * 56 110 0x16
668 * 57 104 0x16
669 * 58 98 0x16
670 * 59 110 0x15
671 * 60 104 0x15
672 * 61 98 0x15
673 * 62 110 0x14
674 * 63 104 0x14
675 * 64 98 0x14
676 * 65 110 0x13
677 * 66 104 0x13
678 * 67 98 0x13
679 * 68 110 0x12
680 * 69 104 0x08
681 * 70 98 0x08
682 * 71 110 0x07
683 * 72 104 0x07
684 * 73 98 0x07
685 * 74 110 0x06
686 * 75 104 0x06
687 * 76 98 0x06
688 * 77 110 0x05
689 * 78 104 0x05
690 * 79 98 0x05
691 * 80 110 0x04
692 * 81 104 0x04
693 * 82 98 0x04
694 * 83 110 0x03
695 * 84 104 0x03
696 * 85 98 0x03
697 * 86 110 0x02
698 * 87 104 0x02
699 * 88 98 0x02
700 * 89 110 0x01
701 * 90 104 0x01
702 * 91 98 0x01
703 * 92 110 0x00
704 * 93 104 0x00
705 * 94 98 0x00
706 * 95 93 0x00
707 * 96 88 0x00
708 * 97 83 0x00
709 * 98 78 0x00
710 */
711
712
713/**
714 * Sanity checks and default values for EEPROM regulatory levels.
715 * If EEPROM values fall outside MIN/MAX range, use default values.
716 *
717 * Regulatory limits refer to the maximum average txpower allowed by
718 * regulatory agencies in the geographies in which the device is meant
719 * to be operated. These limits are SKU-specific (i.e. geography-specific),
720 * and channel-specific; each channel has an individual regulatory limit
721 * listed in the EEPROM.
722 *
723 * Units are in half-dBm (i.e. "34" means 17 dBm).
724 */
725#define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34)
726#define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34)
727#define IWL_TX_POWER_REGULATORY_MIN (0)
728#define IWL_TX_POWER_REGULATORY_MAX (34)
729
730/**
731 * Sanity checks and default values for EEPROM saturation levels.
732 * If EEPROM values fall outside MIN/MAX range, use default values.
733 *
734 * Saturation is the highest level that the output power amplifier can produce
735 * without significant clipping distortion. This is a "peak" power level.
736 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
737 * require differing amounts of backoff, relative to their average power output,
738 * in order to avoid clipping distortion.
739 *
740 * Driver must make sure that it is violating neither the saturation limit,
741 * nor the regulatory limit, when calculating Tx power settings for various
742 * rates.
743 *
744 * Units are in half-dBm (i.e. "38" means 19 dBm).
745 */
746#define IWL_TX_POWER_DEFAULT_SATURATION_24 (38)
747#define IWL_TX_POWER_DEFAULT_SATURATION_52 (38)
748#define IWL_TX_POWER_SATURATION_MIN (20)
749#define IWL_TX_POWER_SATURATION_MAX (50)
750
751/**
752 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
753 * and thermal Txpower calibration.
754 *
755 * When calculating txpower, driver must compensate for current device
756 * temperature; higher temperature requires higher gain. Driver must calculate
757 * current temperature (see "4965 temperature calculation"), then compare vs.
758 * factory calibration temperature in EEPROM; if current temperature is higher
759 * than factory temperature, driver must *increase* gain by proportions shown
760 * in table below. If current temperature is lower than factory, driver must
761 * *decrease* gain.
762 *
763 * Different frequency ranges require different compensation, as shown below.
764 */
765/* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
766#define CALIB_IWL_TX_ATTEN_GR1_FCH 34
767#define CALIB_IWL_TX_ATTEN_GR1_LCH 43
768
769/* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
770#define CALIB_IWL_TX_ATTEN_GR2_FCH 44
771#define CALIB_IWL_TX_ATTEN_GR2_LCH 70
772
773/* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
774#define CALIB_IWL_TX_ATTEN_GR3_FCH 71
775#define CALIB_IWL_TX_ATTEN_GR3_LCH 124
776
777/* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
778#define CALIB_IWL_TX_ATTEN_GR4_FCH 125
779#define CALIB_IWL_TX_ATTEN_GR4_LCH 200
780
781/* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
782#define CALIB_IWL_TX_ATTEN_GR5_FCH 1
783#define CALIB_IWL_TX_ATTEN_GR5_LCH 20
784
Zhu Yib481de92007-09-25 17:54:57 -0700785enum {
786 CALIB_CH_GROUP_1 = 0,
787 CALIB_CH_GROUP_2 = 1,
788 CALIB_CH_GROUP_3 = 2,
789 CALIB_CH_GROUP_4 = 3,
790 CALIB_CH_GROUP_5 = 4,
791 CALIB_CH_GROUP_MAX
792};
793
Zhu Yib481de92007-09-25 17:54:57 -0700794/********************* END TXPOWER *****************************************/
795
Ben Cahill5d5456f2007-11-29 11:10:06 +0800796
797/**
798 * Tx/Rx Queues
799 *
800 * Most communication between driver and 4965 is via queues of data buffers.
801 * For example, all commands that the driver issues to device's embedded
802 * controller (uCode) are via the command queue (one of the Tx queues). All
803 * uCode command responses/replies/notifications, including Rx frames, are
804 * conveyed from uCode to driver via the Rx queue.
805 *
806 * Most support for these queues, including handshake support, resides in
807 * structures in host DRAM, shared between the driver and the device. When
808 * allocating this memory, the driver must make sure that data written by
809 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
810 * cache memory), so DRAM and cache are consistent, and the device can
811 * immediately see changes made by the driver.
812 *
813 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
814 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
815 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
816 */
Emmanuel Grumbach038669e2008-04-23 17:15:04 -0700817#define IWL49_NUM_FIFOS 7
818#define IWL49_CMD_FIFO_NUM 4
819#define IWL49_NUM_QUEUES 16
Tomas Winkler9f17b312008-07-11 11:53:35 +0800820#define IWL49_NUM_AMPDU_QUEUES 8
Ben Cahill5d5456f2007-11-29 11:10:06 +0800821
Zhu Yib481de92007-09-25 17:54:57 -0700822
Ben Cahill5d5456f2007-11-29 11:10:06 +0800823/**
Tomas Winkler127901a2008-10-23 23:48:55 -0700824 * struct iwl4965_schedq_bc_tbl
Ben Cahill5d5456f2007-11-29 11:10:06 +0800825 *
826 * Byte Count table
827 *
828 * Each Tx queue uses a byte-count table containing 320 entries:
829 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
830 * duplicate the first 64 entries (to avoid wrap-around within a Tx window;
831 * max Tx window is 64 TFDs).
832 *
833 * When driver sets up a new TFD, it must also enter the total byte count
834 * of the frame to be transmitted into the corresponding entry in the byte
835 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver
836 * must duplicate the byte count entry in corresponding index 256-319.
837 *
Tomas Winkler127901a2008-10-23 23:48:55 -0700838 * padding puts each byte count table on a 1024-byte boundary;
Ben Cahill5d5456f2007-11-29 11:10:06 +0800839 * 4965 assumes tables are separated by 1024 bytes.
840 */
Tomas Winkler4ddbb7d2008-11-07 09:58:40 -0800841struct iwl4965_scd_bc_tbl {
Tomas Winkler127901a2008-10-23 23:48:55 -0700842 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
843 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
Zhu Yib481de92007-09-25 17:54:57 -0700844} __attribute__ ((packed));
845
Tomas Winkler4ddbb7d2008-11-07 09:58:40 -0800846#endif /* !__iwl_4965_hw_h__ */