Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _CAM_CCI_DEV_H_ |
| 14 | #define _CAM_CCI_DEV_H_ |
| 15 | |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/of_gpio.h> |
| 21 | #include <linux/of_platform.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/irqreturn.h> |
| 24 | #include <linux/ion.h> |
| 25 | #include <linux/iommu.h> |
| 26 | #include <linux/timer.h> |
| 27 | #include <linux/kernel.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <media/cam_sensor.h> |
| 30 | #include <media/v4l2-event.h> |
| 31 | #include <media/v4l2-ioctl.h> |
| 32 | #include <media/v4l2-subdev.h> |
| 33 | #include <cam_sensor_cmn_header.h> |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 34 | #include <cam_io_util.h> |
| 35 | #include <cam_sensor_util.h> |
| 36 | #include <cam_subdev.h> |
| 37 | #include <cam_cpas_api.h> |
| 38 | #include "cam_cci_hwreg.h" |
Alok Pandey | 01b1b35 | 2017-06-25 20:38:54 +0530 | [diff] [blame] | 39 | #include "cam_soc_util.h" |
Jigarkumar Zala | cbb5a38 | 2017-07-17 19:06:42 -0700 | [diff] [blame] | 40 | #include "cam_debug_util.h" |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 41 | |
| 42 | #define V4L2_IDENT_CCI 50005 |
| 43 | #define CCI_I2C_QUEUE_0_SIZE 128 |
| 44 | #define CCI_I2C_QUEUE_1_SIZE 32 |
| 45 | #define CYCLES_PER_MICRO_SEC_DEFAULT 4915 |
| 46 | #define CCI_MAX_DELAY 1000000 |
| 47 | |
| 48 | #define CCI_TIMEOUT msecs_to_jiffies(500) |
| 49 | |
| 50 | #define NUM_MASTERS 2 |
| 51 | #define NUM_QUEUES 2 |
| 52 | |
| 53 | #define TRUE 1 |
| 54 | #define FALSE 0 |
| 55 | |
| 56 | #define CCI_PINCTRL_STATE_DEFAULT "cci_default" |
| 57 | #define CCI_PINCTRL_STATE_SLEEP "cci_suspend" |
| 58 | |
| 59 | #define CCI_NUM_CLK_MAX 16 |
| 60 | #define CCI_NUM_CLK_CASES 5 |
| 61 | #define CCI_CLK_SRC_NAME "cci_src_clk" |
| 62 | #define MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_10 10 |
| 63 | #define MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11 11 |
| 64 | #define BURST_MIN_FREE_SIZE 8 |
| 65 | #define MAX_LRME_V4l2_EVENTS 30 |
| 66 | |
| 67 | /* Max bytes that can be read per CCI read transaction */ |
| 68 | #define CCI_READ_MAX 12 |
| 69 | #define CCI_I2C_READ_MAX_RETRIES 3 |
| 70 | #define CCI_I2C_MAX_READ 8192 |
| 71 | #define CCI_I2C_MAX_WRITE 8192 |
| 72 | |
| 73 | #define CAMX_CCI_DEV_NAME "cam-cci-driver" |
| 74 | |
| 75 | /* Max bytes that can be read per CCI read transaction */ |
| 76 | #define CCI_READ_MAX 12 |
| 77 | #define CCI_I2C_READ_MAX_RETRIES 3 |
| 78 | #define CCI_I2C_MAX_READ 8192 |
| 79 | #define CCI_I2C_MAX_WRITE 8192 |
| 80 | |
| 81 | #define PRIORITY_QUEUE (QUEUE_0) |
| 82 | #define SYNC_QUEUE (QUEUE_1) |
| 83 | |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 84 | enum cci_i2c_sync { |
| 85 | MSM_SYNC_DISABLE, |
| 86 | MSM_SYNC_ENABLE, |
| 87 | }; |
| 88 | |
| 89 | enum cam_cci_cmd_type { |
| 90 | MSM_CCI_INIT, |
| 91 | MSM_CCI_RELEASE, |
| 92 | MSM_CCI_SET_SID, |
| 93 | MSM_CCI_SET_FREQ, |
| 94 | MSM_CCI_SET_SYNC_CID, |
| 95 | MSM_CCI_I2C_READ, |
| 96 | MSM_CCI_I2C_WRITE, |
| 97 | MSM_CCI_I2C_WRITE_SEQ, |
Karthik Anantha Ram | 0fb02a3 | 2017-08-23 11:52:50 -0700 | [diff] [blame^] | 98 | MSM_CCI_I2C_WRITE_BURST, |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 99 | MSM_CCI_I2C_WRITE_ASYNC, |
| 100 | MSM_CCI_GPIO_WRITE, |
| 101 | MSM_CCI_I2C_WRITE_SYNC, |
| 102 | MSM_CCI_I2C_WRITE_SYNC_BLOCK, |
| 103 | }; |
| 104 | |
| 105 | enum cci_i2c_queue_t { |
| 106 | QUEUE_0, |
| 107 | QUEUE_1, |
| 108 | QUEUE_INVALID, |
| 109 | }; |
| 110 | |
| 111 | struct cam_cci_wait_sync_cfg { |
| 112 | uint16_t cid; |
| 113 | int16_t csid; |
| 114 | uint16_t line; |
| 115 | uint16_t delay; |
| 116 | }; |
| 117 | |
| 118 | struct cam_cci_gpio_cfg { |
| 119 | uint16_t gpio_queue; |
| 120 | uint16_t i2c_queue; |
| 121 | }; |
| 122 | |
| 123 | struct cam_cci_read_cfg { |
| 124 | uint32_t addr; |
| 125 | uint16_t addr_type; |
| 126 | uint8_t *data; |
| 127 | uint16_t num_byte; |
| 128 | }; |
| 129 | |
| 130 | struct cam_cci_i2c_queue_info { |
| 131 | uint32_t max_queue_size; |
| 132 | uint32_t report_id; |
| 133 | uint32_t irq_en; |
| 134 | uint32_t capture_rep_data; |
| 135 | }; |
| 136 | |
| 137 | struct cam_cci_master_info { |
| 138 | uint32_t status; |
| 139 | atomic_t q_free[NUM_QUEUES]; |
| 140 | uint8_t q_lock[NUM_QUEUES]; |
| 141 | uint8_t reset_pending; |
| 142 | struct mutex mutex; |
| 143 | struct completion reset_complete; |
| 144 | struct mutex mutex_q[NUM_QUEUES]; |
| 145 | struct completion report_q[NUM_QUEUES]; |
| 146 | atomic_t done_pending[NUM_QUEUES]; |
| 147 | }; |
| 148 | |
| 149 | struct cam_cci_clk_params_t { |
| 150 | uint16_t hw_thigh; |
| 151 | uint16_t hw_tlow; |
| 152 | uint16_t hw_tsu_sto; |
| 153 | uint16_t hw_tsu_sta; |
| 154 | uint16_t hw_thd_dat; |
| 155 | uint16_t hw_thd_sta; |
| 156 | uint16_t hw_tbuf; |
| 157 | uint8_t hw_scl_stretch_en; |
| 158 | uint8_t hw_trdhld; |
| 159 | uint8_t hw_tsp; |
| 160 | uint32_t cci_clk_src; |
| 161 | }; |
| 162 | |
| 163 | enum cam_cci_state_t { |
| 164 | CCI_STATE_ENABLED, |
| 165 | CCI_STATE_DISABLED, |
| 166 | }; |
| 167 | |
| 168 | /** |
| 169 | * struct cci_device |
| 170 | * @pdev: Platform device |
| 171 | * @subdev: V4L2 sub device |
| 172 | * @base: Base address of CCI device |
| 173 | * @hw_version: Hardware version |
| 174 | * @ref_count: Reference Count |
| 175 | * @cci_state: CCI state machine |
| 176 | * @num_clk: Number of CCI clock |
| 177 | * @cci_clk: CCI clock structure |
| 178 | * @cci_clk_info: CCI clock information |
| 179 | * @cam_cci_i2c_queue_info: CCI queue information |
| 180 | * @i2c_freq_mode: I2C frequency of operations |
| 181 | * @cci_clk_params: CCI hw clk params |
| 182 | * @cci_gpio_tbl: CCI GPIO table |
| 183 | * @cci_gpio_tbl_size: GPIO table size |
| 184 | * @cci_pinctrl: Pinctrl structure |
| 185 | * @cci_pinctrl_status: CCI pinctrl status |
| 186 | * @cci_clk_src: CCI clk src rate |
| 187 | * @cci_vreg: CCI regulator structure |
| 188 | * @cci_reg_ptr: CCI individual regulator structure |
| 189 | * @regulator_count: Regulator count |
| 190 | * @support_seq_write: |
| 191 | * Set this flag when sequential write is enabled |
| 192 | * @write_wq: Work queue structure |
| 193 | * @valid_sync: Is it a valid sync with CSID |
| 194 | * @v4l2_dev_str: V4L2 device structure |
| 195 | * @cci_wait_sync_cfg: CCI sync config |
| 196 | * @cycles_per_us: Cycles per micro sec |
| 197 | * @payload_size: CCI packet payload size |
| 198 | */ |
| 199 | struct cci_device { |
| 200 | struct v4l2_subdev subdev; |
Alok Pandey | 01b1b35 | 2017-06-25 20:38:54 +0530 | [diff] [blame] | 201 | struct cam_hw_soc_info soc_info; |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 202 | uint32_t hw_version; |
| 203 | uint8_t ref_count; |
| 204 | enum cam_cci_state_t cci_state; |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 205 | struct cam_cci_i2c_queue_info |
| 206 | cci_i2c_queue_info[NUM_MASTERS][NUM_QUEUES]; |
| 207 | struct cam_cci_master_info cci_master_info[NUM_MASTERS]; |
| 208 | enum i2c_freq_mode i2c_freq_mode[NUM_MASTERS]; |
| 209 | struct cam_cci_clk_params_t cci_clk_params[I2C_MAX_MODES]; |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 210 | struct msm_pinctrl_info cci_pinctrl; |
| 211 | uint8_t cci_pinctrl_status; |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 212 | uint8_t support_seq_write; |
| 213 | struct workqueue_struct *write_wq[MASTER_MAX]; |
| 214 | struct cam_cci_wait_sync_cfg cci_wait_sync_cfg; |
| 215 | uint8_t valid_sync; |
| 216 | struct cam_subdev v4l2_dev_str; |
| 217 | uint32_t cycles_per_us; |
Alok Pandey | 01b1b35 | 2017-06-25 20:38:54 +0530 | [diff] [blame] | 218 | int32_t clk_level_index; |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 219 | uint8_t payload_size; |
Viswanadha Raju Thotakura | 9a3795e | 2017-02-25 13:27:08 -0800 | [diff] [blame] | 220 | char device_name[20]; |
| 221 | uint32_t cpas_handle; |
| 222 | }; |
| 223 | |
| 224 | enum cam_cci_i2c_cmd_type { |
| 225 | CCI_I2C_SET_PARAM_CMD = 1, |
| 226 | CCI_I2C_WAIT_CMD, |
| 227 | CCI_I2C_WAIT_SYNC_CMD, |
| 228 | CCI_I2C_WAIT_GPIO_EVENT_CMD, |
| 229 | CCI_I2C_TRIG_I2C_EVENT_CMD, |
| 230 | CCI_I2C_LOCK_CMD, |
| 231 | CCI_I2C_UNLOCK_CMD, |
| 232 | CCI_I2C_REPORT_CMD, |
| 233 | CCI_I2C_WRITE_CMD, |
| 234 | CCI_I2C_READ_CMD, |
| 235 | CCI_I2C_WRITE_DISABLE_P_CMD, |
| 236 | CCI_I2C_READ_DISABLE_P_CMD, |
| 237 | CCI_I2C_WRITE_CMD2, |
| 238 | CCI_I2C_WRITE_CMD3, |
| 239 | CCI_I2C_REPEAT_CMD, |
| 240 | CCI_I2C_INVALID_CMD, |
| 241 | }; |
| 242 | |
| 243 | enum cam_cci_gpio_cmd_type { |
| 244 | CCI_GPIO_SET_PARAM_CMD = 1, |
| 245 | CCI_GPIO_WAIT_CMD, |
| 246 | CCI_GPIO_WAIT_SYNC_CMD, |
| 247 | CCI_GPIO_WAIT_GPIO_IN_EVENT_CMD, |
| 248 | CCI_GPIO_WAIT_I2C_Q_TRIG_EVENT_CMD, |
| 249 | CCI_GPIO_OUT_CMD, |
| 250 | CCI_GPIO_TRIG_EVENT_CMD, |
| 251 | CCI_GPIO_REPORT_CMD, |
| 252 | CCI_GPIO_REPEAT_CMD, |
| 253 | CCI_GPIO_CONTINUE_CMD, |
| 254 | CCI_GPIO_INVALID_CMD, |
| 255 | }; |
| 256 | |
| 257 | struct cam_sensor_cci_client { |
| 258 | struct v4l2_subdev *cci_subdev; |
| 259 | uint32_t freq; |
| 260 | enum i2c_freq_mode i2c_freq_mode; |
| 261 | enum cci_i2c_master_t cci_i2c_master; |
| 262 | uint16_t sid; |
| 263 | uint16_t cid; |
| 264 | uint32_t timeout; |
| 265 | uint16_t retries; |
| 266 | uint16_t id_map; |
| 267 | }; |
| 268 | |
| 269 | struct cam_cci_ctrl { |
| 270 | int32_t status; |
| 271 | struct cam_sensor_cci_client *cci_info; |
| 272 | enum cam_cci_cmd_type cmd; |
| 273 | union { |
| 274 | struct cam_sensor_i2c_reg_setting cci_i2c_write_cfg; |
| 275 | struct cam_cci_read_cfg cci_i2c_read_cfg; |
| 276 | struct cam_cci_wait_sync_cfg cci_wait_sync_cfg; |
| 277 | struct cam_cci_gpio_cfg gpio_cfg; |
| 278 | } cfg; |
| 279 | }; |
| 280 | |
| 281 | struct cci_write_async { |
| 282 | struct cci_device *cci_dev; |
| 283 | struct cam_cci_ctrl c_ctrl; |
| 284 | enum cci_i2c_queue_t queue; |
| 285 | struct work_struct work; |
| 286 | enum cci_i2c_sync sync_en; |
| 287 | }; |
| 288 | |
| 289 | irqreturn_t cam_cci_irq(int irq_num, void *data); |
| 290 | |
| 291 | #ifdef CONFIG_SPECTRA_CAMERA |
| 292 | struct v4l2_subdev *cam_cci_get_subdev(void); |
| 293 | #else |
| 294 | static inline struct v4l2_subdev *cam_cci_get_subdev(void) |
| 295 | { |
| 296 | return NULL; |
| 297 | } |
| 298 | #endif |
| 299 | |
| 300 | #define VIDIOC_MSM_CCI_CFG \ |
| 301 | _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl *) |
| 302 | |
| 303 | #endif /* _CAM_CCI_DEV_H_ */ |