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gerrit-public.fairphone.software / kernel / msm-4.9 / 0fbd88ca20a68a633b565e1f5ba18ca64afb0c78 / . / arch / blackfin / include / asm / dpmc.h
blob: 528f4768578185e52584de63ac0eb28ceaca4215 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1/*
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
3 *
Mike Frysingera8e8e492009-10-15 06:47:28 +0000[diff] [blame]4 * Copyright (C) 2004-2009 Analog Device Inc.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]5 *
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]6 * Licensed under the GPL-2
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]7 */
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]8
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_
11
Steven Miao93f89512012-05-16 18:26:10 +0800[diff] [blame]12#ifdef __ASSEMBLY__
13#define PM_REG0 R7
14#define PM_REG1 R6
15#define PM_REG2 R5
16#define PM_REG3 R4
17#define PM_REG4 R3
18#define PM_REG5 R2
19#define PM_REG6 R1
20#define PM_REG7 R0
21#define PM_REG8 P5
22#define PM_REG9 P4
23#define PM_REG10 P3
24#define PM_REG11 P2
25#define PM_REG12 P1
26#define PM_REG13 P0
27
28#define PM_REGSET0 R7:7
29#define PM_REGSET1 R7:6
30#define PM_REGSET2 R7:5
31#define PM_REGSET3 R7:4
32#define PM_REGSET4 R7:3
33#define PM_REGSET5 R7:2
34#define PM_REGSET6 R7:1
35#define PM_REGSET7 R7:0
36#define PM_REGSET8 R7:0, P5:5
37#define PM_REGSET9 R7:0, P5:4
38#define PM_REGSET10 R7:0, P5:3
39#define PM_REGSET11 R7:0, P5:2
40#define PM_REGSET12 R7:0, P5:1
41#define PM_REGSET13 R7:0, P5:0
42
43#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
44#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
45#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
46#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
47#define PM_PUSH(n, x) PM_REG##n = [FP++];
48#define PM_POP(n, x) [FP--] = PM_REG##n;
49#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
50#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
51#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
52#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
53#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
54#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
55
56
57 .macro bfin_cpu_reg_save
58 /*
59 * Save the core regs early so we can blow them away when
60 * saving/restoring MMR states
61 */
62 [--sp] = (R7:0, P5:0);
63 [--sp] = fp;
64 [--sp] = usp;
65
66 [--sp] = i0;
67 [--sp] = i1;
68 [--sp] = i2;
69 [--sp] = i3;
70
71 [--sp] = m0;
72 [--sp] = m1;
73 [--sp] = m2;
74 [--sp] = m3;
75
76 [--sp] = l0;
77 [--sp] = l1;
78 [--sp] = l2;
79 [--sp] = l3;
80
81 [--sp] = b0;
82 [--sp] = b1;
83 [--sp] = b2;
84 [--sp] = b3;
85 [--sp] = a0.x;
86 [--sp] = a0.w;
87 [--sp] = a1.x;
88 [--sp] = a1.w;
89
90 [--sp] = LC0;
91 [--sp] = LC1;
92 [--sp] = LT0;
93 [--sp] = LT1;
94 [--sp] = LB0;
95 [--sp] = LB1;
96
97 /* We can't push RETI directly as that'll change IPEND[4] */
98 r7 = RETI;
99 [--sp] = RETS;
100 [--sp] = ASTAT;
101 [--sp] = CYCLES;
102 [--sp] = CYCLES2;
103 [--sp] = SYSCFG;
104 [--sp] = RETX;
105 [--sp] = SEQSTAT;
106 [--sp] = r7;
107
108 /* Save first func arg in M3 */
109 M3 = R0;
110 .endm
111
112 .macro bfin_cpu_reg_restore
113 /* Restore Core Registers */
114 RETI = [sp++];
115 SEQSTAT = [sp++];
116 RETX = [sp++];
117 SYSCFG = [sp++];
118 CYCLES2 = [sp++];
119 CYCLES = [sp++];
120 ASTAT = [sp++];
121 RETS = [sp++];
122
123 LB1 = [sp++];
124 LB0 = [sp++];
125 LT1 = [sp++];
126 LT0 = [sp++];
127 LC1 = [sp++];
128 LC0 = [sp++];
129
130 a1.w = [sp++];
131 a1.x = [sp++];
132 a0.w = [sp++];
133 a0.x = [sp++];
134 b3 = [sp++];
135 b2 = [sp++];
136 b1 = [sp++];
137 b0 = [sp++];
138
139 l3 = [sp++];
140 l2 = [sp++];
141 l1 = [sp++];
142 l0 = [sp++];
143
144 m3 = [sp++];
145 m2 = [sp++];
146 m1 = [sp++];
147 m0 = [sp++];
148
149 i3 = [sp++];
150 i2 = [sp++];
151 i1 = [sp++];
152 i0 = [sp++];
153
154 usp = [sp++];
155 fp = [sp++];
156 (R7:0, P5:0) = [sp++];
157
158 .endm
159
160 .macro bfin_sys_mmr_save
161 /* Save system MMRs */
162 FP.H = hi(SYSMMR_BASE);
163 FP.L = lo(SYSMMR_BASE);
164#ifdef SIC_IMASK0
165 PM_SYS_PUSH(0, SIC_IMASK0)
166 PM_SYS_PUSH(1, SIC_IMASK1)
167# ifdef SIC_IMASK2
168 PM_SYS_PUSH(2, SIC_IMASK2)
169# endif
170#else
171# ifdef SIC_IMASK
172 PM_SYS_PUSH(0, SIC_IMASK)
173# endif
174#endif
175
176#ifdef SIC_IAR0
177 PM_SYS_PUSH(3, SIC_IAR0)
178 PM_SYS_PUSH(4, SIC_IAR1)
179 PM_SYS_PUSH(5, SIC_IAR2)
180#endif
181#ifdef SIC_IAR3
182 PM_SYS_PUSH(6, SIC_IAR3)
183#endif
184#ifdef SIC_IAR4
185 PM_SYS_PUSH(7, SIC_IAR4)
186 PM_SYS_PUSH(8, SIC_IAR5)
187 PM_SYS_PUSH(9, SIC_IAR6)
188#endif
189#ifdef SIC_IAR7
190 PM_SYS_PUSH(10, SIC_IAR7)
191#endif
192#ifdef SIC_IAR8
193 PM_SYS_PUSH(11, SIC_IAR8)
194 PM_SYS_PUSH(12, SIC_IAR9)
195 PM_SYS_PUSH(13, SIC_IAR10)
196#endif
197 PM_PUSH_SYNC(13)
198#ifdef SIC_IAR11
199 PM_SYS_PUSH(0, SIC_IAR11)
200#endif
201
202#ifdef SIC_IWR
203 PM_SYS_PUSH(1, SIC_IWR)
204#endif
205#ifdef SIC_IWR0
206 PM_SYS_PUSH(1, SIC_IWR0)
207#endif
208#ifdef SIC_IWR1
209 PM_SYS_PUSH(2, SIC_IWR1)
210#endif
211#ifdef SIC_IWR2
212 PM_SYS_PUSH(3, SIC_IWR2)
213#endif
214
215#ifdef PINT0_ASSIGN
216 PM_SYS_PUSH(4, PINT0_MASK_SET)
217 PM_SYS_PUSH(5, PINT1_MASK_SET)
218 PM_SYS_PUSH(6, PINT2_MASK_SET)
219 PM_SYS_PUSH(7, PINT3_MASK_SET)
220 PM_SYS_PUSH(8, PINT0_ASSIGN)
221 PM_SYS_PUSH(9, PINT1_ASSIGN)
222 PM_SYS_PUSH(10, PINT2_ASSIGN)
223 PM_SYS_PUSH(11, PINT3_ASSIGN)
224 PM_SYS_PUSH(12, PINT0_INVERT_SET)
225 PM_SYS_PUSH(13, PINT1_INVERT_SET)
226 PM_PUSH_SYNC(13)
227 PM_SYS_PUSH(0, PINT2_INVERT_SET)
228 PM_SYS_PUSH(1, PINT3_INVERT_SET)
229 PM_SYS_PUSH(2, PINT0_EDGE_SET)
230 PM_SYS_PUSH(3, PINT1_EDGE_SET)
231 PM_SYS_PUSH(4, PINT2_EDGE_SET)
232 PM_SYS_PUSH(5, PINT3_EDGE_SET)
233#endif
234
235#ifdef SYSCR
236 PM_SYS_PUSH16(6, SYSCR)
237#endif
238
239#ifdef EBIU_AMGCTL
240 PM_SYS_PUSH16(7, EBIU_AMGCTL)
241 PM_SYS_PUSH(8, EBIU_AMBCTL0)
242 PM_SYS_PUSH(9, EBIU_AMBCTL1)
243#endif
244#ifdef EBIU_FCTL
245 PM_SYS_PUSH(10, EBIU_MBSCTL)
246 PM_SYS_PUSH(11, EBIU_MODE)
247 PM_SYS_PUSH(12, EBIU_FCTL)
248 PM_PUSH_SYNC(12)
249#else
250 PM_PUSH_SYNC(9)
251#endif
252 .endm
253
254
255 .macro bfin_sys_mmr_restore
256/* Restore System MMRs */
257 FP.H = hi(SYSMMR_BASE);
258 FP.L = lo(SYSMMR_BASE);
259
260#ifdef EBIU_FCTL
261 PM_POP_SYNC(12)
262 PM_SYS_POP(12, EBIU_FCTL)
263 PM_SYS_POP(11, EBIU_MODE)
264 PM_SYS_POP(10, EBIU_MBSCTL)
265#else
266 PM_POP_SYNC(9)
267#endif
268
269#ifdef EBIU_AMBCTL
270 PM_SYS_POP(9, EBIU_AMBCTL1)
271 PM_SYS_POP(8, EBIU_AMBCTL0)
272 PM_SYS_POP16(7, EBIU_AMGCTL)
273#endif
274
275#ifdef SYSCR
276 PM_SYS_POP16(6, SYSCR)
277#endif
278
279#ifdef PINT0_ASSIGN
280 PM_SYS_POP(5, PINT3_EDGE_SET)
281 PM_SYS_POP(4, PINT2_EDGE_SET)
282 PM_SYS_POP(3, PINT1_EDGE_SET)
283 PM_SYS_POP(2, PINT0_EDGE_SET)
284 PM_SYS_POP(1, PINT3_INVERT_SET)
285 PM_SYS_POP(0, PINT2_INVERT_SET)
286 PM_POP_SYNC(13)
287 PM_SYS_POP(13, PINT1_INVERT_SET)
288 PM_SYS_POP(12, PINT0_INVERT_SET)
289 PM_SYS_POP(11, PINT3_ASSIGN)
290 PM_SYS_POP(10, PINT2_ASSIGN)
291 PM_SYS_POP(9, PINT1_ASSIGN)
292 PM_SYS_POP(8, PINT0_ASSIGN)
293 PM_SYS_POP(7, PINT3_MASK_SET)
294 PM_SYS_POP(6, PINT2_MASK_SET)
295 PM_SYS_POP(5, PINT1_MASK_SET)
296 PM_SYS_POP(4, PINT0_MASK_SET)
297#endif
298
299#ifdef SIC_IWR2
300 PM_SYS_POP(3, SIC_IWR2)
301#endif
302#ifdef SIC_IWR1
303 PM_SYS_POP(2, SIC_IWR1)
304#endif
305#ifdef SIC_IWR0
306 PM_SYS_POP(1, SIC_IWR0)
307#endif
308#ifdef SIC_IWR
309 PM_SYS_POP(1, SIC_IWR)
310#endif
311
312#ifdef SIC_IAR11
313 PM_SYS_POP(0, SIC_IAR11)
314#endif
315 PM_POP_SYNC(13)
316#ifdef SIC_IAR8
317 PM_SYS_POP(13, SIC_IAR10)
318 PM_SYS_POP(12, SIC_IAR9)
319 PM_SYS_POP(11, SIC_IAR8)
320#endif
321#ifdef SIC_IAR7
322 PM_SYS_POP(10, SIC_IAR7)
323#endif
324#ifdef SIC_IAR6
325 PM_SYS_POP(9, SIC_IAR6)
326 PM_SYS_POP(8, SIC_IAR5)
327 PM_SYS_POP(7, SIC_IAR4)
328#endif
329#ifdef SIC_IAR3
330 PM_SYS_POP(6, SIC_IAR3)
331#endif
332#ifdef SIC_IAR0
333 PM_SYS_POP(5, SIC_IAR2)
334 PM_SYS_POP(4, SIC_IAR1)
335 PM_SYS_POP(3, SIC_IAR0)
336#endif
337#ifdef SIC_IMASK0
338# ifdef SIC_IMASK2
339 PM_SYS_POP(2, SIC_IMASK2)
340# endif
341 PM_SYS_POP(1, SIC_IMASK1)
342 PM_SYS_POP(0, SIC_IMASK0)
343#else
344# ifdef SIC_IMASK
345 PM_SYS_POP(0, SIC_IMASK)
346# endif
347#endif
348 .endm
349
350 .macro bfin_core_mmr_save
351 /* Save Core MMRs */
352 I0.H = hi(COREMMR_BASE);
353 I0.L = lo(COREMMR_BASE);
354 I1 = I0;
355 I2 = I0;
356 I3 = I0;
357 B0 = I0;
358 B1 = I0;
359 B2 = I0;
360 B3 = I0;
361 I1.L = lo(DCPLB_ADDR0);
362 I2.L = lo(DCPLB_DATA0);
363 I3.L = lo(ICPLB_ADDR0);
364 B0.L = lo(ICPLB_DATA0);
365 B1.L = lo(EVT2);
366 B2.L = lo(IMASK);
367 B3.L = lo(TCNTL);
368
369 /* Event Vectors */
370 FP = B1;
371 PM_PUSH(0, EVT2)
372 PM_PUSH(1, EVT3)
373 FP += 4; /* EVT4 */
374 PM_PUSH(2, EVT5)
375 PM_PUSH(3, EVT6)
376 PM_PUSH(4, EVT7)
377 PM_PUSH(5, EVT8)
378 PM_PUSH_SYNC(5)
379
380 PM_PUSH(0, EVT9)
381 PM_PUSH(1, EVT10)
382 PM_PUSH(2, EVT11)
383 PM_PUSH(3, EVT12)
384 PM_PUSH(4, EVT13)
385 PM_PUSH(5, EVT14)
386 PM_PUSH(6, EVT15)
387
388 /* CEC */
389 FP = B2;
390 PM_PUSH(7, IMASK)
391 FP += 4; /* IPEND */
392 PM_PUSH(8, ILAT)
393 PM_PUSH(9, IPRIO)
394
395 /* Core Timer */
396 FP = B3;
397 PM_PUSH(10, TCNTL)
398 PM_PUSH(11, TPERIOD)
399 PM_PUSH(12, TSCALE)
400 PM_PUSH(13, TCOUNT)
401 PM_PUSH_SYNC(13)
402
403 /* Misc non-contiguous registers */
404 FP = I0;
405 PM_CORE_PUSH(0, DMEM_CONTROL);
406 PM_CORE_PUSH(1, IMEM_CONTROL);
407 PM_CORE_PUSH(2, TBUFCTL);
408 PM_PUSH_SYNC(2)
409
410 /* DCPLB Addr */
411 FP = I1;
412 PM_PUSH(0, DCPLB_ADDR0)
413 PM_PUSH(1, DCPLB_ADDR1)
414 PM_PUSH(2, DCPLB_ADDR2)
415 PM_PUSH(3, DCPLB_ADDR3)
416 PM_PUSH(4, DCPLB_ADDR4)
417 PM_PUSH(5, DCPLB_ADDR5)
418 PM_PUSH(6, DCPLB_ADDR6)
419 PM_PUSH(7, DCPLB_ADDR7)
420 PM_PUSH(8, DCPLB_ADDR8)
421 PM_PUSH(9, DCPLB_ADDR9)
422 PM_PUSH(10, DCPLB_ADDR10)
423 PM_PUSH(11, DCPLB_ADDR11)
424 PM_PUSH(12, DCPLB_ADDR12)
425 PM_PUSH(13, DCPLB_ADDR13)
426 PM_PUSH_SYNC(13)
427 PM_PUSH(0, DCPLB_ADDR14)
428 PM_PUSH(1, DCPLB_ADDR15)
429
430 /* DCPLB Data */
431 FP = I2;
432 PM_PUSH(2, DCPLB_DATA0)
433 PM_PUSH(3, DCPLB_DATA1)
434 PM_PUSH(4, DCPLB_DATA2)
435 PM_PUSH(5, DCPLB_DATA3)
436 PM_PUSH(6, DCPLB_DATA4)
437 PM_PUSH(7, DCPLB_DATA5)
438 PM_PUSH(8, DCPLB_DATA6)
439 PM_PUSH(9, DCPLB_DATA7)
440 PM_PUSH(10, DCPLB_DATA8)
441 PM_PUSH(11, DCPLB_DATA9)
442 PM_PUSH(12, DCPLB_DATA10)
443 PM_PUSH(13, DCPLB_DATA11)
444 PM_PUSH_SYNC(13)
445 PM_PUSH(0, DCPLB_DATA12)
446 PM_PUSH(1, DCPLB_DATA13)
447 PM_PUSH(2, DCPLB_DATA14)
448 PM_PUSH(3, DCPLB_DATA15)
449
450 /* ICPLB Addr */
451 FP = I3;
452 PM_PUSH(4, ICPLB_ADDR0)
453 PM_PUSH(5, ICPLB_ADDR1)
454 PM_PUSH(6, ICPLB_ADDR2)
455 PM_PUSH(7, ICPLB_ADDR3)
456 PM_PUSH(8, ICPLB_ADDR4)
457 PM_PUSH(9, ICPLB_ADDR5)
458 PM_PUSH(10, ICPLB_ADDR6)
459 PM_PUSH(11, ICPLB_ADDR7)
460 PM_PUSH(12, ICPLB_ADDR8)
461 PM_PUSH(13, ICPLB_ADDR9)
462 PM_PUSH_SYNC(13)
463 PM_PUSH(0, ICPLB_ADDR10)
464 PM_PUSH(1, ICPLB_ADDR11)
465 PM_PUSH(2, ICPLB_ADDR12)
466 PM_PUSH(3, ICPLB_ADDR13)
467 PM_PUSH(4, ICPLB_ADDR14)
468 PM_PUSH(5, ICPLB_ADDR15)
469
470 /* ICPLB Data */
471 FP = B0;
472 PM_PUSH(6, ICPLB_DATA0)
473 PM_PUSH(7, ICPLB_DATA1)
474 PM_PUSH(8, ICPLB_DATA2)
475 PM_PUSH(9, ICPLB_DATA3)
476 PM_PUSH(10, ICPLB_DATA4)
477 PM_PUSH(11, ICPLB_DATA5)
478 PM_PUSH(12, ICPLB_DATA6)
479 PM_PUSH(13, ICPLB_DATA7)
480 PM_PUSH_SYNC(13)
481 PM_PUSH(0, ICPLB_DATA8)
482 PM_PUSH(1, ICPLB_DATA9)
483 PM_PUSH(2, ICPLB_DATA10)
484 PM_PUSH(3, ICPLB_DATA11)
485 PM_PUSH(4, ICPLB_DATA12)
486 PM_PUSH(5, ICPLB_DATA13)
487 PM_PUSH(6, ICPLB_DATA14)
488 PM_PUSH(7, ICPLB_DATA15)
489 PM_PUSH_SYNC(7)
490 .endm
491
492 .macro bfin_core_mmr_restore
493 /* Restore Core MMRs */
494 I0.H = hi(COREMMR_BASE);
495 I0.L = lo(COREMMR_BASE);
496 I1 = I0;
497 I2 = I0;
498 I3 = I0;
499 B0 = I0;
500 B1 = I0;
501 B2 = I0;
502 B3 = I0;
503 I1.L = lo(DCPLB_ADDR15);
504 I2.L = lo(DCPLB_DATA15);
505 I3.L = lo(ICPLB_ADDR15);
506 B0.L = lo(ICPLB_DATA15);
507 B1.L = lo(EVT15);
508 B2.L = lo(IPRIO);
509 B3.L = lo(TCOUNT);
510
511 /* ICPLB Data */
512 FP = B0;
513 PM_POP_SYNC(7)
514 PM_POP(7, ICPLB_DATA15)
515 PM_POP(6, ICPLB_DATA14)
516 PM_POP(5, ICPLB_DATA13)
517 PM_POP(4, ICPLB_DATA12)
518 PM_POP(3, ICPLB_DATA11)
519 PM_POP(2, ICPLB_DATA10)
520 PM_POP(1, ICPLB_DATA9)
521 PM_POP(0, ICPLB_DATA8)
522 PM_POP_SYNC(13)
523 PM_POP(13, ICPLB_DATA7)
524 PM_POP(12, ICPLB_DATA6)
525 PM_POP(11, ICPLB_DATA5)
526 PM_POP(10, ICPLB_DATA4)
527 PM_POP(9, ICPLB_DATA3)
528 PM_POP(8, ICPLB_DATA2)
529 PM_POP(7, ICPLB_DATA1)
530 PM_POP(6, ICPLB_DATA0)
531
532 /* ICPLB Addr */
533 FP = I3;
534 PM_POP(5, ICPLB_ADDR15)
535 PM_POP(4, ICPLB_ADDR14)
536 PM_POP(3, ICPLB_ADDR13)
537 PM_POP(2, ICPLB_ADDR12)
538 PM_POP(1, ICPLB_ADDR11)
539 PM_POP(0, ICPLB_ADDR10)
540 PM_POP_SYNC(13)
541 PM_POP(13, ICPLB_ADDR9)
542 PM_POP(12, ICPLB_ADDR8)
543 PM_POP(11, ICPLB_ADDR7)
544 PM_POP(10, ICPLB_ADDR6)
545 PM_POP(9, ICPLB_ADDR5)
546 PM_POP(8, ICPLB_ADDR4)
547 PM_POP(7, ICPLB_ADDR3)
548 PM_POP(6, ICPLB_ADDR2)
549 PM_POP(5, ICPLB_ADDR1)
550 PM_POP(4, ICPLB_ADDR0)
551
552 /* DCPLB Data */
553 FP = I2;
554 PM_POP(3, DCPLB_DATA15)
555 PM_POP(2, DCPLB_DATA14)
556 PM_POP(1, DCPLB_DATA13)
557 PM_POP(0, DCPLB_DATA12)
558 PM_POP_SYNC(13)
559 PM_POP(13, DCPLB_DATA11)
560 PM_POP(12, DCPLB_DATA10)
561 PM_POP(11, DCPLB_DATA9)
562 PM_POP(10, DCPLB_DATA8)
563 PM_POP(9, DCPLB_DATA7)
564 PM_POP(8, DCPLB_DATA6)
565 PM_POP(7, DCPLB_DATA5)
566 PM_POP(6, DCPLB_DATA4)
567 PM_POP(5, DCPLB_DATA3)
568 PM_POP(4, DCPLB_DATA2)
569 PM_POP(3, DCPLB_DATA1)
570 PM_POP(2, DCPLB_DATA0)
571
572 /* DCPLB Addr */
573 FP = I1;
574 PM_POP(1, DCPLB_ADDR15)
575 PM_POP(0, DCPLB_ADDR14)
576 PM_POP_SYNC(13)
577 PM_POP(13, DCPLB_ADDR13)
578 PM_POP(12, DCPLB_ADDR12)
579 PM_POP(11, DCPLB_ADDR11)
580 PM_POP(10, DCPLB_ADDR10)
581 PM_POP(9, DCPLB_ADDR9)
582 PM_POP(8, DCPLB_ADDR8)
583 PM_POP(7, DCPLB_ADDR7)
584 PM_POP(6, DCPLB_ADDR6)
585 PM_POP(5, DCPLB_ADDR5)
586 PM_POP(4, DCPLB_ADDR4)
587 PM_POP(3, DCPLB_ADDR3)
588 PM_POP(2, DCPLB_ADDR2)
589 PM_POP(1, DCPLB_ADDR1)
590 PM_POP(0, DCPLB_ADDR0)
591
592
593 /* Misc non-contiguous registers */
594
595 /* icache & dcache will enable later
596 drop IMEM_CONTROL, DMEM_CONTROL pop
597 */
598 FP = I0;
599 PM_POP_SYNC(2)
600 PM_CORE_POP(2, TBUFCTL)
601 PM_CORE_POP(1, IMEM_CONTROL)
602 PM_CORE_POP(0, DMEM_CONTROL)
603
604 /* Core Timer */
605 FP = B3;
606 R0 = 0x1;
607 [FP - 0xC] = R0;
608
609 PM_POP_SYNC(13)
610 FP = B3;
611 PM_POP(13, TCOUNT)
612 PM_POP(12, TSCALE)
613 PM_POP(11, TPERIOD)
614 PM_POP(10, TCNTL)
615
616 /* CEC */
617 FP = B2;
618 PM_POP(9, IPRIO)
619 PM_POP(8, ILAT)
620 FP += -4; /* IPEND */
621 PM_POP(7, IMASK)
622
623 /* Event Vectors */
624 FP = B1;
625 PM_POP(6, EVT15)
626 PM_POP(5, EVT14)
627 PM_POP(4, EVT13)
628 PM_POP(3, EVT12)
629 PM_POP(2, EVT11)
630 PM_POP(1, EVT10)
631 PM_POP(0, EVT9)
632 PM_POP_SYNC(5)
633 PM_POP(5, EVT8)
634 PM_POP(4, EVT7)
635 PM_POP(3, EVT6)
636 PM_POP(2, EVT5)
637 FP += -4; /* EVT4 */
638 PM_POP(1, EVT3)
639 PM_POP(0, EVT2)
640 .endm
641#endif
642
Mike Frysingere15124c2010-10-28 15:34:09 -0400[diff] [blame]643#include <mach/pll.h>
644
Mike Frysingera8e8e492009-10-15 06:47:28 +0000[diff] [blame]645/* PLL_CTL Masks */
646#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
647#define PLL_OFF 0x0002 /* PLL Not Powered */
648#define STOPCK 0x0008 /* Core Clock Off */
649#define PDWN 0x0020 /* Enter Deep Sleep Mode */
650#ifdef __ADSPBF539__
651# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
652# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
653#else
654# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
655# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
656#endif
657#define BYPASS 0x0100 /* Bypass the PLL */
658#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
659#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
660#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
661
662/* PLL_DIV Masks */
663#define SSEL 0x000F /* System Select */
664#define CSEL 0x0030 /* Core Select */
665#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
666#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
667#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
668#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
669
670#define CCLK_DIV1 CSEL_DIV1
671#define CCLK_DIV2 CSEL_DIV2
672#define CCLK_DIV4 CSEL_DIV4
673#define CCLK_DIV8 CSEL_DIV8
674
675#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
676#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
677
678/* PLL_STAT Masks */
679#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
680#define FULL_ON 0x0002 /* Processor In Full On Mode */
681#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
682#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
683
684#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
685#define CANWS 0x0800 /* CAN Wake-Up Status */
686#define USBWS 0x2000 /* USB Wake-Up Status */
687#define KPADWS 0x4000 /* Keypad Wake-Up Status */
688#define ROTWS 0x8000 /* Rotary Wake-Up Status */
689#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
690
691/* VR_CTL Masks */
692#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
693#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
694#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
695#else
696#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
697#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
698#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
699#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
700#endif
701#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
702
703#define GAIN 0x000C /* Voltage Level Gain */
704#define GAIN_5 0x0000 /* GAIN = 5 */
705#define GAIN_10 0x0004 /* GAIN = 1 */
706#define GAIN_20 0x0008 /* GAIN = 2 */
707#define GAIN_50 0x000C /* GAIN = 5 */
708
709#define VLEV 0x00F0 /* Internal Voltage Level */
710#ifdef __ADSPBF52x__
Mike Frysingerf2b0cd62010-03-04 07:35:30 -0500[diff] [blame]711#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
Mike Frysingera8e8e492009-10-15 06:47:28 +0000[diff] [blame]712#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
713#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
714#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
715#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
716#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
717#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
718#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
719#else
Mike Frysingerf2b0cd62010-03-04 07:35:30 -0500[diff] [blame]720#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
Mike Frysingera8e8e492009-10-15 06:47:28 +0000[diff] [blame]721#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
722#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
723#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
724#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
725#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
726#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
727#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
728#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
729#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
730#endif
731
Steven Miao0fbd88c2012-05-17 17:29:54 +0800[diff] [blame^]732#ifdef CONFIG_BF60x
733#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */
734#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */
735#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */
736#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
737#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
738#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
739#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */
740#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */
741#else
Mike Frysingera8e8e492009-10-15 06:47:28 +0000[diff] [blame]742#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
743#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
744#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
745#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
746#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
747#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
748#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
749#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
750#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
751
752#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
753#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
754#else
755#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
756#endif
Steven Miao0fbd88c2012-05-17 17:29:54 +0800[diff] [blame^]757#endif
Steven Miao93f89512012-05-16 18:26:10 +0800[diff] [blame]758
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800[diff] [blame]759#ifndef __ASSEMBLY__
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]760
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800[diff] [blame]761void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800[diff] [blame]762void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800[diff] [blame]763void do_hibernate(int wakeup);
764void set_dram_srfs(void);
765void unset_dram_srfs(void);
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]766
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800[diff] [blame]767#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]768
Graf Yang6f546bc2010-01-28 10:46:55 +0000[diff] [blame]769#ifdef CONFIG_CPU_FREQ
770#define CPUFREQ_CPU 0
771#endif
Michael Hennerich14b03202008-05-07 11:41:26 +0800[diff] [blame]772struct bfin_dpmc_platform_data {
773 const unsigned int *tuple_tab;
774 unsigned short tabsize;
775 unsigned short vr_settling_time; /* in us */
776};
777
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800[diff] [blame]778#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]779
780#endif /*_BLACKFIN_DPMC_H_*/