Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a7793 SoC |
| 3 | * |
| 4 | * Copyright (C) 2014-2015 Renesas Electronics Corporation |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <dt-bindings/clock/r8a7793-clock.h> |
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 14 | |
| 15 | / { |
| 16 | compatible = "renesas,r8a7793"; |
| 17 | interrupt-parent = <&gic>; |
| 18 | #address-cells = <2>; |
| 19 | #size-cells = <2>; |
| 20 | |
| 21 | cpus { |
| 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; |
| 24 | |
| 25 | cpu0: cpu@0 { |
| 26 | device_type = "cpu"; |
| 27 | compatible = "arm,cortex-a15"; |
| 28 | reg = <0>; |
| 29 | clock-frequency = <1500000000>; |
| 30 | voltage-tolerance = <1>; /* 1% */ |
| 31 | clocks = <&cpg_clocks R8A7793_CLK_Z>; |
| 32 | clock-latency = <300000>; /* 300 us */ |
| 33 | |
| 34 | /* kHz - uV - OPPs unknown yet */ |
| 35 | operating-points = <1500000 1000000>, |
| 36 | <1312500 1000000>, |
| 37 | <1125000 1000000>, |
| 38 | < 937500 1000000>, |
| 39 | < 750000 1000000>, |
| 40 | < 375000 1000000>; |
| 41 | }; |
| 42 | }; |
| 43 | |
| 44 | gic: interrupt-controller@f1001000 { |
Geert Uytterhoeven | 5b3b326 | 2015-06-17 15:03:35 +0200 | [diff] [blame] | 45 | compatible = "arm,gic-400"; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 46 | #interrupt-cells = <3>; |
| 47 | #address-cells = <0>; |
| 48 | interrupt-controller; |
| 49 | reg = <0 0xf1001000 0 0x1000>, |
| 50 | <0 0xf1002000 0 0x1000>, |
| 51 | <0 0xf1004000 0 0x2000>, |
| 52 | <0 0xf1006000 0 0x2000>; |
| 53 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 54 | }; |
| 55 | |
Simon Horman | 0fddfb5 | 2015-11-06 16:30:48 +0900 | [diff] [blame^] | 56 | thermal@e61f0000 { |
| 57 | compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal"; |
| 58 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
| 59 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| 60 | clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; |
| 61 | power-domains = <&cpg_clocks>; |
| 62 | }; |
| 63 | |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 64 | timer { |
| 65 | compatible = "arm,armv7-timer"; |
| 66 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 67 | <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 68 | <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 69 | <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| 70 | }; |
| 71 | |
| 72 | cmt0: timer@ffca0000 { |
| 73 | compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; |
| 74 | reg = <0 0xffca0000 0 0x1004>; |
| 75 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <0 143 IRQ_TYPE_LEVEL_HIGH>; |
| 77 | clocks = <&mstp1_clks R8A7793_CLK_CMT0>; |
| 78 | clock-names = "fck"; |
Geert Uytterhoeven | 4b31bad | 2015-08-04 14:28:12 +0200 | [diff] [blame] | 79 | power-domains = <&cpg_clocks>; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 80 | |
| 81 | renesas,channels-mask = <0x60>; |
| 82 | |
| 83 | status = "disabled"; |
| 84 | }; |
| 85 | |
| 86 | cmt1: timer@e6130000 { |
| 87 | compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; |
| 88 | reg = <0 0xe6130000 0 0x1004>; |
| 89 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, |
| 90 | <0 121 IRQ_TYPE_LEVEL_HIGH>, |
| 91 | <0 122 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | <0 123 IRQ_TYPE_LEVEL_HIGH>, |
| 93 | <0 124 IRQ_TYPE_LEVEL_HIGH>, |
| 94 | <0 125 IRQ_TYPE_LEVEL_HIGH>, |
| 95 | <0 126 IRQ_TYPE_LEVEL_HIGH>, |
| 96 | <0 127 IRQ_TYPE_LEVEL_HIGH>; |
| 97 | clocks = <&mstp3_clks R8A7793_CLK_CMT1>; |
| 98 | clock-names = "fck"; |
Geert Uytterhoeven | 4b31bad | 2015-08-04 14:28:12 +0200 | [diff] [blame] | 99 | power-domains = <&cpg_clocks>; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 100 | |
| 101 | renesas,channels-mask = <0xff>; |
| 102 | |
| 103 | status = "disabled"; |
| 104 | }; |
| 105 | |
| 106 | irqc0: interrupt-controller@e61c0000 { |
| 107 | compatible = "renesas,irqc-r8a7793", "renesas,irqc"; |
| 108 | #interrupt-cells = <2>; |
| 109 | interrupt-controller; |
| 110 | reg = <0 0xe61c0000 0 0x200>; |
| 111 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 112 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 113 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| 114 | <0 3 IRQ_TYPE_LEVEL_HIGH>, |
| 115 | <0 12 IRQ_TYPE_LEVEL_HIGH>, |
| 116 | <0 13 IRQ_TYPE_LEVEL_HIGH>, |
| 117 | <0 14 IRQ_TYPE_LEVEL_HIGH>, |
| 118 | <0 15 IRQ_TYPE_LEVEL_HIGH>, |
| 119 | <0 16 IRQ_TYPE_LEVEL_HIGH>, |
| 120 | <0 17 IRQ_TYPE_LEVEL_HIGH>; |
| 121 | clocks = <&mstp4_clks R8A7793_CLK_IRQC>; |
Geert Uytterhoeven | 4b31bad | 2015-08-04 14:28:12 +0200 | [diff] [blame] | 122 | power-domains = <&cpg_clocks>; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | scif0: serial@e6e60000 { |
| 126 | compatible = "renesas,scif-r8a7793", "renesas,scif"; |
| 127 | reg = <0 0xe6e60000 0 64>; |
| 128 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
| 129 | clocks = <&mstp7_clks R8A7793_CLK_SCIF0>; |
| 130 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 4b31bad | 2015-08-04 14:28:12 +0200 | [diff] [blame] | 131 | power-domains = <&cpg_clocks>; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 132 | status = "disabled"; |
| 133 | }; |
| 134 | |
| 135 | scif1: serial@e6e68000 { |
| 136 | compatible = "renesas,scif-r8a7793", "renesas,scif"; |
| 137 | reg = <0 0xe6e68000 0 64>; |
| 138 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
| 139 | clocks = <&mstp7_clks R8A7793_CLK_SCIF1>; |
| 140 | clock-names = "sci_ick"; |
Geert Uytterhoeven | 4b31bad | 2015-08-04 14:28:12 +0200 | [diff] [blame] | 141 | power-domains = <&cpg_clocks>; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 142 | status = "disabled"; |
| 143 | }; |
| 144 | |
| 145 | ether: ethernet@ee700000 { |
| 146 | compatible = "renesas,ether-r8a7793"; |
| 147 | reg = <0 0xee700000 0 0x400>; |
| 148 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; |
| 149 | clocks = <&mstp8_clks R8A7793_CLK_ETHER>; |
Geert Uytterhoeven | 4b31bad | 2015-08-04 14:28:12 +0200 | [diff] [blame] | 150 | power-domains = <&cpg_clocks>; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 151 | phy-mode = "rmii"; |
| 152 | #address-cells = <1>; |
| 153 | #size-cells = <0>; |
| 154 | status = "disabled"; |
| 155 | }; |
| 156 | |
| 157 | clocks { |
| 158 | #address-cells = <2>; |
| 159 | #size-cells = <2>; |
| 160 | ranges; |
| 161 | |
| 162 | /* External root clock */ |
| 163 | extal_clk: extal_clk { |
| 164 | compatible = "fixed-clock"; |
| 165 | #clock-cells = <0>; |
| 166 | /* This value must be overridden by the board. */ |
| 167 | clock-frequency = <0>; |
| 168 | clock-output-names = "extal"; |
| 169 | }; |
| 170 | |
| 171 | /* Special CPG clocks */ |
| 172 | cpg_clocks: cpg_clocks@e6150000 { |
| 173 | compatible = "renesas,r8a7793-cpg-clocks", |
| 174 | "renesas,rcar-gen2-cpg-clocks"; |
| 175 | reg = <0 0xe6150000 0 0x1000>; |
| 176 | clocks = <&extal_clk>; |
| 177 | #clock-cells = <1>; |
| 178 | clock-output-names = "main", "pll0", "pll1", "pll3", |
| 179 | "lb", "qspi", "sdh", "sd0", "z", |
| 180 | "rcan", "adsp"; |
Geert Uytterhoeven | 4b31bad | 2015-08-04 14:28:12 +0200 | [diff] [blame] | 181 | #power-domain-cells = <0>; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | /* Variable factor clocks */ |
| 185 | sd2_clk: sd2_clk@e6150078 { |
| 186 | compatible = "renesas,r8a7793-div6-clock", |
| 187 | "renesas,cpg-div6-clock"; |
| 188 | reg = <0 0xe6150078 0 4>; |
| 189 | clocks = <&pll1_div2_clk>; |
| 190 | #clock-cells = <0>; |
| 191 | clock-output-names = "sd2"; |
| 192 | }; |
| 193 | sd3_clk: sd3_clk@e615026c { |
| 194 | compatible = "renesas,r8a7793-div6-clock", |
| 195 | "renesas,cpg-div6-clock"; |
| 196 | reg = <0 0xe615026c 0 4>; |
| 197 | clocks = <&pll1_div2_clk>; |
| 198 | #clock-cells = <0>; |
| 199 | clock-output-names = "sd3"; |
| 200 | }; |
| 201 | mmc0_clk: mmc0_clk@e6150240 { |
| 202 | compatible = "renesas,r8a7793-div6-clock", |
| 203 | "renesas,cpg-div6-clock"; |
| 204 | reg = <0 0xe6150240 0 4>; |
| 205 | clocks = <&pll1_div2_clk>; |
| 206 | #clock-cells = <0>; |
| 207 | clock-output-names = "mmc0"; |
| 208 | }; |
| 209 | |
| 210 | /* Fixed factor clocks */ |
| 211 | pll1_div2_clk: pll1_div2_clk { |
| 212 | compatible = "fixed-factor-clock"; |
| 213 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; |
| 214 | #clock-cells = <0>; |
| 215 | clock-div = <2>; |
| 216 | clock-mult = <1>; |
| 217 | clock-output-names = "pll1_div2"; |
| 218 | }; |
| 219 | zg_clk: zg_clk { |
| 220 | compatible = "fixed-factor-clock"; |
| 221 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; |
| 222 | #clock-cells = <0>; |
| 223 | clock-div = <5>; |
| 224 | clock-mult = <1>; |
| 225 | clock-output-names = "zg"; |
| 226 | }; |
| 227 | zx_clk: zx_clk { |
| 228 | compatible = "fixed-factor-clock"; |
| 229 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; |
| 230 | #clock-cells = <0>; |
| 231 | clock-div = <3>; |
| 232 | clock-mult = <1>; |
| 233 | clock-output-names = "zx"; |
| 234 | }; |
| 235 | zs_clk: zs_clk { |
| 236 | compatible = "fixed-factor-clock"; |
| 237 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; |
| 238 | #clock-cells = <0>; |
| 239 | clock-div = <6>; |
| 240 | clock-mult = <1>; |
| 241 | clock-output-names = "zs"; |
| 242 | }; |
| 243 | hp_clk: hp_clk { |
| 244 | compatible = "fixed-factor-clock"; |
| 245 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; |
| 246 | #clock-cells = <0>; |
| 247 | clock-div = <12>; |
| 248 | clock-mult = <1>; |
| 249 | clock-output-names = "hp"; |
| 250 | }; |
| 251 | p_clk: p_clk { |
| 252 | compatible = "fixed-factor-clock"; |
| 253 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; |
| 254 | #clock-cells = <0>; |
| 255 | clock-div = <24>; |
| 256 | clock-mult = <1>; |
| 257 | clock-output-names = "p"; |
| 258 | }; |
| 259 | rclk_clk: rclk_clk { |
| 260 | compatible = "fixed-factor-clock"; |
| 261 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; |
| 262 | #clock-cells = <0>; |
| 263 | clock-div = <(48 * 1024)>; |
| 264 | clock-mult = <1>; |
| 265 | clock-output-names = "rclk"; |
| 266 | }; |
| 267 | mp_clk: mp_clk { |
| 268 | compatible = "fixed-factor-clock"; |
| 269 | clocks = <&pll1_div2_clk>; |
| 270 | #clock-cells = <0>; |
| 271 | clock-div = <15>; |
| 272 | clock-mult = <1>; |
| 273 | clock-output-names = "mp"; |
| 274 | }; |
| 275 | cp_clk: cp_clk { |
| 276 | compatible = "fixed-factor-clock"; |
| 277 | clocks = <&extal_clk>; |
| 278 | #clock-cells = <0>; |
| 279 | clock-div = <2>; |
| 280 | clock-mult = <1>; |
| 281 | clock-output-names = "cp"; |
| 282 | }; |
| 283 | |
| 284 | /* Gate clocks */ |
| 285 | mstp1_clks: mstp1_clks@e6150134 { |
| 286 | compatible = "renesas,r8a7793-mstp-clocks", |
| 287 | "renesas,cpg-mstp-clocks"; |
| 288 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
| 289 | clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
| 290 | <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, |
| 291 | <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, |
| 292 | <&zs_clk>, <&zs_clk>, <&zs_clk>; |
| 293 | #clock-cells = <1>; |
| 294 | clock-indices = < |
| 295 | R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 |
| 296 | R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 |
| 297 | R8A7793_CLK_3DG R8A7793_CLK_2DDMAC |
| 298 | R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 |
| 299 | R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 |
| 300 | R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 |
| 301 | R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 |
| 302 | R8A7793_CLK_VSP1_S |
| 303 | >; |
| 304 | clock-output-names = |
| 305 | "vcp0", "vpc0", "ssp_dev", "tmu1", |
| 306 | "pvrsrvkm", "tddmac", "fdp1", "fdp0", |
| 307 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", |
| 308 | "vsp1-du0", "vsps"; |
| 309 | }; |
| 310 | mstp3_clks: mstp3_clks@e615013c { |
| 311 | compatible = "renesas,r8a7793-mstp-clocks", |
| 312 | "renesas,cpg-mstp-clocks"; |
| 313 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| 314 | clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, |
| 315 | <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, |
| 316 | <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, |
| 317 | <&rclk_clk>, <&hp_clk>, <&hp_clk>; |
| 318 | #clock-cells = <1>; |
| 319 | clock-indices = < |
| 320 | R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 |
| 321 | R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 |
| 322 | R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 |
| 323 | R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 |
| 324 | R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 |
| 325 | R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 |
| 326 | >; |
| 327 | clock-output-names = |
| 328 | "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", |
| 329 | "i2c7", "pciec", "i2c8", "ssusb", "cmt1", |
| 330 | "usbdmac0", "usbdmac1"; |
| 331 | }; |
| 332 | mstp4_clks: mstp4_clks@e6150140 { |
| 333 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 334 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| 335 | clocks = <&cp_clk>; |
| 336 | #clock-cells = <1>; |
| 337 | clock-indices = <R8A7793_CLK_IRQC>; |
| 338 | clock-output-names = "irqc"; |
| 339 | }; |
Simon Horman | 0fddfb5 | 2015-11-06 16:30:48 +0900 | [diff] [blame^] | 340 | mstp5_clks: mstp5_clks@e6150144 { |
| 341 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 342 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
| 343 | clocks = <&extal_clk>; |
| 344 | #clock-cells = <1>; |
| 345 | clock-indices = <R8A7793_CLK_THERMAL>; |
| 346 | clock-output-names = "thermal"; |
| 347 | }; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 348 | mstp7_clks: mstp7_clks@e615014c { |
| 349 | compatible = "renesas,r8a7793-mstp-clocks", |
| 350 | "renesas,cpg-mstp-clocks"; |
| 351 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
| 352 | clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, |
| 353 | <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
| 354 | <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, |
| 355 | <&zx_clk>, <&zx_clk>; |
| 356 | #clock-cells = <1>; |
| 357 | clock-indices = < |
| 358 | R8A7793_CLK_EHCI R8A7793_CLK_HSUSB |
| 359 | R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 |
| 360 | R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 |
| 361 | R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 |
| 362 | R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 |
| 363 | R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 |
| 364 | R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 |
| 365 | >; |
| 366 | clock-output-names = |
| 367 | "ehci", "hsusb", "hscif2", "scif5", "scif4", |
| 368 | "hscif1", "hscif0", "scif3", "scif2", |
| 369 | "scif1", "scif0", "du1", "du0", "lvds0"; |
| 370 | }; |
| 371 | mstp8_clks: mstp8_clks@e6150990 { |
| 372 | compatible = "renesas,r8a7793-mstp-clocks", |
| 373 | "renesas,cpg-mstp-clocks"; |
| 374 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
| 375 | clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, |
| 376 | <&p_clk>, <&zs_clk>, <&zs_clk>; |
| 377 | #clock-cells = <1>; |
| 378 | clock-indices = < |
| 379 | R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 |
| 380 | R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 |
| 381 | R8A7793_CLK_ETHER R8A7793_CLK_SATA1 |
| 382 | R8A7793_CLK_SATA0 |
| 383 | >; |
| 384 | clock-output-names = |
| 385 | "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", |
| 386 | "sata1", "sata0"; |
| 387 | }; |
| 388 | }; |
| 389 | |
Magnus Damm | 098cb3a | 2015-10-18 14:35:41 +0900 | [diff] [blame] | 390 | ipmmu_sy0: mmu@e6280000 { |
| 391 | compatible = "renesas,ipmmu-vmsa"; |
| 392 | reg = <0 0xe6280000 0 0x1000>; |
| 393 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, |
| 394 | <0 224 IRQ_TYPE_LEVEL_HIGH>; |
| 395 | #iommu-cells = <1>; |
| 396 | status = "disabled"; |
| 397 | }; |
| 398 | |
| 399 | ipmmu_sy1: mmu@e6290000 { |
| 400 | compatible = "renesas,ipmmu-vmsa"; |
| 401 | reg = <0 0xe6290000 0 0x1000>; |
| 402 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; |
| 403 | #iommu-cells = <1>; |
| 404 | status = "disabled"; |
| 405 | }; |
| 406 | |
| 407 | ipmmu_ds: mmu@e6740000 { |
| 408 | compatible = "renesas,ipmmu-vmsa"; |
| 409 | reg = <0 0xe6740000 0 0x1000>; |
| 410 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, |
| 411 | <0 199 IRQ_TYPE_LEVEL_HIGH>; |
| 412 | #iommu-cells = <1>; |
| 413 | status = "disabled"; |
| 414 | }; |
| 415 | |
| 416 | ipmmu_mp: mmu@ec680000 { |
| 417 | compatible = "renesas,ipmmu-vmsa"; |
| 418 | reg = <0 0xec680000 0 0x1000>; |
| 419 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; |
| 420 | #iommu-cells = <1>; |
| 421 | status = "disabled"; |
| 422 | }; |
| 423 | |
| 424 | ipmmu_mx: mmu@fe951000 { |
| 425 | compatible = "renesas,ipmmu-vmsa"; |
| 426 | reg = <0 0xfe951000 0 0x1000>; |
| 427 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, |
| 428 | <0 221 IRQ_TYPE_LEVEL_HIGH>; |
| 429 | #iommu-cells = <1>; |
| 430 | status = "disabled"; |
| 431 | }; |
| 432 | |
| 433 | ipmmu_rt: mmu@ffc80000 { |
| 434 | compatible = "renesas,ipmmu-vmsa"; |
| 435 | reg = <0 0xffc80000 0 0x1000>; |
| 436 | interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; |
| 437 | #iommu-cells = <1>; |
| 438 | status = "disabled"; |
| 439 | }; |
| 440 | |
| 441 | ipmmu_gp: mmu@e62a0000 { |
| 442 | compatible = "renesas,ipmmu-vmsa"; |
| 443 | reg = <0 0xe62a0000 0 0x1000>; |
| 444 | interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, |
| 445 | <0 261 IRQ_TYPE_LEVEL_HIGH>; |
| 446 | #iommu-cells = <1>; |
| 447 | status = "disabled"; |
| 448 | }; |
Ulrich Hecht | 0e03e8a | 2015-06-01 16:22:55 +0200 | [diff] [blame] | 449 | }; |