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Giuliano Pochinidd7b2542006-06-28 13:53:41 +02001/****************************************************************************
2
3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
4 All rights reserved
5 www.echoaudio.com
6
7 This file is part of Echo Digital Audio's generic driver library.
8
9 Echo Digital Audio's generic driver library is free software;
10 you can redistribute it and/or modify it under the terms of
11 the GNU General Public License as published by the Free Software
12 Foundation.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
23
24 *************************************************************************
25
26 Translation from C++ and adaptation for use in ALSA-Driver
27 were made by Giuliano Pochini <pochini@shiny.it>
28
29****************************************************************************/
30
31
32static int write_control_reg(struct echoaudio *chip, u32 value, char force);
33static int set_input_clock(struct echoaudio *chip, u16 clock);
34static int set_professional_spdif(struct echoaudio *chip, char prof);
35static int set_digital_mode(struct echoaudio *chip, u8 mode);
Giuliano Pochini19b50062010-02-14 18:15:34 +010036static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
Giuliano Pochinidd7b2542006-06-28 13:53:41 +020037static int check_asic_status(struct echoaudio *chip);
38
39
40static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
41{
42 int err;
43
44 DE_INIT(("init_hw() - Mona\n"));
Takashi Iwaida3cec32008-08-08 17:12:14 +020045 if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA))
46 return -ENODEV;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +020047
48 if ((err = init_dsp_comm_page(chip))) {
49 DE_INIT(("init_hw - could not initialize DSP comm page\n"));
50 return err;
51 }
52
53 chip->device_id = device_id;
54 chip->subdevice_id = subdevice_id;
55 chip->bad_board = TRUE;
56 chip->input_clock_types =
57 ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
58 ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
59 chip->digital_modes =
60 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
61 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
62 ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
63
64 /* Mona comes in both '301 and '361 flavors */
65 if (chip->device_id == DEVICE_ID_56361)
Giuliano Pochini19b50062010-02-14 18:15:34 +010066 chip->dsp_code_to_load = FW_MONA_361_DSP;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +020067 else
Giuliano Pochini19b50062010-02-14 18:15:34 +010068 chip->dsp_code_to_load = FW_MONA_301_DSP;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +020069
Giuliano Pochinidd7b2542006-06-28 13:53:41 +020070 if ((err = load_firmware(chip)) < 0)
71 return err;
72 chip->bad_board = FALSE;
73
Giuliano Pochinidd7b2542006-06-28 13:53:41 +020074 DE_INIT(("init_hw done\n"));
75 return err;
76}
77
78
79
Giuliano Pochiniad3499f2010-02-14 18:15:59 +010080static int set_mixer_defaults(struct echoaudio *chip)
81{
82 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
83 chip->professional_spdif = FALSE;
84 chip->digital_in_automute = TRUE;
85 return init_line_levels(chip);
86}
87
88
89
Giuliano Pochinidd7b2542006-06-28 13:53:41 +020090static u32 detect_input_clocks(const struct echoaudio *chip)
91{
92 u32 clocks_from_dsp, clock_bits;
93
94 /* Map the DSP clock detect bits to the generic driver clock
95 detect bits */
96 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
97
98 clock_bits = ECHO_CLOCK_BIT_INTERNAL;
99
100 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
101 clock_bits |= ECHO_CLOCK_BIT_SPDIF;
102
103 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
104 clock_bits |= ECHO_CLOCK_BIT_ADAT;
105
106 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
107 clock_bits |= ECHO_CLOCK_BIT_WORD;
108
109 return clock_bits;
110}
111
112
113
114/* Mona has an ASIC on the PCI card and another ASIC in the external box;
115both need to be loaded. */
116static int load_asic(struct echoaudio *chip)
117{
118 u32 control_reg;
119 int err;
Giuliano Pochini19b50062010-02-14 18:15:34 +0100120 short asic;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200121
122 if (chip->asic_loaded)
123 return 0;
124
125 mdelay(10);
126
127 if (chip->device_id == DEVICE_ID_56361)
Giuliano Pochini19b50062010-02-14 18:15:34 +0100128 asic = FW_MONA_361_1_ASIC48;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200129 else
Giuliano Pochini19b50062010-02-14 18:15:34 +0100130 asic = FW_MONA_301_1_ASIC48;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200131
132 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
133 if (err < 0)
134 return err;
135
136 chip->asic_code = asic;
137 mdelay(10);
138
139 /* Do the external one */
140 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
Giuliano Pochini19b50062010-02-14 18:15:34 +0100141 FW_MONA_2_ASIC);
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200142 if (err < 0)
143 return err;
144
145 mdelay(10);
146 err = check_asic_status(chip);
147
148 /* Set up the control register if the load succeeded -
149 48 kHz, internal clock, S/PDIF RCA mode */
150 if (!err) {
151 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
152 err = write_control_reg(chip, control_reg, TRUE);
153 }
154
155 return err;
156}
157
158
159
160/* Depending on what digital mode you want, Mona needs different ASICs
161loaded. This function checks the ASIC needed for the new mode and sees
162if it matches the one already loaded. */
163static int switch_asic(struct echoaudio *chip, char double_speed)
164{
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200165 int err;
Giuliano Pochini19b50062010-02-14 18:15:34 +0100166 short asic;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200167
168 /* Check the clock detect bits to see if this is
169 a single-speed clock or a double-speed clock; load
170 a new ASIC if necessary. */
171 if (chip->device_id == DEVICE_ID_56361) {
172 if (double_speed)
Giuliano Pochini19b50062010-02-14 18:15:34 +0100173 asic = FW_MONA_361_1_ASIC96;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200174 else
Giuliano Pochini19b50062010-02-14 18:15:34 +0100175 asic = FW_MONA_361_1_ASIC48;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200176 } else {
177 if (double_speed)
Giuliano Pochini19b50062010-02-14 18:15:34 +0100178 asic = FW_MONA_301_1_ASIC96;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200179 else
Giuliano Pochini19b50062010-02-14 18:15:34 +0100180 asic = FW_MONA_301_1_ASIC48;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200181 }
182
183 if (asic != chip->asic_code) {
184 /* Load the desired ASIC */
185 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
186 asic);
187 if (err < 0)
188 return err;
189 chip->asic_code = asic;
190 }
191
192 return 0;
193}
194
195
196
197static int set_sample_rate(struct echoaudio *chip, u32 rate)
198{
199 u32 control_reg, clock;
Giuliano Pochini19b50062010-02-14 18:15:34 +0100200 short asic;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200201 char force_write;
202
203 /* Only set the clock for internal mode. */
204 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
205 DE_ACT(("set_sample_rate: Cannot set sample rate - "
206 "clock not set to CLK_CLOCKININTERNAL\n"));
207 /* Save the rate anyhow */
208 chip->comm_page->sample_rate = cpu_to_le32(rate);
209 chip->sample_rate = rate;
210 return 0;
211 }
212
213 /* Now, check to see if the required ASIC is loaded */
214 if (rate >= 88200) {
215 if (chip->digital_mode == DIGITAL_MODE_ADAT)
216 return -EINVAL;
217 if (chip->device_id == DEVICE_ID_56361)
Giuliano Pochini19b50062010-02-14 18:15:34 +0100218 asic = FW_MONA_361_1_ASIC96;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200219 else
Giuliano Pochini19b50062010-02-14 18:15:34 +0100220 asic = FW_MONA_301_1_ASIC96;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200221 } else {
222 if (chip->device_id == DEVICE_ID_56361)
Giuliano Pochini19b50062010-02-14 18:15:34 +0100223 asic = FW_MONA_361_1_ASIC48;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200224 else
Giuliano Pochini19b50062010-02-14 18:15:34 +0100225 asic = FW_MONA_301_1_ASIC48;
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200226 }
227
228 force_write = 0;
229 if (asic != chip->asic_code) {
230 int err;
231 /* Load the desired ASIC (load_asic_generic() can sleep) */
232 spin_unlock_irq(&chip->lock);
233 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
234 asic);
235 spin_lock_irq(&chip->lock);
236
237 if (err < 0)
238 return err;
239 chip->asic_code = asic;
240 force_write = 1;
241 }
242
243 /* Compute the new control register value */
244 clock = 0;
245 control_reg = le32_to_cpu(chip->comm_page->control_register);
246 control_reg &= GML_CLOCK_CLEAR_MASK;
247 control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
248
249 switch (rate) {
250 case 96000:
251 clock = GML_96KHZ;
252 break;
253 case 88200:
254 clock = GML_88KHZ;
255 break;
256 case 48000:
257 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
258 break;
259 case 44100:
260 clock = GML_44KHZ;
261 /* Professional mode */
262 if (control_reg & GML_SPDIF_PRO_MODE)
263 clock |= GML_SPDIF_SAMPLE_RATE0;
264 break;
265 case 32000:
266 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
267 GML_SPDIF_SAMPLE_RATE1;
268 break;
269 case 22050:
270 clock = GML_22KHZ;
271 break;
272 case 16000:
273 clock = GML_16KHZ;
274 break;
275 case 11025:
276 clock = GML_11KHZ;
277 break;
278 case 8000:
279 clock = GML_8KHZ;
280 break;
281 default:
282 DE_ACT(("set_sample_rate: %d invalid!\n", rate));
283 return -EINVAL;
284 }
285
286 control_reg |= clock;
287
288 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
289 chip->sample_rate = rate;
290 DE_ACT(("set_sample_rate: %d clock %d\n", rate, clock));
291
292 return write_control_reg(chip, control_reg, force_write);
293}
294
295
296
297static int set_input_clock(struct echoaudio *chip, u16 clock)
298{
299 u32 control_reg, clocks_from_dsp;
300 int err;
301
302 DE_ACT(("set_input_clock:\n"));
303
304 /* Prevent two simultaneous calls to switch_asic() */
305 if (atomic_read(&chip->opencount))
306 return -EAGAIN;
307
308 /* Mask off the clock select bits */
309 control_reg = le32_to_cpu(chip->comm_page->control_register) &
310 GML_CLOCK_CLEAR_MASK;
311 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
312
313 switch (clock) {
314 case ECHO_CLOCK_INTERNAL:
315 DE_ACT(("Set Mona clock to INTERNAL\n"));
316 chip->input_clock = ECHO_CLOCK_INTERNAL;
317 return set_sample_rate(chip, chip->sample_rate);
318 case ECHO_CLOCK_SPDIF:
319 if (chip->digital_mode == DIGITAL_MODE_ADAT)
320 return -EAGAIN;
321 spin_unlock_irq(&chip->lock);
322 err = switch_asic(chip, clocks_from_dsp &
323 GML_CLOCK_DETECT_BIT_SPDIF96);
324 spin_lock_irq(&chip->lock);
325 if (err < 0)
326 return err;
327 DE_ACT(("Set Mona clock to SPDIF\n"));
328 control_reg |= GML_SPDIF_CLOCK;
329 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
330 control_reg |= GML_DOUBLE_SPEED_MODE;
331 else
332 control_reg &= ~GML_DOUBLE_SPEED_MODE;
333 break;
334 case ECHO_CLOCK_WORD:
335 DE_ACT(("Set Mona clock to WORD\n"));
336 spin_unlock_irq(&chip->lock);
337 err = switch_asic(chip, clocks_from_dsp &
338 GML_CLOCK_DETECT_BIT_WORD96);
339 spin_lock_irq(&chip->lock);
340 if (err < 0)
341 return err;
342 control_reg |= GML_WORD_CLOCK;
343 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
344 control_reg |= GML_DOUBLE_SPEED_MODE;
345 else
346 control_reg &= ~GML_DOUBLE_SPEED_MODE;
347 break;
348 case ECHO_CLOCK_ADAT:
349 DE_ACT(("Set Mona clock to ADAT\n"));
350 if (chip->digital_mode != DIGITAL_MODE_ADAT)
351 return -EAGAIN;
352 control_reg |= GML_ADAT_CLOCK;
353 control_reg &= ~GML_DOUBLE_SPEED_MODE;
354 break;
355 default:
356 DE_ACT(("Input clock 0x%x not supported for Mona\n", clock));
357 return -EINVAL;
358 }
359
360 chip->input_clock = clock;
361 return write_control_reg(chip, control_reg, TRUE);
362}
363
364
365
366static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
367{
368 u32 control_reg;
369 int err, incompatible_clock;
370
371 /* Set clock to "internal" if it's not compatible with the new mode */
372 incompatible_clock = FALSE;
373 switch (mode) {
374 case DIGITAL_MODE_SPDIF_OPTICAL:
375 case DIGITAL_MODE_SPDIF_RCA:
376 if (chip->input_clock == ECHO_CLOCK_ADAT)
377 incompatible_clock = TRUE;
378 break;
379 case DIGITAL_MODE_ADAT:
380 if (chip->input_clock == ECHO_CLOCK_SPDIF)
381 incompatible_clock = TRUE;
382 break;
383 default:
384 DE_ACT(("Digital mode not supported: %d\n", mode));
385 return -EINVAL;
386 }
387
388 spin_lock_irq(&chip->lock);
389
390 if (incompatible_clock) { /* Switch to 48KHz, internal */
391 chip->sample_rate = 48000;
392 set_input_clock(chip, ECHO_CLOCK_INTERNAL);
393 }
394
395 /* Clear the current digital mode */
396 control_reg = le32_to_cpu(chip->comm_page->control_register);
397 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
398
399 /* Tweak the control reg */
400 switch (mode) {
401 case DIGITAL_MODE_SPDIF_OPTICAL:
402 control_reg |= GML_SPDIF_OPTICAL_MODE;
403 break;
404 case DIGITAL_MODE_SPDIF_RCA:
405 /* GML_SPDIF_OPTICAL_MODE bit cleared */
406 break;
407 case DIGITAL_MODE_ADAT:
408 /* If the current ASIC is the 96KHz ASIC, switch the ASIC
409 and set to 48 KHz */
Giuliano Pochini19b50062010-02-14 18:15:34 +0100410 if (chip->asic_code == FW_MONA_361_1_ASIC96 ||
411 chip->asic_code == FW_MONA_301_1_ASIC96) {
Giuliano Pochinidd7b2542006-06-28 13:53:41 +0200412 set_sample_rate(chip, 48000);
413 }
414 control_reg |= GML_ADAT_MODE;
415 control_reg &= ~GML_DOUBLE_SPEED_MODE;
416 break;
417 }
418
419 err = write_control_reg(chip, control_reg, FALSE);
420 spin_unlock_irq(&chip->lock);
421 if (err < 0)
422 return err;
423 chip->digital_mode = mode;
424
425 DE_ACT(("set_digital_mode to %d\n", mode));
426 return incompatible_clock;
427}