blob: e1f27d653f603d17413b04aa0e9f540f10cf504a [file] [log] [blame]
Maxime Bizone7300d02009-08-18 13:23:37 +01001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */
8
9#include <linux/init.h>
10#include <linux/bootmem.h>
Kevin Cernekeea068dde2013-06-18 08:34:31 +000011#include <linux/smp.h>
Maxime Bizone7300d02009-08-18 13:23:37 +010012#include <asm/bootinfo.h>
Kevin Cernekeea068dde2013-06-18 08:34:31 +000013#include <asm/bmips.h>
14#include <asm/smp-ops.h>
15#include <asm/mipsregs.h>
Maxime Bizone7300d02009-08-18 13:23:37 +010016#include <bcm63xx_board.h>
17#include <bcm63xx_cpu.h>
18#include <bcm63xx_io.h>
19#include <bcm63xx_regs.h>
20#include <bcm63xx_gpio.h>
21
22void __init prom_init(void)
23{
24 u32 reg, mask;
25
26 bcm63xx_cpu_init();
27
28 /* stop any running watchdog */
29 bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
30 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
31
32 /* disable all hardware blocks clock for now */
Florian Fainelli7b933422013-06-18 16:55:40 +000033 if (BCMCPU_IS_3368())
34 mask = CKCTL_3368_ALL_SAFE_EN;
35 else if (BCMCPU_IS_6328())
Jonas Gorskie5766ae2012-07-24 16:33:12 +020036 mask = CKCTL_6328_ALL_SAFE_EN;
37 else if (BCMCPU_IS_6338())
Maxime Bizone7300d02009-08-18 13:23:37 +010038 mask = CKCTL_6338_ALL_SAFE_EN;
39 else if (BCMCPU_IS_6345())
40 mask = CKCTL_6345_ALL_SAFE_EN;
41 else if (BCMCPU_IS_6348())
42 mask = CKCTL_6348_ALL_SAFE_EN;
Maxime Bizon04712f32011-11-04 19:09:35 +010043 else if (BCMCPU_IS_6358())
Maxime Bizone7300d02009-08-18 13:23:37 +010044 mask = CKCTL_6358_ALL_SAFE_EN;
Jonas Gorski2c8aaf72013-03-21 14:03:17 +000045 else if (BCMCPU_IS_6362())
46 mask = CKCTL_6362_ALL_SAFE_EN;
Maxime Bizon04712f32011-11-04 19:09:35 +010047 else if (BCMCPU_IS_6368())
48 mask = CKCTL_6368_ALL_SAFE_EN;
49 else
50 mask = 0;
Maxime Bizone7300d02009-08-18 13:23:37 +010051
52 reg = bcm_perf_readl(PERF_CKCTL_REG);
53 reg &= ~mask;
54 bcm_perf_writel(reg, PERF_CKCTL_REG);
55
Maxime Bizone7300d02009-08-18 13:23:37 +010056 /* register gpiochip */
57 bcm63xx_gpio_init();
58
59 /* do low level board init */
60 board_prom_init();
Kevin Cernekeea068dde2013-06-18 08:34:31 +000061
Jonas Gorski10102692013-12-18 14:12:07 +010062 /* set up SMP */
63 if (!register_bmips_smp_ops()) {
Kevin Cernekeea068dde2013-06-18 08:34:31 +000064 /*
Jonas Gorski0e983d72013-12-18 14:11:59 +010065 * BCM6328 might not have its second CPU enabled, while BCM3368
66 * and BCM6358 need special handling for their shared TLB, so
67 * disable SMP for now.
Kevin Cernekeea068dde2013-06-18 08:34:31 +000068 */
69 if (BCMCPU_IS_6328()) {
Jonas Gorski7ac836c2013-06-18 08:34:32 +000070 reg = bcm_readl(BCM_6328_OTP_BASE +
71 OTP_USER_BITS_6328_REG(3));
72
73 if (reg & OTP_6328_REG3_TP1_DISABLED)
74 bmips_smp_enabled = 0;
Jonas Gorski0e983d72013-12-18 14:11:59 +010075 } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
Kevin Cernekeea068dde2013-06-18 08:34:31 +000076 bmips_smp_enabled = 0;
77 }
78
79 if (!bmips_smp_enabled)
80 return;
81
82 /*
83 * The bootloader has set up the CPU1 reset vector at
84 * 0xa000_0200.
85 * This conflicts with the special interrupt vector (IV).
86 * The bootloader has also set up CPU1 to respond to the wrong
87 * IPI interrupt.
88 * Here we will start up CPU1 in the background and ask it to
89 * reconfigure itself then go back to sleep.
90 */
91 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
92 __sync();
93 set_c0_cause(C_SW0);
94 cpumask_set_cpu(1, &bmips_booted_mask);
95
96 /*
97 * FIXME: we really should have some sort of hazard barrier here
98 */
99 }
Maxime Bizone7300d02009-08-18 13:23:37 +0100100}
101
102void __init prom_free_prom_memory(void)
103{
104}