| Arnaldo Carvalho de Melo | e43a19c | 2015-05-06 18:35:20 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copied from the kernel sources: |
| 3 | * |
| 4 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> |
| 5 | */ |
| 6 | #ifndef _TOOLS_LINUX_ASM_POWERPC_BARRIER_H |
| 7 | #define _TOOLS_LINUX_ASM_POWERPC_BARRIER_H |
| 8 | |
| 9 | /* |
| 10 | * Memory barrier. |
| 11 | * The sync instruction guarantees that all memory accesses initiated |
| 12 | * by this processor have been performed (with respect to all other |
| 13 | * mechanisms that access memory). The eieio instruction is a barrier |
| 14 | * providing an ordering (separately) for (a) cacheable stores and (b) |
| 15 | * loads and stores to non-cacheable memory (e.g. I/O devices). |
| 16 | * |
| 17 | * mb() prevents loads and stores being reordered across this point. |
| 18 | * rmb() prevents loads being reordered across this point. |
| 19 | * wmb() prevents stores being reordered across this point. |
| 20 | * |
| 21 | * *mb() variants without smp_ prefix must order all types of memory |
| 22 | * operations with one another. sync is the only instruction sufficient |
| 23 | * to do this. |
| 24 | */ |
| 25 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") |
| 26 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") |
| 27 | #define wmb() __asm__ __volatile__ ("sync" : : : "memory") |
| 28 | |
| 29 | #endif /* _TOOLS_LINUX_ASM_POWERPC_BARRIER_H */ |