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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Digi RightSwitch SE-X loadable device driver for Linux
3 *
4 * The RightSwitch is a 4 (EISA) or 6 (PCI) port etherswitch and
5 * a NIC on an internal board.
6 *
7 * Author: Rick Richardson, rick@remotepoint.com
8 * Derived from the SVR4.2 (UnixWare) driver for the same card.
9 *
10 * Copyright 1995-1996 Digi International Inc.
11 *
12 * This software may be used and distributed according to the terms
13 * of the GNU General Public License, incorporated herein by reference.
14 *
15 * For information on purchasing a RightSwitch SE-4 or SE-6
16 * board, please contact Digi's sales department at 1-612-912-3444
17 * or 1-800-DIGIBRD. Outside the U.S., please check our Web page
18 * at http://www.dgii.com for sales offices worldwide.
19 *
20 * OPERATION:
21 * When compiled as a loadable module, this driver can operate
22 * the board as either a 4/6 port switch with a 5th or 7th port
23 * that is a conventional NIC interface as far as the host is
24 * concerned, OR as 4/6 independent NICs. To select multi-NIC
25 * mode, add "nicmode=1" on the insmod load line for the driver.
26 *
27 * This driver uses the "dev" common ethernet device structure
28 * and a private "priv" (dev->priv) structure that contains
29 * mostly DGRS-specific information and statistics. To keep
30 * the code for both the switch mode and the multi-NIC mode
31 * as similar as possible, I have introduced the concept of
32 * "dev0"/"priv0" and "devN"/"privN" pointer pairs in subroutines
33 * where needed. The first pair of pointers points to the
34 * "dev" and "priv" structures of the zeroth (0th) device
35 * interface associated with a board. The second pair of
36 * pointers points to the current (Nth) device interface
37 * for the board: the one for which we are processing data.
38 *
39 * In switch mode, the pairs of pointers are always the same,
40 * that is, dev0 == devN and priv0 == privN. This is just
41 * like previous releases of this driver which did not support
42 * NIC mode.
43 *
44 * In multi-NIC mode, the pairs of pointers may be different.
45 * We use the devN and privN pointers to reference just the
46 * name, port number, and statistics for the current interface.
47 * We use the dev0 and priv0 pointers to access the variables
48 * that control access to the board, such as board address
49 * and simulated 82596 variables. This is because there is
50 * only one "fake" 82596 that serves as the interface to
51 * the board. We do not want to try to keep the variables
52 * associated with this 82596 in sync across all devices.
53 *
54 * This scheme works well. As you will see, except for
55 * initialization, there is very little difference between
56 * the two modes as far as this driver is concerned. On the
57 * receive side in NIC mode, the interrupt *always* comes in on
58 * the 0th interface (dev0/priv0). We then figure out which
59 * real 82596 port it came in on from looking at the "chan"
60 * member that the board firmware adds at the end of each
61 * RBD (a.k.a. TBD). We get the channel number like this:
62 * int chan = ((I596_RBD *) S2H(cbp->xmit.tbdp))->chan;
63 *
64 * On the transmit side in multi-NIC mode, we specify the
65 * output 82596 port by setting the new "dstchan" structure
66 * member that is at the end of the RFD, like this:
67 * priv0->rfdp->dstchan = privN->chan;
68 *
69 * TODO:
70 * - Multi-NIC mode is not yet supported when the driver is linked
71 * into the kernel.
72 * - Better handling of multicast addresses.
73 *
74 * Fixes:
75 * Arnaldo Carvalho de Melo <acme@conectiva.com.br> - 11/01/2001
76 * - fix dgrs_found_device wrt checking kmalloc return and
77 * rollbacking the partial steps of the whole process when
78 * one of the devices can't be allocated. Fix SET_MODULE_OWNER
79 * on the loop to use devN instead of repeated calls to dev.
80 *
81 * davej <davej@suse.de> - 9/2/2001
82 * - Enable PCI device before reading ioaddr/irq
83 *
84 */
85
86#include <linux/module.h>
87#include <linux/eisa.h>
88#include <linux/kernel.h>
89#include <linux/string.h>
90#include <linux/delay.h>
91#include <linux/errno.h>
92#include <linux/ioport.h>
93#include <linux/slab.h>
94#include <linux/interrupt.h>
95#include <linux/pci.h>
96#include <linux/init.h>
97#include <linux/netdevice.h>
98#include <linux/etherdevice.h>
99#include <linux/skbuff.h>
100#include <linux/bitops.h>
101
102#include <asm/io.h>
103#include <asm/byteorder.h>
104#include <asm/uaccess.h>
105
106static char version[] __initdata =
107 "$Id: dgrs.c,v 1.13 2000/06/06 04:07:00 rick Exp $";
108
109/*
110 * DGRS include files
111 */
112typedef unsigned char uchar;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113#define vol volatile
114
115#include "dgrs.h"
116#include "dgrs_es4h.h"
117#include "dgrs_plx9060.h"
118#include "dgrs_i82596.h"
119#include "dgrs_ether.h"
120#include "dgrs_asstruct.h"
121#include "dgrs_bcomm.h"
122
123#ifdef CONFIG_PCI
124static struct pci_device_id dgrs_pci_tbl[] = {
125 { SE6_PCI_VENDOR_ID, SE6_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, },
126 { } /* Terminating entry */
127};
128MODULE_DEVICE_TABLE(pci, dgrs_pci_tbl);
129#endif
130
131#ifdef CONFIG_EISA
132static struct eisa_device_id dgrs_eisa_tbl[] = {
133 { "DBI0A01" },
134 { }
135};
136MODULE_DEVICE_TABLE(eisa, dgrs_eisa_tbl);
137#endif
138
139MODULE_LICENSE("GPL");
140
141
142/*
143 * Firmware. Compiled separately for local compilation,
144 * but #included for Linux distribution.
145 */
146#ifndef NOFW
147 #include "dgrs_firmware.c"
148#else
149 extern int dgrs_firmnum;
150 extern char dgrs_firmver[];
151 extern char dgrs_firmdate[];
152 extern uchar dgrs_code[];
153 extern int dgrs_ncode;
154#endif
155
156/*
157 * Linux out*() is backwards from all other operating systems
158 */
159#define OUTB(ADDR, VAL) outb(VAL, ADDR)
160#define OUTW(ADDR, VAL) outw(VAL, ADDR)
161#define OUTL(ADDR, VAL) outl(VAL, ADDR)
162
163/*
164 * Macros to convert switch to host and host to switch addresses
165 * (assumes a local variable priv points to board dependent struct)
166 */
167#define S2H(A) ( ((unsigned long)(A)&0x00ffffff) + priv0->vmem )
168#define S2HN(A) ( ((unsigned long)(A)&0x00ffffff) + privN->vmem )
169#define H2S(A) ( ((char *) (A) - priv0->vmem) + 0xA3000000 )
170
171/*
172 * Convert a switch address to a "safe" address for use with the
173 * PLX 9060 DMA registers and the associated HW kludge that allows
174 * for host access of the DMA registers.
175 */
176#define S2DMA(A) ( (unsigned long)(A) & 0x00ffffff)
177
178/*
179 * "Space.c" variables, now settable from module interface
180 * Use the name below, minus the "dgrs_" prefix. See init_module().
181 */
182static int dgrs_debug = 1;
183static int dgrs_dma = 1;
184static int dgrs_spantree = -1;
185static int dgrs_hashexpire = -1;
186static uchar dgrs_ipaddr[4] = { 0xff, 0xff, 0xff, 0xff};
187static uchar dgrs_iptrap[4] = { 0xff, 0xff, 0xff, 0xff};
188static __u32 dgrs_ipxnet = -1;
189static int dgrs_nicmode;
190
191/*
192 * Private per-board data structure (dev->priv)
193 */
194typedef struct
195{
196 /*
197 * Stuff for generic ethercard I/F
198 */
199 struct net_device_stats stats;
200
201 /*
202 * DGRS specific data
203 */
204 char *vmem;
205
206 struct bios_comm *bcomm; /* Firmware BIOS comm structure */
207 PORT *port; /* Ptr to PORT[0] struct in VM */
208 I596_SCB *scbp; /* Ptr to SCB struct in VM */
209 I596_RFD *rfdp; /* Current RFD list */
210 I596_RBD *rbdp; /* Current RBD list */
211
212 volatile int intrcnt; /* Count of interrupts */
213
214 /*
215 * SE-4 (EISA) board variables
216 */
217 uchar is_reg; /* EISA: Value for ES4H_IS reg */
218
219 /*
220 * SE-6 (PCI) board variables
221 *
222 * The PLX "expansion rom" space is used for DMA register
223 * access from the host on the SE-6. These are the physical
224 * and virtual addresses of that space.
225 */
226 ulong plxreg; /* Phys address of PLX chip */
227 char *vplxreg; /* Virtual address of PLX chip */
228 ulong plxdma; /* Phys addr of PLX "expansion rom" */
229 ulong volatile *vplxdma; /* Virtual addr of "expansion rom" */
230 int use_dma; /* Flag: use DMA */
231 DMACHAIN *dmadesc_s; /* area for DMA chains (SW addr.) */
232 DMACHAIN *dmadesc_h; /* area for DMA chains (Host Virtual) */
233
234 /*
235 * Multi-NIC mode variables
236 *
237 * All entries of the devtbl[] array are valid for the 0th
238 * device (i.e. eth0, but not eth1...eth5). devtbl[0] is
239 * valid for all devices (i.e. eth0, eth1, ..., eth5).
240 */
241 int nports; /* Number of physical ports (4 or 6) */
242 int chan; /* Channel # (1-6) for this device */
243 struct net_device *devtbl[6]; /* Ptrs to N device structs */
244
245} DGRS_PRIV;
246
247
248/*
249 * reset or un-reset the IDT processor
250 */
251static void
252proc_reset(struct net_device *dev0, int reset)
253{
254 DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
255
256 if (priv0->plxreg)
257 {
258 ulong val;
259 val = inl(dev0->base_addr + PLX_MISC_CSR);
260 if (reset)
261 val |= SE6_RESET;
262 else
263 val &= ~SE6_RESET;
264 OUTL(dev0->base_addr + PLX_MISC_CSR, val);
265 }
266 else
267 {
268 OUTB(dev0->base_addr + ES4H_PC, reset ? ES4H_PC_RESET : 0);
269 }
270}
271
272/*
273 * See if the board supports bus master DMA
274 */
275static int
276check_board_dma(struct net_device *dev0)
277{
278 DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
279 ulong x;
280
281 /*
282 * If Space.c says not to use DMA, or if it's not a PLX based
283 * PCI board, or if the expansion ROM space is not PCI
284 * configured, then return false.
285 */
286 if (!dgrs_dma || !priv0->plxreg || !priv0->plxdma)
287 return (0);
288
289 /*
290 * Set the local address remap register of the "expansion rom"
291 * area to 0x80000000 so that we can use it to access the DMA
292 * registers from the host side.
293 */
294 OUTL(dev0->base_addr + PLX_ROM_BASE_ADDR, 0x80000000);
295
296 /*
297 * Set the PCI region descriptor to:
298 * Space 0:
299 * disable read-prefetch
300 * enable READY
301 * enable BURST
302 * 0 internal wait states
303 * Expansion ROM: (used for host DMA register access)
304 * disable read-prefetch
305 * enable READY
306 * disable BURST
307 * 0 internal wait states
308 */
309 OUTL(dev0->base_addr + PLX_BUS_REGION, 0x49430343);
310
311 /*
312 * Now map the DMA registers into our virtual space
313 */
314 priv0->vplxdma = (ulong *) ioremap (priv0->plxdma, 256);
315 if (!priv0->vplxdma)
316 {
317 printk("%s: can't *remap() the DMA regs\n", dev0->name);
318 return (0);
319 }
320
321 /*
322 * Now test to see if we can access the DMA registers
323 * If we write -1 and get back 1FFF, then we accessed the
324 * DMA register. Otherwise, we probably have an old board
325 * and wrote into regular RAM.
326 */
327 priv0->vplxdma[PLX_DMA0_MODE/4] = 0xFFFFFFFF;
328 x = priv0->vplxdma[PLX_DMA0_MODE/4];
329 if (x != 0x00001FFF) {
330 iounmap((void *)priv0->vplxdma);
331 return (0);
332 }
333
334 return (1);
335}
336
337/*
338 * Initiate DMA using PLX part on PCI board. Spin the
339 * processor until completed. All addresses are physical!
340 *
341 * If pciaddr is NULL, then it's a chaining DMA, and lcladdr is
342 * the address of the first DMA descriptor in the chain.
343 *
344 * If pciaddr is not NULL, then it's a single DMA.
345 *
346 * In either case, "lcladdr" must have been fixed up to make
347 * sure the MSB isn't set using the S2DMA macro before passing
348 * the address to this routine.
349 */
350static int
351do_plx_dma(
352 struct net_device *dev,
353 ulong pciaddr,
354 ulong lcladdr,
355 int len,
356 int to_host
357)
358{
359 int i;
360 ulong csr = 0;
361 DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
362
363 if (pciaddr)
364 {
365 /*
366 * Do a single, non-chain DMA
367 */
368 priv->vplxdma[PLX_DMA0_PCI_ADDR/4] = pciaddr;
369 priv->vplxdma[PLX_DMA0_LCL_ADDR/4] = lcladdr;
370 priv->vplxdma[PLX_DMA0_SIZE/4] = len;
371 priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = to_host
372 ? PLX_DMA_DESC_TO_HOST
373 : PLX_DMA_DESC_TO_BOARD;
374 priv->vplxdma[PLX_DMA0_MODE/4] =
375 PLX_DMA_MODE_WIDTH32
376 | PLX_DMA_MODE_WAITSTATES(0)
377 | PLX_DMA_MODE_READY
378 | PLX_DMA_MODE_NOBTERM
379 | PLX_DMA_MODE_BURST
380 | PLX_DMA_MODE_NOCHAIN;
381 }
382 else
383 {
384 /*
385 * Do a chaining DMA
386 */
387 priv->vplxdma[PLX_DMA0_MODE/4] =
388 PLX_DMA_MODE_WIDTH32
389 | PLX_DMA_MODE_WAITSTATES(0)
390 | PLX_DMA_MODE_READY
391 | PLX_DMA_MODE_NOBTERM
392 | PLX_DMA_MODE_BURST
393 | PLX_DMA_MODE_CHAIN;
394 priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = lcladdr;
395 }
396
397 priv->vplxdma[PLX_DMA_CSR/4] =
398 PLX_DMA_CSR_0_ENABLE | PLX_DMA_CSR_0_START;
399
400 /*
401 * Wait for DMA to complete
402 */
403 for (i = 0; i < 1000000; ++i)
404 {
405 /*
406 * Spin the host CPU for 1 usec, so we don't thrash
407 * the PCI bus while the PLX 9060 is doing DMA.
408 */
409 udelay(1);
410
411 csr = (volatile unsigned long) priv->vplxdma[PLX_DMA_CSR/4];
412
413 if (csr & PLX_DMA_CSR_0_DONE)
414 break;
415 }
416
417 if ( ! (csr & PLX_DMA_CSR_0_DONE) )
418 {
419 printk("%s: DMA done never occurred. DMA disabled.\n",
420 dev->name);
421 priv->use_dma = 0;
422 return 1;
423 }
424 return 0;
425}
426
427/*
428 * dgrs_rcv_frame()
429 *
430 * Process a received frame. This is called from the interrupt
431 * routine, and works for both switch mode and multi-NIC mode.
432 *
433 * Note that when in multi-NIC mode, we want to always access the
434 * hardware using the dev and priv structures of the first port,
435 * so that we are using only one set of variables to maintain
436 * the board interface status, but we want to use the Nth port
437 * dev and priv structures to maintain statistics and to pass
438 * the packet up.
439 *
440 * Only the first device structure is attached to the interrupt.
441 * We use the special "chan" variable at the end of the first RBD
442 * to select the Nth device in multi-NIC mode.
443 *
444 * We currently do chained DMA on a per-packet basis when the
445 * packet is "long", and we spin the CPU a short time polling
446 * for DMA completion. This avoids a second interrupt overhead,
447 * and gives the best performance for light traffic to the host.
448 *
449 * However, a better scheme that could be implemented would be
450 * to see how many packets are outstanding for the host, and if
451 * the number is "large", create a long chain to DMA several
452 * packets into the host in one go. In this case, we would set
453 * up some state variables to let the host CPU continue doing
454 * other things until a DMA completion interrupt comes along.
455 */
456static void
457dgrs_rcv_frame(
458 struct net_device *dev0,
459 DGRS_PRIV *priv0,
460 I596_CB *cbp
461)
462{
463 int len;
464 I596_TBD *tbdp;
465 struct sk_buff *skb;
466 uchar *putp;
467 uchar *p;
468 struct net_device *devN;
469 DGRS_PRIV *privN;
470
471 /*
472 * Determine Nth priv and dev structure pointers
473 */
474 if (dgrs_nicmode)
475 { /* Multi-NIC mode */
476 int chan = ((I596_RBD *) S2H(cbp->xmit.tbdp))->chan;
477
478 devN = priv0->devtbl[chan-1];
479 /*
480 * If devN is null, we got an interrupt before the I/F
481 * has been initialized. Pitch the packet.
482 */
483 if (devN == NULL)
484 goto out;
485 privN = (DGRS_PRIV *) devN->priv;
486 }
487 else
488 { /* Switch mode */
489 devN = dev0;
490 privN = priv0;
491 }
492
493 if (0) printk("%s: rcv len=%ld\n", devN->name, cbp->xmit.count);
494
495 /*
496 * Allocate a message block big enough to hold the whole frame
497 */
498 len = cbp->xmit.count;
499 if ((skb = dev_alloc_skb(len+5)) == NULL)
500 {
501 printk("%s: dev_alloc_skb failed for rcv buffer\n", devN->name);
502 ++privN->stats.rx_dropped;
503 /* discarding the frame */
504 goto out;
505 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 skb_reserve(skb, 2); /* Align IP header */
507
508again:
509 putp = p = skb_put(skb, len);
510
511 /*
512 * There are three modes here for doing the packet copy.
513 * If we have DMA, and the packet is "long", we use the
514 * chaining mode of DMA. If it's shorter, we use single
515 * DMA's. Otherwise, we use memcpy().
516 */
517 if (priv0->use_dma && priv0->dmadesc_h && len > 64)
518 {
519 /*
520 * If we can use DMA and it's a long frame, copy it using
521 * DMA chaining.
522 */
523 DMACHAIN *ddp_h; /* Host virtual DMA desc. pointer */
524 DMACHAIN *ddp_s; /* Switch physical DMA desc. pointer */
525 uchar *phys_p;
526
527 /*
528 * Get the physical address of the STREAMS buffer.
529 * NOTE: allocb() guarantees that the whole buffer
530 * is in a single page if the length < 4096.
531 */
532 phys_p = (uchar *) virt_to_phys(putp);
533
534 ddp_h = priv0->dmadesc_h;
535 ddp_s = priv0->dmadesc_s;
536 tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
537 for (;;)
538 {
539 int count;
540 int amt;
541
542 count = tbdp->count;
543 amt = count & 0x3fff;
544 if (amt == 0)
545 break; /* For safety */
546 if ( (p-putp) >= len)
547 {
548 printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
549 proc_reset(dev0, 1); /* Freeze IDT */
550 break; /* For Safety */
551 }
552
553 ddp_h->pciaddr = (ulong) phys_p;
554 ddp_h->lcladdr = S2DMA(tbdp->buf);
555 ddp_h->len = amt;
556
557 phys_p += amt;
558 p += amt;
559
560 if (count & I596_TBD_EOF)
561 {
562 ddp_h->next = PLX_DMA_DESC_TO_HOST
563 | PLX_DMA_DESC_EOC;
564 ++ddp_h;
565 break;
566 }
567 else
568 {
569 ++ddp_s;
570 ddp_h->next = PLX_DMA_DESC_TO_HOST
571 | (ulong) ddp_s;
572 tbdp = (I596_TBD *) S2H(tbdp->next);
573 ++ddp_h;
574 }
575 }
576 if (ddp_h - priv0->dmadesc_h)
577 {
578 int rc;
579
580 rc = do_plx_dma(dev0,
581 0, (ulong) priv0->dmadesc_s, len, 0);
582 if (rc)
583 {
584 printk("%s: Chained DMA failure\n", devN->name);
585 goto again;
586 }
587 }
588 }
589 else if (priv0->use_dma)
590 {
591 /*
592 * If we can use DMA and it's a shorter frame, copy it
593 * using single DMA transfers.
594 */
595 uchar *phys_p;
596
597 /*
598 * Get the physical address of the STREAMS buffer.
599 * NOTE: allocb() guarantees that the whole buffer
600 * is in a single page if the length < 4096.
601 */
602 phys_p = (uchar *) virt_to_phys(putp);
603
604 tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
605 for (;;)
606 {
607 int count;
608 int amt;
609 int rc;
610
611 count = tbdp->count;
612 amt = count & 0x3fff;
613 if (amt == 0)
614 break; /* For safety */
615 if ( (p-putp) >= len)
616 {
617 printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
618 proc_reset(dev0, 1); /* Freeze IDT */
619 break; /* For Safety */
620 }
621 rc = do_plx_dma(dev0, (ulong) phys_p,
622 S2DMA(tbdp->buf), amt, 1);
623 if (rc)
624 {
625 memcpy(p, S2H(tbdp->buf), amt);
626 printk("%s: Single DMA failed\n", devN->name);
627 }
628 phys_p += amt;
629 p += amt;
630 if (count & I596_TBD_EOF)
631 break;
632 tbdp = (I596_TBD *) S2H(tbdp->next);
633 }
634 }
635 else
636 {
637 /*
638 * Otherwise, copy it piece by piece using memcpy()
639 */
640 tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
641 for (;;)
642 {
643 int count;
644 int amt;
645
646 count = tbdp->count;
647 amt = count & 0x3fff;
648 if (amt == 0)
649 break; /* For safety */
650 if ( (p-putp) >= len)
651 {
652 printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
653 proc_reset(dev0, 1); /* Freeze IDT */
654 break; /* For Safety */
655 }
656 memcpy(p, S2H(tbdp->buf), amt);
657 p += amt;
658 if (count & I596_TBD_EOF)
659 break;
660 tbdp = (I596_TBD *) S2H(tbdp->next);
661 }
662 }
663
664 /*
665 * Pass the frame to upper half
666 */
667 skb->protocol = eth_type_trans(skb, devN);
668 netif_rx(skb);
669 devN->last_rx = jiffies;
670 ++privN->stats.rx_packets;
671 privN->stats.rx_bytes += len;
672
673out:
674 cbp->xmit.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
675}
676
677/*
678 * Start transmission of a frame
679 *
680 * The interface to the board is simple: we pretend that we are
681 * a fifth 82596 ethernet controller 'receiving' data, and copy the
682 * data into the same structures that a real 82596 would. This way,
683 * the board firmware handles the host 'port' the same as any other.
684 *
685 * NOTE: we do not use Bus master DMA for this routine. Turns out
686 * that it is not needed. Slave writes over the PCI bus are about
687 * as fast as DMA, due to the fact that the PLX part can do burst
688 * writes. The same is not true for data being read from the board.
689 *
690 * For multi-NIC mode, we tell the firmware the desired 82596
691 * output port by setting the special "dstchan" member at the
692 * end of the traditional 82596 RFD structure.
693 */
694
695static int dgrs_start_xmit(struct sk_buff *skb, struct net_device *devN)
696{
697 DGRS_PRIV *privN = (DGRS_PRIV *) devN->priv;
698 struct net_device *dev0;
699 DGRS_PRIV *priv0;
700 I596_RBD *rbdp;
701 int count;
702 int i, len, amt;
703
704 /*
705 * Determine 0th priv and dev structure pointers
706 */
707 if (dgrs_nicmode)
708 {
709 dev0 = privN->devtbl[0];
710 priv0 = (DGRS_PRIV *) dev0->priv;
711 }
712 else
713 {
714 dev0 = devN;
715 priv0 = privN;
716 }
717
718 if (dgrs_debug > 1)
719 printk("%s: xmit len=%d\n", devN->name, (int) skb->len);
720
721 devN->trans_start = jiffies;
722 netif_start_queue(devN);
723
724 if (priv0->rfdp->cmd & I596_RFD_EL)
725 { /* Out of RFD's */
726 if (0) printk("%s: NO RFD's\n", devN->name);
727 goto no_resources;
728 }
729
730 rbdp = priv0->rbdp;
731 count = 0;
732 priv0->rfdp->rbdp = (I596_RBD *) H2S(rbdp);
733
734 i = 0; len = skb->len;
735 for (;;)
736 {
737 if (rbdp->size & I596_RBD_EL)
738 { /* Out of RBD's */
739 if (0) printk("%s: NO RBD's\n", devN->name);
740 goto no_resources;
741 }
742
743 amt = min_t(unsigned int, len, rbdp->size - count);
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -0300744 skb_copy_from_linear_data_offset(skb, i, S2H(rbdp->buf) + count, amt);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 i += amt;
746 count += amt;
747 len -= amt;
748 if (len == 0)
749 {
750 if (skb->len < 60)
751 rbdp->count = 60 | I596_RBD_EOF;
752 else
753 rbdp->count = count | I596_RBD_EOF;
754 rbdp = (I596_RBD *) S2H(rbdp->next);
755 goto frame_done;
756 }
757 else if (count < 32)
758 {
759 /* More data to come, but we used less than 32
760 * bytes of this RBD. Keep filling this RBD.
761 */
762 {} /* Yes, we do nothing here */
763 }
764 else
765 {
766 rbdp->count = count;
767 rbdp = (I596_RBD *) S2H(rbdp->next);
768 count = 0;
769 }
770 }
771
772frame_done:
773 priv0->rbdp = rbdp;
774 if (dgrs_nicmode)
775 priv0->rfdp->dstchan = privN->chan;
776 priv0->rfdp->status = I596_RFD_C | I596_RFD_OK;
777 priv0->rfdp = (I596_RFD *) S2H(priv0->rfdp->next);
778
779 ++privN->stats.tx_packets;
780
781 dev_kfree_skb (skb);
782 return (0);
783
784no_resources:
785 priv0->scbp->status |= I596_SCB_RNR; /* simulate I82596 */
786 return (-EAGAIN);
787}
788
789/*
790 * Open the interface
791 */
792static int
793dgrs_open( struct net_device *dev )
794{
795 netif_start_queue(dev);
796 return (0);
797}
798
799/*
800 * Close the interface
801 */
802static int dgrs_close( struct net_device *dev )
803{
804 netif_stop_queue(dev);
805 return (0);
806}
807
808/*
809 * Get statistics
810 */
811static struct net_device_stats *dgrs_get_stats( struct net_device *dev )
812{
813 DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
814
815 return (&priv->stats);
816}
817
818/*
819 * Set multicast list and/or promiscuous mode
820 */
821
822static void dgrs_set_multicast_list( struct net_device *dev)
823{
824 DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
825
826 priv->port->is_promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
827}
828
829/*
830 * Unique ioctl's
831 */
832static int dgrs_ioctl(struct net_device *devN, struct ifreq *ifr, int cmd)
833{
834 DGRS_PRIV *privN = (DGRS_PRIV *) devN->priv;
835 DGRS_IOCTL ioc;
836 int i;
837
838 if (cmd != DGRSIOCTL)
839 return -EINVAL;
840
841 if(copy_from_user(&ioc, ifr->ifr_data, sizeof(DGRS_IOCTL)))
842 return -EFAULT;
843
844 switch (ioc.cmd)
845 {
846 case DGRS_GETMEM:
847 if (ioc.len != sizeof(ulong))
848 return -EINVAL;
849 if(copy_to_user(ioc.data, &devN->mem_start, ioc.len))
850 return -EFAULT;
851 return (0);
852 case DGRS_SETFILTER:
853 if (!capable(CAP_NET_ADMIN))
854 return -EPERM;
855 if (ioc.port > privN->bcomm->bc_nports)
856 return -EINVAL;
857 if (ioc.filter >= NFILTERS)
858 return -EINVAL;
859 if (ioc.len > privN->bcomm->bc_filter_area_len)
860 return -EINVAL;
861
862 /* Wait for old command to finish */
863 for (i = 0; i < 1000; ++i)
864 {
865 if ( (volatile long) privN->bcomm->bc_filter_cmd <= 0 )
866 break;
867 udelay(1);
868 }
869 if (i >= 1000)
870 return -EIO;
871
872 privN->bcomm->bc_filter_port = ioc.port;
873 privN->bcomm->bc_filter_num = ioc.filter;
874 privN->bcomm->bc_filter_len = ioc.len;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400875
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 if (ioc.len)
877 {
878 if(copy_from_user(S2HN(privN->bcomm->bc_filter_area),
879 ioc.data, ioc.len))
880 return -EFAULT;
881 privN->bcomm->bc_filter_cmd = BC_FILTER_SET;
882 }
883 else
884 privN->bcomm->bc_filter_cmd = BC_FILTER_CLR;
885 return(0);
886 default:
887 return -EOPNOTSUPP;
888 }
889}
890
891/*
892 * Process interrupts
893 *
894 * dev, priv will always refer to the 0th device in Multi-NIC mode.
895 */
896
David Howells7d12e782006-10-05 14:55:46 +0100897static irqreturn_t dgrs_intr(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898{
Jeff Garzikc31f28e2006-10-06 14:56:04 -0400899 struct net_device *dev0 = dev_id;
900 DGRS_PRIV *priv0 = dev0->priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 I596_CB *cbp;
902 int cmd;
903 int i;
904
905 ++priv0->intrcnt;
906 if (1) ++priv0->bcomm->bc_cnt[4];
907 if (0)
908 {
909 static int cnt = 100;
910 if (--cnt > 0)
911 printk("%s: interrupt: irq %d\n", dev0->name, irq);
912 }
913
914 /*
915 * Get 596 command
916 */
917 cmd = priv0->scbp->cmd;
918
919 /*
920 * See if RU has been restarted
921 */
922 if ( (cmd & I596_SCB_RUC) == I596_SCB_RUC_START)
923 {
924 if (0) printk("%s: RUC start\n", dev0->name);
925 priv0->rfdp = (I596_RFD *) S2H(priv0->scbp->rfdp);
926 priv0->rbdp = (I596_RBD *) S2H(priv0->rfdp->rbdp);
927 priv0->scbp->status &= ~(I596_SCB_RNR|I596_SCB_RUS);
928 /*
929 * Tell upper half (halves)
930 */
931 if (dgrs_nicmode)
932 {
933 for (i = 0; i < priv0->nports; ++i)
934 netif_wake_queue (priv0->devtbl[i]);
935 }
936 else
937 netif_wake_queue (dev0);
938 /* if (bd->flags & TX_QUEUED)
939 DL_sched(bd, bdd); */
940 }
941
942 /*
943 * See if any CU commands to process
944 */
945 if ( (cmd & I596_SCB_CUC) != I596_SCB_CUC_START)
946 {
947 priv0->scbp->cmd = 0; /* Ignore all other commands */
948 goto ack_intr;
949 }
950 priv0->scbp->status &= ~(I596_SCB_CNA|I596_SCB_CUS);
951
952 /*
953 * Process a command
954 */
955 cbp = (I596_CB *) S2H(priv0->scbp->cbp);
956 priv0->scbp->cmd = 0; /* Safe to clear the command */
957 for (;;)
958 {
959 switch (cbp->nop.cmd & I596_CB_CMD)
960 {
961 case I596_CB_CMD_XMIT:
962 dgrs_rcv_frame(dev0, priv0, cbp);
963 break;
964 default:
965 cbp->nop.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
966 break;
967 }
968 if (cbp->nop.cmd & I596_CB_CMD_EL)
969 break;
970 cbp = (I596_CB *) S2H(cbp->nop.next);
971 }
972 priv0->scbp->status |= I596_SCB_CNA;
973
974 /*
975 * Ack the interrupt
976 */
977ack_intr:
978 if (priv0->plxreg)
979 OUTL(dev0->base_addr + PLX_LCL2PCI_DOORBELL, 1);
980
981 return IRQ_HANDLED;
982}
983
984/*
985 * Download the board firmware
986 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400987static int __init
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988dgrs_download(struct net_device *dev0)
989{
990 DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
991 int is;
992 unsigned long i;
993
Arjan van de Venf71e1302006-03-03 21:33:57 -0500994 static const int iv2is[16] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995 0, 0, 0, ES4H_IS_INT3,
996 0, ES4H_IS_INT5, 0, ES4H_IS_INT7,
997 0, 0, ES4H_IS_INT10, ES4H_IS_INT11,
998 ES4H_IS_INT12, 0, 0, ES4H_IS_INT15 };
999
1000 /*
1001 * Map in the dual port memory
1002 */
1003 priv0->vmem = ioremap(dev0->mem_start, 2048*1024);
1004 if (!priv0->vmem)
1005 {
1006 printk("%s: cannot map in board memory\n", dev0->name);
1007 return -ENXIO;
1008 }
1009
1010 /*
1011 * Hold the processor and configure the board addresses
1012 */
1013 if (priv0->plxreg)
1014 { /* PCI bus */
1015 proc_reset(dev0, 1);
1016 }
1017 else
1018 { /* EISA bus */
1019 is = iv2is[dev0->irq & 0x0f];
1020 if (!is)
1021 {
1022 printk("%s: Illegal IRQ %d\n", dev0->name, dev0->irq);
1023 iounmap(priv0->vmem);
1024 priv0->vmem = NULL;
1025 return -ENXIO;
1026 }
1027 OUTB(dev0->base_addr + ES4H_AS_31_24,
1028 (uchar) (dev0->mem_start >> 24) );
1029 OUTB(dev0->base_addr + ES4H_AS_23_16,
1030 (uchar) (dev0->mem_start >> 16) );
1031 priv0->is_reg = ES4H_IS_LINEAR | is |
1032 ((uchar) (dev0->mem_start >> 8) & ES4H_IS_AS15);
1033 OUTB(dev0->base_addr + ES4H_IS, priv0->is_reg);
1034 OUTB(dev0->base_addr + ES4H_EC, ES4H_EC_ENABLE);
1035 OUTB(dev0->base_addr + ES4H_PC, ES4H_PC_RESET);
1036 OUTB(dev0->base_addr + ES4H_MW, ES4H_MW_ENABLE | 0x00);
1037 }
1038
1039 /*
1040 * See if we can do DMA on the SE-6
1041 */
1042 priv0->use_dma = check_board_dma(dev0);
1043 if (priv0->use_dma)
1044 printk("%s: Bus Master DMA is enabled.\n", dev0->name);
1045
1046 /*
1047 * Load and verify the code at the desired address
1048 */
1049 memcpy(priv0->vmem, dgrs_code, dgrs_ncode); /* Load code */
1050 if (memcmp(priv0->vmem, dgrs_code, dgrs_ncode))
1051 {
1052 iounmap(priv0->vmem);
1053 priv0->vmem = NULL;
1054 printk("%s: download compare failed\n", dev0->name);
1055 return -ENXIO;
1056 }
1057
1058 /*
1059 * Configurables
1060 */
1061 priv0->bcomm = (struct bios_comm *) (priv0->vmem + 0x0100);
1062 priv0->bcomm->bc_nowait = 1; /* Tell board to make printf not wait */
1063 priv0->bcomm->bc_squelch = 0; /* Flag from Space.c */
1064 priv0->bcomm->bc_150ohm = 0; /* Flag from Space.c */
1065
1066 priv0->bcomm->bc_spew = 0; /* Debug flag from Space.c */
1067 priv0->bcomm->bc_maxrfd = 0; /* Debug flag from Space.c */
1068 priv0->bcomm->bc_maxrbd = 0; /* Debug flag from Space.c */
1069
1070 /*
1071 * Tell board we are operating in switch mode (1) or in
1072 * multi-NIC mode (2).
1073 */
1074 priv0->bcomm->bc_host = dgrs_nicmode ? BC_MULTINIC : BC_SWITCH;
1075
1076 /*
1077 * Request memory space on board for DMA chains
1078 */
1079 if (priv0->use_dma)
1080 priv0->bcomm->bc_hostarea_len = (2048/64) * 16;
1081
1082 /*
1083 * NVRAM configurables from Space.c
1084 */
1085 priv0->bcomm->bc_spantree = dgrs_spantree;
1086 priv0->bcomm->bc_hashexpire = dgrs_hashexpire;
1087 memcpy(priv0->bcomm->bc_ipaddr, dgrs_ipaddr, 4);
1088 memcpy(priv0->bcomm->bc_iptrap, dgrs_iptrap, 4);
1089 memcpy(priv0->bcomm->bc_ipxnet, &dgrs_ipxnet, 4);
1090
1091 /*
1092 * Release processor, wait 8 seconds for board to initialize
1093 */
1094 proc_reset(dev0, 0);
1095
1096 for (i = jiffies + 8 * HZ; time_after(i, jiffies); )
1097 {
1098 barrier(); /* Gcc 2.95 needs this */
1099 if (priv0->bcomm->bc_status >= BC_RUN)
1100 break;
1101 }
1102
1103 if (priv0->bcomm->bc_status < BC_RUN)
1104 {
1105 printk("%s: board not operating\n", dev0->name);
1106 iounmap(priv0->vmem);
1107 priv0->vmem = NULL;
1108 return -ENXIO;
1109 }
1110
1111 priv0->port = (PORT *) S2H(priv0->bcomm->bc_port);
1112 priv0->scbp = (I596_SCB *) S2H(priv0->port->scbp);
1113 priv0->rfdp = (I596_RFD *) S2H(priv0->scbp->rfdp);
1114 priv0->rbdp = (I596_RBD *) S2H(priv0->rfdp->rbdp);
1115
1116 priv0->scbp->status = I596_SCB_CNA; /* CU is idle */
1117
1118 /*
1119 * Get switch physical and host virtual pointers to DMA
1120 * chaining area. NOTE: the MSB of the switch physical
1121 * address *must* be turned off. Otherwise, the HW kludge
1122 * that allows host access of the PLX DMA registers will
1123 * erroneously select the PLX registers.
1124 */
1125 priv0->dmadesc_s = (DMACHAIN *) S2DMA(priv0->bcomm->bc_hostarea);
1126 if (priv0->dmadesc_s)
1127 priv0->dmadesc_h = (DMACHAIN *) S2H(priv0->dmadesc_s);
1128 else
1129 priv0->dmadesc_h = NULL;
1130
1131 /*
1132 * Enable board interrupts
1133 */
1134 if (priv0->plxreg)
1135 { /* PCI bus */
1136 OUTL(dev0->base_addr + PLX_INT_CSR,
1137 inl(dev0->base_addr + PLX_INT_CSR)
1138 | PLX_PCI_DOORBELL_IE); /* Enable intr to host */
1139 OUTL(dev0->base_addr + PLX_LCL2PCI_DOORBELL, 1);
1140 }
1141 else
1142 { /* EISA bus */
1143 }
1144
1145 return (0);
1146}
1147
1148/*
1149 * Probe (init) a board
1150 */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001151static int __init
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152dgrs_probe1(struct net_device *dev)
1153{
1154 DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
1155 unsigned long i;
1156 int rc;
1157
1158 printk("%s: Digi RightSwitch io=%lx mem=%lx irq=%d plx=%lx dma=%lx\n",
1159 dev->name, dev->base_addr, dev->mem_start, dev->irq,
1160 priv->plxreg, priv->plxdma);
1161
1162 /*
1163 * Download the firmware and light the processor
1164 */
1165 rc = dgrs_download(dev);
1166 if (rc)
1167 goto err_out;
1168
1169 /*
1170 * Get ether address of board
1171 */
1172 printk("%s: Ethernet address", dev->name);
1173 memcpy(dev->dev_addr, priv->port->ethaddr, 6);
1174 for (i = 0; i < 6; ++i)
1175 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1176 printk("\n");
1177
1178 if (dev->dev_addr[0] & 1)
1179 {
1180 printk("%s: Illegal Ethernet Address\n", dev->name);
1181 rc = -ENXIO;
1182 goto err_out;
1183 }
1184
1185 /*
1186 * ACK outstanding interrupts, hook the interrupt,
1187 * and verify that we are getting interrupts from the board.
1188 */
1189 if (priv->plxreg)
1190 OUTL(dev->base_addr + PLX_LCL2PCI_DOORBELL, 1);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001191
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07001192 rc = request_irq(dev->irq, &dgrs_intr, IRQF_SHARED, "RightSwitch", dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 if (rc)
1194 goto err_out;
1195
1196 priv->intrcnt = 0;
1197 for (i = jiffies + 2*HZ + HZ/2; time_after(i, jiffies); )
1198 {
1199 cpu_relax();
1200 if (priv->intrcnt >= 2)
1201 break;
1202 }
1203 if (priv->intrcnt < 2)
1204 {
1205 printk(KERN_ERR "%s: Not interrupting on IRQ %d (%d)\n",
1206 dev->name, dev->irq, priv->intrcnt);
1207 rc = -ENXIO;
1208 goto err_free_irq;
1209 }
1210
1211 /*
1212 * Entry points...
1213 */
1214 dev->open = &dgrs_open;
1215 dev->stop = &dgrs_close;
1216 dev->get_stats = &dgrs_get_stats;
1217 dev->hard_start_xmit = &dgrs_start_xmit;
1218 dev->set_multicast_list = &dgrs_set_multicast_list;
1219 dev->do_ioctl = &dgrs_ioctl;
1220
1221 return rc;
1222
1223err_free_irq:
1224 free_irq(dev->irq, dev);
1225err_out:
1226 return rc;
1227}
1228
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001229static int __init
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230dgrs_initclone(struct net_device *dev)
1231{
1232 DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
1233 int i;
1234
1235 printk("%s: Digi RightSwitch port %d ",
1236 dev->name, priv->chan);
1237 for (i = 0; i < 6; ++i)
1238 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1239 printk("\n");
1240
1241 return (0);
1242}
1243
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001244static struct net_device * __init
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245dgrs_found_device(
1246 int io,
1247 ulong mem,
1248 int irq,
1249 ulong plxreg,
1250 ulong plxdma,
1251 struct device *pdev
1252)
1253{
1254 DGRS_PRIV *priv;
1255 struct net_device *dev;
1256 int i, ret = -ENOMEM;
1257
1258 dev = alloc_etherdev(sizeof(DGRS_PRIV));
1259 if (!dev)
1260 goto err0;
1261
1262 priv = (DGRS_PRIV *)dev->priv;
1263
1264 dev->base_addr = io;
1265 dev->mem_start = mem;
1266 dev->mem_end = mem + 2048 * 1024 - 1;
1267 dev->irq = irq;
1268 priv->plxreg = plxreg;
1269 priv->plxdma = plxdma;
1270 priv->vplxdma = NULL;
1271
1272 priv->chan = 1;
1273 priv->devtbl[0] = dev;
1274
1275 SET_MODULE_OWNER(dev);
1276 SET_NETDEV_DEV(dev, pdev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001277
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 ret = dgrs_probe1(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001279 if (ret)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280 goto err1;
1281
1282 ret = register_netdev(dev);
1283 if (ret)
1284 goto err2;
1285
1286 if ( !dgrs_nicmode )
1287 return dev; /* Switch mode, we are done */
1288
1289 /*
1290 * Operating card as N separate NICs
1291 */
1292
1293 priv->nports = priv->bcomm->bc_nports;
1294
1295 for (i = 1; i < priv->nports; ++i)
1296 {
1297 struct net_device *devN;
1298 DGRS_PRIV *privN;
1299 /* Allocate new dev and priv structures */
1300 devN = alloc_etherdev(sizeof(DGRS_PRIV));
1301 ret = -ENOMEM;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001302 if (!devN)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303 goto fail;
1304
1305 /* Don't copy the network device structure! */
1306
1307 /* copy the priv structure of dev[0] */
1308 privN = (DGRS_PRIV *)devN->priv;
1309 *privN = *priv;
1310
1311 /* ... and zero out VM areas */
1312 privN->vmem = NULL;
1313 privN->vplxdma = NULL;
1314 /* ... and zero out IRQ */
1315 devN->irq = 0;
1316 /* ... and base MAC address off address of 1st port */
1317 devN->dev_addr[5] += i;
1318
1319 ret = dgrs_initclone(devN);
1320 if (ret)
1321 goto fail;
1322
1323 SET_MODULE_OWNER(devN);
1324 SET_NETDEV_DEV(dev, pdev);
1325
1326 ret = register_netdev(devN);
1327 if (ret) {
1328 free_netdev(devN);
1329 goto fail;
1330 }
1331 privN->chan = i+1;
1332 priv->devtbl[i] = devN;
1333 }
1334 return dev;
1335
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001336 fail:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 while (i >= 0) {
1338 struct net_device *d = priv->devtbl[i--];
1339 unregister_netdev(d);
1340 free_netdev(d);
1341 }
1342
1343 err2:
1344 free_irq(dev->irq, dev);
1345 err1:
1346 free_netdev(dev);
1347 err0:
1348 return ERR_PTR(ret);
1349}
1350
1351static void __devexit dgrs_remove(struct net_device *dev)
1352{
1353 DGRS_PRIV *priv = dev->priv;
1354 int i;
1355
1356 unregister_netdev(dev);
1357
1358 for (i = 1; i < priv->nports; ++i) {
1359 struct net_device *d = priv->devtbl[i];
1360 if (d) {
1361 unregister_netdev(d);
1362 free_netdev(d);
1363 }
1364 }
1365
1366 proc_reset(priv->devtbl[0], 1);
1367
1368 if (priv->vmem)
1369 iounmap(priv->vmem);
1370 if (priv->vplxdma)
1371 iounmap((uchar *) priv->vplxdma);
1372
1373 if (dev->irq)
1374 free_irq(dev->irq, dev);
1375
1376 for (i = 1; i < priv->nports; ++i) {
1377 if (priv->devtbl[i])
1378 unregister_netdev(priv->devtbl[i]);
1379 }
1380}
1381
1382#ifdef CONFIG_PCI
1383static int __init dgrs_pci_probe(struct pci_dev *pdev,
1384 const struct pci_device_id *ent)
1385{
1386 struct net_device *dev;
1387 int err;
1388 uint io;
1389 uint mem;
1390 uint irq;
1391 uint plxreg;
1392 uint plxdma;
1393
1394 /*
1395 * Get and check the bus-master and latency values.
1396 * Some PCI BIOSes fail to set the master-enable bit,
1397 * and the latency timer must be set to the maximum
1398 * value to avoid data corruption that occurs when the
1399 * timer expires during a transfer. Yes, it's a bug.
1400 */
1401 err = pci_enable_device(pdev);
1402 if (err)
1403 return err;
1404 err = pci_request_regions(pdev, "RightSwitch");
1405 if (err)
1406 return err;
1407
1408 pci_set_master(pdev);
1409
1410 plxreg = pci_resource_start (pdev, 0);
1411 io = pci_resource_start (pdev, 1);
1412 mem = pci_resource_start (pdev, 2);
1413 pci_read_config_dword(pdev, 0x30, &plxdma);
1414 irq = pdev->irq;
1415 plxdma &= ~15;
1416
1417 /*
1418 * On some BIOSES, the PLX "expansion rom" (used for DMA)
1419 * address comes up as "0". This is probably because
1420 * the BIOS doesn't see a valid 55 AA ROM signature at
1421 * the "ROM" start and zeroes the address. To get
1422 * around this problem the SE-6 is configured to ask
1423 * for 4 MB of space for the dual port memory. We then
1424 * must set its range back to 2 MB, and use the upper
1425 * half for DMA register access
1426 */
1427 OUTL(io + PLX_SPACE0_RANGE, 0xFFE00000L);
1428 if (plxdma == 0)
1429 plxdma = mem + (2048L * 1024L);
1430 pci_write_config_dword(pdev, 0x30, plxdma + 1);
1431 pci_read_config_dword(pdev, 0x30, &plxdma);
1432 plxdma &= ~15;
1433
1434 dev = dgrs_found_device(io, mem, irq, plxreg, plxdma, &pdev->dev);
1435 if (IS_ERR(dev)) {
1436 pci_release_regions(pdev);
1437 return PTR_ERR(dev);
1438 }
1439
1440 pci_set_drvdata(pdev, dev);
1441 return 0;
1442}
1443
1444static void __devexit dgrs_pci_remove(struct pci_dev *pdev)
1445{
1446 struct net_device *dev = pci_get_drvdata(pdev);
1447
1448 dgrs_remove(dev);
1449 pci_release_regions(pdev);
1450 free_netdev(dev);
1451}
1452
1453static struct pci_driver dgrs_pci_driver = {
1454 .name = "dgrs",
1455 .id_table = dgrs_pci_tbl,
1456 .probe = dgrs_pci_probe,
1457 .remove = __devexit_p(dgrs_pci_remove),
1458};
Richard Knutsson18317ab2005-11-21 21:32:03 -08001459#else
1460static struct pci_driver dgrs_pci_driver = {};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461#endif
1462
1463
1464#ifdef CONFIG_EISA
1465static int is2iv[8] __initdata = { 0, 3, 5, 7, 10, 11, 12, 15 };
1466
1467static int __init dgrs_eisa_probe (struct device *gendev)
1468{
1469 struct net_device *dev;
1470 struct eisa_device *edev = to_eisa_device(gendev);
1471 uint io = edev->base_addr;
1472 uint mem;
1473 uint irq;
1474 int rc = -ENODEV; /* Not EISA configured */
1475
1476 if (!request_region(io, 256, "RightSwitch")) {
1477 printk(KERN_ERR "dgrs: eisa io 0x%x, which is busy.\n", io);
1478 return -EBUSY;
1479 }
1480
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001481 if ( ! (inb(io+ES4H_EC) & ES4H_EC_ENABLE) )
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 goto err_out;
1483
1484 mem = (inb(io+ES4H_AS_31_24) << 24)
1485 + (inb(io+ES4H_AS_23_16) << 16);
1486
1487 irq = is2iv[ inb(io+ES4H_IS) & ES4H_IS_INTMASK ];
1488
1489 dev = dgrs_found_device(io, mem, irq, 0L, 0L, gendev);
1490 if (IS_ERR(dev)) {
1491 rc = PTR_ERR(dev);
1492 goto err_out;
1493 }
1494
1495 gendev->driver_data = dev;
1496 return 0;
1497 err_out:
1498 release_region(io, 256);
1499 return rc;
1500}
1501
1502static int __devexit dgrs_eisa_remove(struct device *gendev)
1503{
1504 struct net_device *dev = gendev->driver_data;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001505
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506 dgrs_remove(dev);
1507
1508 release_region(dev->base_addr, 256);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001509
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510 free_netdev(dev);
1511 return 0;
1512}
1513
1514
1515static struct eisa_driver dgrs_eisa_driver = {
1516 .id_table = dgrs_eisa_tbl,
1517 .driver = {
1518 .name = "dgrs",
1519 .probe = dgrs_eisa_probe,
1520 .remove = __devexit_p(dgrs_eisa_remove),
1521 }
1522};
1523#endif
1524
1525/*
1526 * Variables that can be overriden from module command line
1527 */
1528static int debug = -1;
1529static int dma = -1;
1530static int hashexpire = -1;
1531static int spantree = -1;
1532static int ipaddr[4] = { -1 };
1533static int iptrap[4] = { -1 };
1534static __u32 ipxnet = -1;
1535static int nicmode = -1;
1536
1537module_param(debug, int, 0);
1538module_param(dma, int, 0);
1539module_param(hashexpire, int, 0);
1540module_param(spantree, int, 0);
1541module_param_array(ipaddr, int, NULL, 0);
1542module_param_array(iptrap, int, NULL, 0);
1543module_param(ipxnet, int, 0);
1544module_param(nicmode, int, 0);
1545MODULE_PARM_DESC(debug, "Digi RightSwitch enable debugging (0-1)");
1546MODULE_PARM_DESC(dma, "Digi RightSwitch enable BM DMA (0-1)");
1547MODULE_PARM_DESC(nicmode, "Digi RightSwitch operating mode (1: switch, 2: multi-NIC)");
1548
1549static int __init dgrs_init_module (void)
1550{
1551 int i;
Bjorn Helgaasc2f6fab2006-03-25 03:07:19 -08001552 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
1554 /*
1555 * Command line variable overrides
1556 * debug=NNN
1557 * dma=0/1
1558 * spantree=0/1
1559 * hashexpire=NNN
1560 * ipaddr=A,B,C,D
1561 * iptrap=A,B,C,D
1562 * ipxnet=NNN
1563 * nicmode=NNN
1564 */
1565 if (debug >= 0)
1566 dgrs_debug = debug;
1567 if (dma >= 0)
1568 dgrs_dma = dma;
1569 if (nicmode >= 0)
1570 dgrs_nicmode = nicmode;
1571 if (hashexpire >= 0)
1572 dgrs_hashexpire = hashexpire;
1573 if (spantree >= 0)
1574 dgrs_spantree = spantree;
1575 if (ipaddr[0] != -1)
1576 for (i = 0; i < 4; ++i)
1577 dgrs_ipaddr[i] = ipaddr[i];
1578 if (iptrap[0] != -1)
1579 for (i = 0; i < 4; ++i)
1580 dgrs_iptrap[i] = iptrap[i];
1581 if (ipxnet != -1)
1582 dgrs_ipxnet = htonl( ipxnet );
1583
1584 if (dgrs_debug)
1585 {
1586 printk(KERN_INFO "dgrs: SW=%s FW=Build %d %s\nFW Version=%s\n",
1587 version, dgrs_firmnum, dgrs_firmdate, dgrs_firmver);
1588 }
1589
1590 /*
1591 * Find and configure all the cards
1592 */
1593#ifdef CONFIG_EISA
Bjorn Helgaasc2f6fab2006-03-25 03:07:19 -08001594 err = eisa_driver_register(&dgrs_eisa_driver);
1595 if (err)
1596 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597#endif
Bjorn Helgaasc2f6fab2006-03-25 03:07:19 -08001598 err = pci_register_driver(&dgrs_pci_driver);
1599 if (err)
1600 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601 return 0;
1602}
1603
1604static void __exit dgrs_cleanup_module (void)
1605{
1606#ifdef CONFIG_EISA
1607 eisa_driver_unregister (&dgrs_eisa_driver);
1608#endif
1609#ifdef CONFIG_PCI
1610 pci_unregister_driver (&dgrs_pci_driver);
1611#endif
1612}
1613
1614module_init(dgrs_init_module);
1615module_exit(dgrs_cleanup_module);