blob: 2a95d10e9d928d45877d5491c0b94e6ec18711d3 [file] [log] [blame]
Andy Yanb21f4b62014-12-05 14:26:31 +08001/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
2 *
3 * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/component.h>
12#include <linux/mfd/syscon.h>
13#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
14#include <drm/bridge/dw_hdmi.h>
15#include <video/imx-ipu-v3.h>
16#include <linux/regmap.h>
17#include <drm/drm_of.h>
18#include <drm/drmP.h>
19#include <drm/drm_crtc_helper.h>
20#include <drm/drm_edid.h>
21#include <drm/drm_encoder_slave.h>
22
23#include "imx-drm.h"
24
25struct imx_hdmi {
26 struct device *dev;
27 struct drm_encoder encoder;
28 struct regmap *regmap;
29};
30
31static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
32 {
33 45250000, {
34 { 0x01e0, 0x0000 },
35 { 0x21e1, 0x0000 },
36 { 0x41e2, 0x0000 }
37 },
38 }, {
39 92500000, {
40 { 0x0140, 0x0005 },
41 { 0x2141, 0x0005 },
42 { 0x4142, 0x0005 },
43 },
44 }, {
45 148500000, {
46 { 0x00a0, 0x000a },
47 { 0x20a1, 0x000a },
48 { 0x40a2, 0x000a },
49 },
50 }, {
Lucas Stacha5f41852015-10-15 15:42:17 +020051 216000000, {
Andy Yanb21f4b62014-12-05 14:26:31 +080052 { 0x00a0, 0x000a },
53 { 0x2001, 0x000f },
54 { 0x4002, 0x000f },
55 },
Lucas Stacha5f41852015-10-15 15:42:17 +020056 }, {
57 ~0UL, {
58 { 0x0000, 0x0000 },
59 { 0x0000, 0x0000 },
60 { 0x0000, 0x0000 },
61 },
Andy Yanb21f4b62014-12-05 14:26:31 +080062 }
63};
64
65static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
66 /* pixelclk bpp8 bpp10 bpp12 */
67 {
68 54000000, { 0x091c, 0x091c, 0x06dc },
69 }, {
70 58400000, { 0x091c, 0x06dc, 0x06dc },
71 }, {
72 72000000, { 0x06dc, 0x06dc, 0x091c },
73 }, {
74 74250000, { 0x06dc, 0x0b5c, 0x091c },
75 }, {
76 118800000, { 0x091c, 0x091c, 0x06dc },
77 }, {
78 216000000, { 0x06dc, 0x0b5c, 0x091c },
Philipp Zabel6e8958e2015-01-07 23:49:41 +010079 }, {
80 ~0UL, { 0x0000, 0x0000, 0x0000 },
81 },
Andy Yanb21f4b62014-12-05 14:26:31 +080082};
83
Russell King36b8ae02015-03-31 18:23:16 +010084/*
85 * Resistance term 133Ohm Cfg
86 * PREEMP config 0.00
87 * TX/CK level 10
88 */
Yakir Yang034705a2015-03-31 23:56:10 -040089static const struct dw_hdmi_phy_config imx_phy_config[] = {
90 /*pixelclk symbol term vlev */
Lucas Stacha5f41852015-10-15 15:42:17 +020091 { 216000000, 0x800d, 0x0005, 0x01ad},
Yakir Yang034705a2015-03-31 23:56:10 -040092 { ~0UL, 0x0000, 0x0000, 0x0000}
Andy Yanb21f4b62014-12-05 14:26:31 +080093};
94
95static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
96{
97 struct device_node *np = hdmi->dev->of_node;
98
99 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
100 if (IS_ERR(hdmi->regmap)) {
101 dev_err(hdmi->dev, "Unable to get gpr\n");
102 return PTR_ERR(hdmi->regmap);
103 }
104
105 return 0;
106}
107
108static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
109{
110}
111
Andy Yanb21f4b62014-12-05 14:26:31 +0800112static void dw_hdmi_imx_encoder_mode_set(struct drm_encoder *encoder,
113 struct drm_display_mode *mode,
114 struct drm_display_mode *adj_mode)
115{
116}
117
118static void dw_hdmi_imx_encoder_commit(struct drm_encoder *encoder)
119{
120 struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
Philipp Zabel53141e42015-02-24 11:41:28 +0100121 int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
Andy Yanb21f4b62014-12-05 14:26:31 +0800122
123 regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
124 IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
125 mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
126}
127
128static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder)
129{
Philipp Zabel2872c802015-02-02 17:25:59 +0100130 imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_RGB888_1X24);
Andy Yanb21f4b62014-12-05 14:26:31 +0800131}
132
Ville Syrjälä7ae847d2015-12-15 12:21:09 +0100133static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
Andy Yanb21f4b62014-12-05 14:26:31 +0800134 .mode_set = dw_hdmi_imx_encoder_mode_set,
135 .prepare = dw_hdmi_imx_encoder_prepare,
136 .commit = dw_hdmi_imx_encoder_commit,
137 .disable = dw_hdmi_imx_encoder_disable,
138};
139
Ville Syrjälä7ae847d2015-12-15 12:21:09 +0100140static const struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
Andy Yanb21f4b62014-12-05 14:26:31 +0800141 .destroy = drm_encoder_cleanup,
142};
143
Philipp Zabel081c80e2015-01-07 23:52:15 +0100144static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con,
145 struct drm_display_mode *mode)
146{
147 if (mode->clock < 13500)
148 return MODE_CLOCK_LOW;
Lucas Stacha5f41852015-10-15 15:42:17 +0200149 /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
150 if (mode->clock > 216000)
Philipp Zabel081c80e2015-01-07 23:52:15 +0100151 return MODE_CLOCK_HIGH;
152
153 return MODE_OK;
154}
155
156static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con,
157 struct drm_display_mode *mode)
158{
159 if (mode->clock < 13500)
160 return MODE_CLOCK_LOW;
Lucas Stacha5f41852015-10-15 15:42:17 +0200161 /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
162 if (mode->clock > 216000)
Philipp Zabel081c80e2015-01-07 23:52:15 +0100163 return MODE_CLOCK_HIGH;
164
165 return MODE_OK;
166}
167
Andy Yanb21f4b62014-12-05 14:26:31 +0800168static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
Philipp Zabel081c80e2015-01-07 23:52:15 +0100169 .mpll_cfg = imx_mpll_cfg,
170 .cur_ctr = imx_cur_ctr,
Yakir Yang034705a2015-03-31 23:56:10 -0400171 .phy_config = imx_phy_config,
Philipp Zabel081c80e2015-01-07 23:52:15 +0100172 .dev_type = IMX6Q_HDMI,
173 .mode_valid = imx6q_hdmi_mode_valid,
Andy Yanb21f4b62014-12-05 14:26:31 +0800174};
175
176static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
177 .mpll_cfg = imx_mpll_cfg,
178 .cur_ctr = imx_cur_ctr,
Yakir Yang034705a2015-03-31 23:56:10 -0400179 .phy_config = imx_phy_config,
Andy Yanb21f4b62014-12-05 14:26:31 +0800180 .dev_type = IMX6DL_HDMI,
Philipp Zabel081c80e2015-01-07 23:52:15 +0100181 .mode_valid = imx6dl_hdmi_mode_valid,
Andy Yanb21f4b62014-12-05 14:26:31 +0800182};
183
184static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
185 { .compatible = "fsl,imx6q-hdmi",
186 .data = &imx6q_hdmi_drv_data
187 }, {
188 .compatible = "fsl,imx6dl-hdmi",
189 .data = &imx6dl_hdmi_drv_data
190 },
191 {},
192};
193MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
194
195static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
196 void *data)
197{
198 struct platform_device *pdev = to_platform_device(dev);
199 const struct dw_hdmi_plat_data *plat_data;
200 const struct of_device_id *match;
201 struct drm_device *drm = data;
202 struct drm_encoder *encoder;
203 struct imx_hdmi *hdmi;
204 struct resource *iores;
205 int irq;
206 int ret;
207
208 if (!pdev->dev.of_node)
209 return -ENODEV;
210
211 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
212 if (!hdmi)
213 return -ENOMEM;
214
215 match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
216 plat_data = match->data;
217 hdmi->dev = &pdev->dev;
218 encoder = &hdmi->encoder;
219
220 irq = platform_get_irq(pdev, 0);
221 if (irq < 0)
222 return irq;
223
224 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
225 if (!iores)
226 return -ENXIO;
227
228 platform_set_drvdata(pdev, hdmi);
229
230 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
231 /*
232 * If we failed to find the CRTC(s) which this encoder is
233 * supposed to be connected to, it's because the CRTC has
234 * not been registered yet. Defer probing, and hope that
235 * the required CRTC is added later.
236 */
237 if (encoder->possible_crtcs == 0)
238 return -EPROBE_DEFER;
239
240 ret = dw_hdmi_imx_parse_dt(hdmi);
241 if (ret < 0)
242 return ret;
243
244 drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
245 drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
Ville Syrjälä13a3d912015-12-09 16:20:18 +0200246 DRM_MODE_ENCODER_TMDS, NULL);
Andy Yanb21f4b62014-12-05 14:26:31 +0800247
248 return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
249}
250
251static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
252 void *data)
253{
254 return dw_hdmi_unbind(dev, master, data);
255}
256
257static const struct component_ops dw_hdmi_imx_ops = {
258 .bind = dw_hdmi_imx_bind,
259 .unbind = dw_hdmi_imx_unbind,
260};
261
262static int dw_hdmi_imx_probe(struct platform_device *pdev)
263{
264 return component_add(&pdev->dev, &dw_hdmi_imx_ops);
265}
266
267static int dw_hdmi_imx_remove(struct platform_device *pdev)
268{
269 component_del(&pdev->dev, &dw_hdmi_imx_ops);
270
271 return 0;
272}
273
274static struct platform_driver dw_hdmi_imx_platform_driver = {
275 .probe = dw_hdmi_imx_probe,
276 .remove = dw_hdmi_imx_remove,
277 .driver = {
278 .name = "dwhdmi-imx",
279 .of_match_table = dw_hdmi_imx_dt_ids,
280 },
281};
282
283module_platform_driver(dw_hdmi_imx_platform_driver);
284
285MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
286MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
287MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
288MODULE_LICENSE("GPL");
289MODULE_ALIAS("platform:dwhdmi-imx");