Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 1994 - 2002 by Ralf Baechle |
| 7 | * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. |
| 8 | * Copyright (C) 2002 Maciej W. Rozycki |
| 9 | */ |
| 10 | #ifndef _ASM_PGTABLE_BITS_H |
| 11 | #define _ASM_PGTABLE_BITS_H |
| 12 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | |
| 14 | /* |
| 15 | * Note that we shift the lower 32bits of each EntryLo[01] entry |
| 16 | * 6 bits to the left. That way we can convert the PFN into the |
| 17 | * physical address by a single 'and' operation and gain 6 additional |
| 18 | * bits for storing information which isn't present in a normal |
| 19 | * MIPS page table. |
| 20 | * |
| 21 | * Similar to the Alpha port, we need to keep track of the ref |
| 22 | * and mod bits in software. We have a software "yeah you can read |
| 23 | * from this page" bit, and a hardware one which actually lets the |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 24 | * process read from the page. On the same token we have a software |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | * writable bit and the real hardware one which actually lets the |
| 26 | * process write to the page, this keeps a mod bit via the hardware |
| 27 | * dirty bit. |
| 28 | * |
| 29 | * Certain revisions of the R4000 and R5000 have a bug where if a |
| 30 | * certain sequence occurs in the last 3 instructions of an executable |
| 31 | * page, and the following page is not mapped, the cpu can do |
| 32 | * unpredictable things. The code (when it is written) to deal with |
| 33 | * this problem will be in the update_mmu_cache() code for the r4k. |
| 34 | */ |
Chris Dearman | 962f480 | 2007-09-19 00:46:32 +0100 | [diff] [blame] | 35 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 37 | /* |
| 38 | * The following bits are directly used by the TLB hardware |
| 39 | */ |
| 40 | #define _PAGE_R4KBUG (1 << 0) /* workaround for r4k bug */ |
| 41 | #define _PAGE_GLOBAL (1 << 0) |
| 42 | #define _PAGE_VALID_SHIFT 1 |
| 43 | #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 44 | #define _PAGE_SILENT_READ (1 << 1) /* synonym */ |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 45 | #define _PAGE_DIRTY_SHIFT 2 |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 46 | #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) /* The MIPS dirty bit */ |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 47 | #define _PAGE_SILENT_WRITE (1 << 2) |
| 48 | #define _CACHE_SHIFT 3 |
| 49 | #define _CACHE_MASK (7 << 3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 51 | /* |
| 52 | * The following bits are implemented in software |
| 53 | * |
| 54 | * _PAGE_FILE semantics: set:pagecache unset:swap |
Ralf Baechle | 82de378 | 2013-01-18 16:58:26 +0100 | [diff] [blame] | 55 | */ |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 56 | #define _PAGE_PRESENT_SHIFT 6 |
| 57 | #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) |
| 58 | #define _PAGE_READ_SHIFT 7 |
| 59 | #define _PAGE_READ (1 << _PAGE_READ_SHIFT) |
| 60 | #define _PAGE_WRITE_SHIFT 8 |
| 61 | #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) |
| 62 | #define _PAGE_ACCESSED_SHIFT 9 |
| 63 | #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) |
| 64 | #define _PAGE_MODIFIED_SHIFT 10 |
| 65 | #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) |
| 66 | |
| 67 | #define _PAGE_FILE (1 << 10) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 69 | #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 71 | /* |
| 72 | * The following are implemented by software |
| 73 | * |
| 74 | * _PAGE_FILE semantics: set:pagecache unset:swap |
| 75 | */ |
| 76 | #define _PAGE_PRESENT_SHIFT 0 |
| 77 | #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) |
| 78 | #define _PAGE_READ_SHIFT 1 |
| 79 | #define _PAGE_READ (1 << _PAGE_READ_SHIFT) |
| 80 | #define _PAGE_WRITE_SHIFT 2 |
| 81 | #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) |
| 82 | #define _PAGE_ACCESSED_SHIFT 3 |
| 83 | #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) |
| 84 | #define _PAGE_MODIFIED_SHIFT 4 |
| 85 | #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) |
| 86 | #define _PAGE_FILE_SHIFT 4 |
| 87 | #define _PAGE_FILE (1 << _PAGE_FILE_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 89 | /* |
| 90 | * And these are the hardware TLB bits |
| 91 | */ |
| 92 | #define _PAGE_GLOBAL_SHIFT 8 |
| 93 | #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) |
| 94 | #define _PAGE_VALID_SHIFT 9 |
| 95 | #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) |
| 96 | #define _PAGE_SILENT_READ (1 << _PAGE_VALID_SHIFT) /* synonym */ |
| 97 | #define _PAGE_DIRTY_SHIFT 10 |
| 98 | #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) |
| 99 | #define _PAGE_SILENT_WRITE (1 << _PAGE_DIRTY_SHIFT) |
| 100 | #define _CACHE_UNCACHED_SHIFT 11 |
| 101 | #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) |
| 102 | #define _CACHE_MASK (1 << _CACHE_UNCACHED_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 104 | #else /* 'Normal' r4K case */ |
| 105 | /* |
| 106 | * When using the RI/XI bit support, we have 13 bits of flags below |
| 107 | * the physical address. The RI/XI bits are placed such that a SRL 5 |
| 108 | * can strip off the software bits, then a ROTR 2 can move the RI/XI |
| 109 | * into bits [63:62]. This also limits physical address to 56 bits, |
| 110 | * which is more than we need right now. |
| 111 | */ |
| 112 | |
Ralf Baechle | a2c763e | 2012-10-16 22:20:26 +0200 | [diff] [blame] | 113 | /* |
| 114 | * The following bits are implemented in software |
| 115 | * |
| 116 | * _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi. |
| 117 | * _PAGE_FILE semantics: set:pagecache unset:swap |
| 118 | */ |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 119 | #define _PAGE_PRESENT_SHIFT (0) |
| 120 | #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) |
Steven J. Hill | 05857c6 | 2012-09-13 16:51:46 -0500 | [diff] [blame] | 121 | #define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) |
| 122 | #define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 123 | #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) |
| 124 | #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 125 | #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) |
| 126 | #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 127 | #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) |
| 128 | #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 129 | #define _PAGE_FILE (_PAGE_MODIFIED) |
| 130 | |
David Daney | aa1762f | 2012-10-17 00:48:10 +0200 | [diff] [blame] | 131 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 132 | /* huge tlb page */ |
| 133 | #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) |
| 134 | #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | #else |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 136 | #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 137 | #define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ |
Chris Dearman | bec5052 | 2007-09-19 00:51:57 +0100 | [diff] [blame] | 138 | #endif |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 139 | |
Ralf Baechle | 970d032 | 2012-10-18 13:54:15 +0200 | [diff] [blame] | 140 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
| 141 | /* huge tlb page */ |
| 142 | #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) |
| 143 | #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) |
| 144 | #else |
| 145 | #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 146 | #define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ |
Ralf Baechle | 970d032 | 2012-10-18 13:54:15 +0200 | [diff] [blame] | 147 | #endif |
| 148 | |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 149 | /* Page cannot be executed */ |
Ralf Baechle | 970d032 | 2012-10-18 13:54:15 +0200 | [diff] [blame] | 150 | #define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT) |
Steven J. Hill | 05857c6 | 2012-09-13 16:51:46 -0500 | [diff] [blame] | 151 | #define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; }) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 152 | |
| 153 | /* Page cannot be read */ |
Steven J. Hill | 05857c6 | 2012-09-13 16:51:46 -0500 | [diff] [blame] | 154 | #define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) |
| 155 | #define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; }) |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 156 | |
| 157 | #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) |
| 158 | #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) |
| 159 | |
| 160 | #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) |
| 161 | #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 162 | /* synonym */ |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 163 | #define _PAGE_SILENT_READ (_PAGE_VALID) |
| 164 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 165 | /* The MIPS dirty bit */ |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 166 | #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) |
| 167 | #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) |
| 168 | #define _PAGE_SILENT_WRITE (_PAGE_DIRTY) |
| 169 | |
| 170 | #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) |
| 171 | #define _CACHE_MASK (7 << _CACHE_SHIFT) |
| 172 | |
| 173 | #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) |
| 174 | |
Chris Dearman | bec5052 | 2007-09-19 00:51:57 +0100 | [diff] [blame] | 175 | #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ |
| 176 | |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 177 | #ifndef _PFN_SHIFT |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 178 | #define _PFN_SHIFT PAGE_SHIFT |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 179 | #endif |
| 180 | #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) |
| 181 | |
| 182 | #ifndef _PAGE_NO_READ |
| 183 | #define _PAGE_NO_READ ({BUG(); 0; }) |
| 184 | #define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) |
| 185 | #endif |
| 186 | #ifndef _PAGE_NO_EXEC |
| 187 | #define _PAGE_NO_EXEC ({BUG(); 0; }) |
| 188 | #endif |
| 189 | #ifndef _PAGE_GLOBAL_SHIFT |
| 190 | #define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL) |
| 191 | #endif |
| 192 | |
| 193 | |
| 194 | #ifndef __ASSEMBLY__ |
| 195 | /* |
| 196 | * pte_to_entrylo converts a page table entry (PTE) into a Mips |
| 197 | * entrylo0/1 value. |
| 198 | */ |
| 199 | static inline uint64_t pte_to_entrylo(unsigned long pte_val) |
| 200 | { |
Steven J. Hill | 05857c6 | 2012-09-13 16:51:46 -0500 | [diff] [blame] | 201 | if (cpu_has_rixi) { |
David Daney | 6dd9344 | 2010-02-10 15:12:47 -0800 | [diff] [blame] | 202 | int sa; |
| 203 | #ifdef CONFIG_32BIT |
| 204 | sa = 31 - _PAGE_NO_READ_SHIFT; |
| 205 | #else |
| 206 | sa = 63 - _PAGE_NO_READ_SHIFT; |
| 207 | #endif |
| 208 | /* |
| 209 | * C has no way to express that this is a DSRL |
| 210 | * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily |
| 211 | * in the fast path this is done in assembly |
| 212 | */ |
| 213 | return (pte_val >> _PAGE_GLOBAL_SHIFT) | |
| 214 | ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); |
| 215 | } |
| 216 | |
| 217 | return pte_val >> _PAGE_GLOBAL_SHIFT; |
| 218 | } |
| 219 | #endif |
Chris Dearman | bec5052 | 2007-09-19 00:51:57 +0100 | [diff] [blame] | 220 | |
| 221 | /* |
| 222 | * Cache attributes |
| 223 | */ |
| 224 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) |
| 225 | |
| 226 | #define _CACHE_CACHABLE_NONCOHERENT 0 |
| 227 | |
| 228 | #elif defined(CONFIG_CPU_SB1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 229 | |
| 230 | /* No penalty for being coherent on the SB1, so just |
| 231 | use it for "noncoherent" spaces, too. Shouldn't hurt. */ |
| 232 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 233 | #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) |
| 234 | #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) |
Chris Dearman | bec5052 | 2007-09-19 00:51:57 +0100 | [diff] [blame] | 235 | #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) |
| 236 | #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | #else |
| 239 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 240 | #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ |
| 241 | #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) /* R4600 only */ |
| 242 | #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* R4[0246]00 */ |
| 243 | #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* R4[0246]00 */ |
| 244 | #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) /* R4[04]00MC only */ |
| 245 | #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) /* R4[04]00MC only */ |
| 246 | #define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */ |
| 247 | #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) /* R4[04]00MC only */ |
| 248 | #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* R10000 only */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 249 | |
| 250 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | |
Steven J. Hill | 05857c6 | 2012-09-13 16:51:46 -0500 | [diff] [blame] | 252 | #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) |
| 254 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 255 | #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | #endif /* _ASM_PGTABLE_BITS_H */ |