blob: abb5bdecd509acbe13f0b70c78b65a2607becd1d [file] [log] [blame]
viresh kumar986435e2010-04-01 12:30:49 +01001/*
2 * arch/arm/plat-spear/time.c
3 *
Shiraz Hashim5c881d92011-02-16 07:40:32 +01004 * Copyright (C) 2010 ST Microelectronics
viresh kumar986435e2010-04-01 12:30:49 +01005 * Shiraz Hashim<shiraz.hashim@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk.h>
13#include <linux/clockchips.h>
14#include <linux/clocksource.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/time.h>
21#include <linux/irq.h>
22#include <asm/mach/time.h>
viresh kumar986435e2010-04-01 12:30:49 +010023#include <mach/generic.h>
viresh kumar410782b2011-03-07 05:57:01 +010024#include <mach/hardware.h>
25#include <mach/irqs.h>
viresh kumar986435e2010-04-01 12:30:49 +010026
27/*
28 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
29 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
30 * they share same functional clock. Any change in one's functional clock will
31 * also affect other timer.
32 */
33
34#define CLKEVT 0 /* gpt0, channel0 as clockevent */
35#define CLKSRC 1 /* gpt0, channel1 as clocksource */
36
37/* Register offsets, x is channel number */
38#define CR(x) ((x) * 0x80 + 0x80)
39#define IR(x) ((x) * 0x80 + 0x84)
40#define LOAD(x) ((x) * 0x80 + 0x88)
41#define COUNT(x) ((x) * 0x80 + 0x8C)
42
43/* Reg bit definitions */
44#define CTRL_INT_ENABLE 0x0100
45#define CTRL_ENABLE 0x0020
46#define CTRL_ONE_SHOT 0x0010
47
48#define CTRL_PRESCALER1 0x0
49#define CTRL_PRESCALER2 0x1
50#define CTRL_PRESCALER4 0x2
51#define CTRL_PRESCALER8 0x3
52#define CTRL_PRESCALER16 0x4
53#define CTRL_PRESCALER32 0x5
54#define CTRL_PRESCALER64 0x6
55#define CTRL_PRESCALER128 0x7
56#define CTRL_PRESCALER256 0x8
57
58#define INT_STATUS 0x1
59
Linus Walleij4bd48942010-07-19 20:55:46 +010060/*
61 * Minimum clocksource/clockevent timer range in seconds
62 */
63#define SPEAR_MIN_RANGE 4
64
viresh kumar986435e2010-04-01 12:30:49 +010065static __iomem void *gpt_base;
66static struct clk *gpt_clk;
67
68static void clockevent_set_mode(enum clock_event_mode mode,
69 struct clock_event_device *clk_event_dev);
70static int clockevent_next_event(unsigned long evt,
71 struct clock_event_device *clk_event_dev);
72
viresh kumar986435e2010-04-01 12:30:49 +010073static void spear_clocksource_init(void)
74{
75 u32 tick_rate;
76 u16 val;
77
78 /* program the prescaler (/256)*/
79 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
80
81 /* find out actual clock driving Timer */
82 tick_rate = clk_get_rate(gpt_clk);
83 tick_rate >>= CTRL_PRESCALER256;
84
85 writew(0xFFFF, gpt_base + LOAD(CLKSRC));
86
87 val = readw(gpt_base + CR(CLKSRC));
88 val &= ~CTRL_ONE_SHOT; /* autoreload mode */
89 val |= CTRL_ENABLE ;
90 writew(val, gpt_base + CR(CLKSRC));
91
viresh kumar986435e2010-04-01 12:30:49 +010092 /* register the clocksource */
Russell Kingd6e15d72011-05-08 17:10:14 +010093 clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
94 200, 16, clocksource_mmio_readw_up);
viresh kumar986435e2010-04-01 12:30:49 +010095}
96
97static struct clock_event_device clkevt = {
98 .name = "tmr0",
99 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
100 .set_mode = clockevent_set_mode,
101 .set_next_event = clockevent_next_event,
102 .shift = 0, /* to be computed */
103};
104
105static void clockevent_set_mode(enum clock_event_mode mode,
106 struct clock_event_device *clk_event_dev)
107{
108 u32 period;
109 u16 val;
110
111 /* stop the timer */
112 val = readw(gpt_base + CR(CLKEVT));
113 val &= ~CTRL_ENABLE;
114 writew(val, gpt_base + CR(CLKEVT));
115
116 switch (mode) {
117 case CLOCK_EVT_MODE_PERIODIC:
118 period = clk_get_rate(gpt_clk) / HZ;
119 period >>= CTRL_PRESCALER16;
120 writew(period, gpt_base + LOAD(CLKEVT));
121
122 val = readw(gpt_base + CR(CLKEVT));
123 val &= ~CTRL_ONE_SHOT;
124 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
125 writew(val, gpt_base + CR(CLKEVT));
126
127 break;
128 case CLOCK_EVT_MODE_ONESHOT:
129 val = readw(gpt_base + CR(CLKEVT));
130 val |= CTRL_ONE_SHOT;
131 writew(val, gpt_base + CR(CLKEVT));
132
133 break;
134 case CLOCK_EVT_MODE_UNUSED:
135 case CLOCK_EVT_MODE_SHUTDOWN:
136 case CLOCK_EVT_MODE_RESUME:
137
138 break;
139 default:
140 pr_err("Invalid mode requested\n");
141 break;
142 }
143}
144
145static int clockevent_next_event(unsigned long cycles,
146 struct clock_event_device *clk_event_dev)
147{
Gilles Chanteperdrix12021372012-02-24 22:50:50 +0100148 u16 val = readw(gpt_base + CR(CLKEVT));
149
150 if (val & CTRL_ENABLE)
151 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
viresh kumar986435e2010-04-01 12:30:49 +0100152
153 writew(cycles, gpt_base + LOAD(CLKEVT));
154
viresh kumar986435e2010-04-01 12:30:49 +0100155 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
156 writew(val, gpt_base + CR(CLKEVT));
157
158 return 0;
159}
160
161static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
162{
163 struct clock_event_device *evt = &clkevt;
164
165 writew(INT_STATUS, gpt_base + IR(CLKEVT));
166
167 evt->event_handler(evt);
168
169 return IRQ_HANDLED;
170}
171
172static struct irqaction spear_timer_irq = {
173 .name = "timer",
174 .flags = IRQF_DISABLED | IRQF_TIMER,
175 .handler = spear_timer_interrupt
176};
177
178static void __init spear_clockevent_init(void)
179{
180 u32 tick_rate;
181
182 /* program the prescaler */
183 writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
184
185 tick_rate = clk_get_rate(gpt_clk);
186 tick_rate >>= CTRL_PRESCALER16;
187
Linus Walleij4bd48942010-07-19 20:55:46 +0100188 clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
viresh kumar986435e2010-04-01 12:30:49 +0100189
190 clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
191 &clkevt);
192 clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
193
194 clkevt.cpumask = cpumask_of(0);
195
196 clockevents_register_device(&clkevt);
197
198 setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
199}
200
201void __init spear_setup_timer(void)
202{
Shiraz Hashim5c881d92011-02-16 07:40:32 +0100203 int ret;
viresh kumar986435e2010-04-01 12:30:49 +0100204
205 if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
206 pr_err("%s:cannot get IO addr\n", __func__);
207 return;
208 }
209
210 gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
211 if (!gpt_base) {
212 pr_err("%s:ioremap failed for gpt\n", __func__);
213 goto err_mem;
214 }
215
216 gpt_clk = clk_get_sys("gpt0", NULL);
217 if (!gpt_clk) {
218 pr_err("%s:couldn't get clk for gpt\n", __func__);
219 goto err_iomap;
220 }
221
Shiraz Hashim5c881d92011-02-16 07:40:32 +0100222 ret = clk_enable(gpt_clk);
223 if (ret < 0) {
224 pr_err("%s:couldn't enable gpt clock\n", __func__);
225 goto err_clk;
viresh kumar986435e2010-04-01 12:30:49 +0100226 }
227
viresh kumar986435e2010-04-01 12:30:49 +0100228 spear_clockevent_init();
229 spear_clocksource_init();
230
231 return;
232
Shiraz Hashim5c881d92011-02-16 07:40:32 +0100233err_clk:
234 clk_put(gpt_clk);
viresh kumar986435e2010-04-01 12:30:49 +0100235err_iomap:
236 iounmap(gpt_base);
viresh kumar986435e2010-04-01 12:30:49 +0100237err_mem:
238 release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
239}