Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/radeon_drm.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
| 31 | #include "radeon_reg.h" |
| 32 | |
| 33 | /* |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 34 | * GART |
| 35 | * The GART (Graphics Aperture Remapping Table) is an aperture |
| 36 | * in the GPU's address space. System pages can be mapped into |
| 37 | * the aperture and look like contiguous pages from the GPU's |
| 38 | * perspective. A page table maps the pages in the aperture |
| 39 | * to the actual backing pages in system memory. |
| 40 | * |
| 41 | * Radeon GPUs support both an internal GART, as described above, |
| 42 | * and AGP. AGP works similarly, but the GART table is configured |
| 43 | * and maintained by the northbridge rather than the driver. |
| 44 | * Radeon hw has a separate AGP aperture that is programmed to |
| 45 | * point to the AGP aperture provided by the northbridge and the |
| 46 | * requests are passed through to the northbridge aperture. |
| 47 | * Both AGP and internal GART can be used at the same time, however |
| 48 | * that is not currently supported by the driver. |
| 49 | * |
| 50 | * This file handles the common internal GART management. |
| 51 | */ |
| 52 | |
| 53 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 54 | * Common GART table functions. |
| 55 | */ |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 56 | /** |
| 57 | * radeon_gart_table_ram_alloc - allocate system ram for gart page table |
| 58 | * |
| 59 | * @rdev: radeon_device pointer |
| 60 | * |
| 61 | * Allocate system memory for GART page table |
| 62 | * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the |
| 63 | * gart table to be in system memory. |
| 64 | * Returns 0 for success, -ENOMEM for failure. |
| 65 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 66 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev) |
| 67 | { |
| 68 | void *ptr; |
| 69 | |
| 70 | ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, |
| 71 | &rdev->gart.table_addr); |
| 72 | if (ptr == NULL) { |
| 73 | return -ENOMEM; |
| 74 | } |
| 75 | #ifdef CONFIG_X86 |
| 76 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || |
| 77 | rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| 78 | set_memory_uc((unsigned long)ptr, |
| 79 | rdev->gart.table_size >> PAGE_SHIFT); |
| 80 | } |
| 81 | #endif |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 82 | rdev->gart.ptr = ptr; |
| 83 | memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 84 | return 0; |
| 85 | } |
| 86 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 87 | /** |
| 88 | * radeon_gart_table_ram_free - free system ram for gart page table |
| 89 | * |
| 90 | * @rdev: radeon_device pointer |
| 91 | * |
| 92 | * Free system memory for GART page table |
| 93 | * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the |
| 94 | * gart table to be in system memory. |
| 95 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 96 | void radeon_gart_table_ram_free(struct radeon_device *rdev) |
| 97 | { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 98 | if (rdev->gart.ptr == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 99 | return; |
| 100 | } |
| 101 | #ifdef CONFIG_X86 |
| 102 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || |
| 103 | rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 104 | set_memory_wb((unsigned long)rdev->gart.ptr, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | rdev->gart.table_size >> PAGE_SHIFT); |
| 106 | } |
| 107 | #endif |
| 108 | pci_free_consistent(rdev->pdev, rdev->gart.table_size, |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 109 | (void *)rdev->gart.ptr, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | rdev->gart.table_addr); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 111 | rdev->gart.ptr = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 112 | rdev->gart.table_addr = 0; |
| 113 | } |
| 114 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 115 | /** |
| 116 | * radeon_gart_table_vram_alloc - allocate vram for gart page table |
| 117 | * |
| 118 | * @rdev: radeon_device pointer |
| 119 | * |
| 120 | * Allocate video memory for GART page table |
| 121 | * (pcie r4xx, r5xx+). These asics require the |
| 122 | * gart table to be in video memory. |
| 123 | * Returns 0 for success, error for failure. |
| 124 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 125 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev) |
| 126 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 127 | int r; |
| 128 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 129 | if (rdev->gart.robj == NULL) { |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 130 | r = radeon_bo_create(rdev, rdev->gart.table_size, |
Alex Deucher | 268b251 | 2010-11-17 19:00:26 -0500 | [diff] [blame] | 131 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 132 | NULL, &rdev->gart.robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 133 | if (r) { |
| 134 | return r; |
| 135 | } |
| 136 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 137 | return 0; |
| 138 | } |
| 139 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 140 | /** |
| 141 | * radeon_gart_table_vram_pin - pin gart page table in vram |
| 142 | * |
| 143 | * @rdev: radeon_device pointer |
| 144 | * |
| 145 | * Pin the GART page table in vram so it will not be moved |
| 146 | * by the memory manager (pcie r4xx, r5xx+). These asics require the |
| 147 | * gart table to be in video memory. |
| 148 | * Returns 0 for success, error for failure. |
| 149 | */ |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 150 | int radeon_gart_table_vram_pin(struct radeon_device *rdev) |
| 151 | { |
| 152 | uint64_t gpu_addr; |
| 153 | int r; |
| 154 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 155 | r = radeon_bo_reserve(rdev->gart.robj, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 156 | if (unlikely(r != 0)) |
| 157 | return r; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 158 | r = radeon_bo_pin(rdev->gart.robj, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 159 | RADEON_GEM_DOMAIN_VRAM, &gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 160 | if (r) { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 161 | radeon_bo_unreserve(rdev->gart.robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 162 | return r; |
| 163 | } |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 164 | r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 165 | if (r) |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 166 | radeon_bo_unpin(rdev->gart.robj); |
| 167 | radeon_bo_unreserve(rdev->gart.robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 168 | rdev->gart.table_addr = gpu_addr; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 169 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 170 | } |
| 171 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 172 | /** |
| 173 | * radeon_gart_table_vram_unpin - unpin gart page table in vram |
| 174 | * |
| 175 | * @rdev: radeon_device pointer |
| 176 | * |
| 177 | * Unpin the GART page table in vram (pcie r4xx, r5xx+). |
| 178 | * These asics require the gart table to be in video memory. |
| 179 | */ |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 180 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 182 | int r; |
| 183 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 184 | if (rdev->gart.robj == NULL) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 185 | return; |
| 186 | } |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 187 | r = radeon_bo_reserve(rdev->gart.robj, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 188 | if (likely(r == 0)) { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 189 | radeon_bo_kunmap(rdev->gart.robj); |
| 190 | radeon_bo_unpin(rdev->gart.robj); |
| 191 | radeon_bo_unreserve(rdev->gart.robj); |
| 192 | rdev->gart.ptr = NULL; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 193 | } |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 194 | } |
| 195 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 196 | /** |
| 197 | * radeon_gart_table_vram_free - free gart page table vram |
| 198 | * |
| 199 | * @rdev: radeon_device pointer |
| 200 | * |
| 201 | * Free the video memory used for the GART page table |
| 202 | * (pcie r4xx, r5xx+). These asics require the gart table to |
| 203 | * be in video memory. |
| 204 | */ |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 205 | void radeon_gart_table_vram_free(struct radeon_device *rdev) |
| 206 | { |
| 207 | if (rdev->gart.robj == NULL) { |
| 208 | return; |
| 209 | } |
| 210 | radeon_gart_table_vram_unpin(rdev); |
| 211 | radeon_bo_unref(&rdev->gart.robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 212 | } |
| 213 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 214 | /* |
| 215 | * Common gart functions. |
| 216 | */ |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 217 | /** |
| 218 | * radeon_gart_unbind - unbind pages from the gart page table |
| 219 | * |
| 220 | * @rdev: radeon_device pointer |
| 221 | * @offset: offset into the GPU's gart aperture |
| 222 | * @pages: number of pages to unbind |
| 223 | * |
| 224 | * Unbinds the requested pages from the gart page table and |
| 225 | * replaces them with the dummy page (all asics). |
| 226 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 227 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 228 | int pages) |
| 229 | { |
| 230 | unsigned t; |
| 231 | unsigned p; |
| 232 | int i, j; |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 233 | u64 page_base; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 234 | |
| 235 | if (!rdev->gart.ready) { |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 236 | WARN(1, "trying to unbind memory from uninitialized GART !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 237 | return; |
| 238 | } |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 239 | t = offset / RADEON_GPU_PAGE_SIZE; |
| 240 | p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 241 | for (i = 0; i < pages; i++, p++) { |
| 242 | if (rdev->gart.pages[p]) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 243 | rdev->gart.pages[p] = NULL; |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 244 | rdev->gart.pages_addr[p] = rdev->dummy_page.addr; |
| 245 | page_base = rdev->gart.pages_addr[p]; |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 246 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 247 | if (rdev->gart.ptr) { |
| 248 | radeon_gart_set_page(rdev, t, page_base); |
| 249 | } |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 250 | page_base += RADEON_GPU_PAGE_SIZE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | } |
| 252 | } |
| 253 | } |
| 254 | mb(); |
| 255 | radeon_gart_tlb_flush(rdev); |
| 256 | } |
| 257 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 258 | /** |
| 259 | * radeon_gart_bind - bind pages into the gart page table |
| 260 | * |
| 261 | * @rdev: radeon_device pointer |
| 262 | * @offset: offset into the GPU's gart aperture |
| 263 | * @pages: number of pages to bind |
| 264 | * @pagelist: pages to bind |
| 265 | * @dma_addr: DMA addresses of pages |
| 266 | * |
| 267 | * Binds the requested pages to the gart page table |
| 268 | * (all asics). |
| 269 | * Returns 0 for success, -EINVAL for failure. |
| 270 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 272 | int pages, struct page **pagelist, dma_addr_t *dma_addr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 273 | { |
| 274 | unsigned t; |
| 275 | unsigned p; |
| 276 | uint64_t page_base; |
| 277 | int i, j; |
| 278 | |
| 279 | if (!rdev->gart.ready) { |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 280 | WARN(1, "trying to bind memory to uninitialized GART !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | return -EINVAL; |
| 282 | } |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 283 | t = offset / RADEON_GPU_PAGE_SIZE; |
| 284 | p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 285 | |
| 286 | for (i = 0; i < pages; i++, p++) { |
Konrad Rzeszutek Wilk | c52494f | 2011-10-17 17:15:08 -0400 | [diff] [blame] | 287 | rdev->gart.pages_addr[p] = dma_addr[i]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 288 | rdev->gart.pages[p] = pagelist[i]; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 289 | if (rdev->gart.ptr) { |
| 290 | page_base = rdev->gart.pages_addr[p]; |
| 291 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
| 292 | radeon_gart_set_page(rdev, t, page_base); |
| 293 | page_base += RADEON_GPU_PAGE_SIZE; |
| 294 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 295 | } |
| 296 | } |
| 297 | mb(); |
| 298 | radeon_gart_tlb_flush(rdev); |
| 299 | return 0; |
| 300 | } |
| 301 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 302 | /** |
| 303 | * radeon_gart_restore - bind all pages in the gart page table |
| 304 | * |
| 305 | * @rdev: radeon_device pointer |
| 306 | * |
| 307 | * Binds all pages in the gart page table (all asics). |
| 308 | * Used to rebuild the gart table on device startup or resume. |
| 309 | */ |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 310 | void radeon_gart_restore(struct radeon_device *rdev) |
| 311 | { |
| 312 | int i, j, t; |
| 313 | u64 page_base; |
| 314 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 315 | if (!rdev->gart.ptr) { |
| 316 | return; |
| 317 | } |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 318 | for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) { |
| 319 | page_base = rdev->gart.pages_addr[i]; |
| 320 | for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { |
| 321 | radeon_gart_set_page(rdev, t, page_base); |
| 322 | page_base += RADEON_GPU_PAGE_SIZE; |
| 323 | } |
| 324 | } |
| 325 | mb(); |
| 326 | radeon_gart_tlb_flush(rdev); |
| 327 | } |
| 328 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 329 | /** |
| 330 | * radeon_gart_init - init the driver info for managing the gart |
| 331 | * |
| 332 | * @rdev: radeon_device pointer |
| 333 | * |
| 334 | * Allocate the dummy page and init the gart driver info (all asics). |
| 335 | * Returns 0 for success, error for failure. |
| 336 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 337 | int radeon_gart_init(struct radeon_device *rdev) |
| 338 | { |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 339 | int r, i; |
| 340 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 341 | if (rdev->gart.pages) { |
| 342 | return 0; |
| 343 | } |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 344 | /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ |
| 345 | if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 346 | DRM_ERROR("Page size is smaller than GPU page size!\n"); |
| 347 | return -EINVAL; |
| 348 | } |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 349 | r = radeon_dummy_page_init(rdev); |
| 350 | if (r) |
| 351 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 352 | /* Compute table size */ |
| 353 | rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 354 | rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 355 | DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", |
| 356 | rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); |
| 357 | /* Allocate pages table */ |
Christian König | 59240ee | 2012-10-23 15:53:17 +0200 | [diff] [blame] | 358 | rdev->gart.pages = vzalloc(sizeof(void *) * rdev->gart.num_cpu_pages); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 359 | if (rdev->gart.pages == NULL) { |
| 360 | radeon_gart_fini(rdev); |
| 361 | return -ENOMEM; |
| 362 | } |
Christian König | 59240ee | 2012-10-23 15:53:17 +0200 | [diff] [blame] | 363 | rdev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) * |
| 364 | rdev->gart.num_cpu_pages); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 365 | if (rdev->gart.pages_addr == NULL) { |
| 366 | radeon_gart_fini(rdev); |
| 367 | return -ENOMEM; |
| 368 | } |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 369 | /* set GART entry to point to the dummy page by default */ |
| 370 | for (i = 0; i < rdev->gart.num_cpu_pages; i++) { |
| 371 | rdev->gart.pages_addr[i] = rdev->dummy_page.addr; |
| 372 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 373 | return 0; |
| 374 | } |
| 375 | |
Alex Deucher | 03eec93 | 2012-07-17 14:02:39 -0400 | [diff] [blame] | 376 | /** |
| 377 | * radeon_gart_fini - tear down the driver info for managing the gart |
| 378 | * |
| 379 | * @rdev: radeon_device pointer |
| 380 | * |
| 381 | * Tear down the gart driver info and free the dummy page (all asics). |
| 382 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | void radeon_gart_fini(struct radeon_device *rdev) |
| 384 | { |
| 385 | if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { |
| 386 | /* unbind pages */ |
| 387 | radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); |
| 388 | } |
| 389 | rdev->gart.ready = false; |
Christian König | 59240ee | 2012-10-23 15:53:17 +0200 | [diff] [blame] | 390 | vfree(rdev->gart.pages); |
| 391 | vfree(rdev->gart.pages_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 392 | rdev->gart.pages = NULL; |
| 393 | rdev->gart.pages_addr = NULL; |
Alex Deucher | 92656d7 | 2011-04-12 13:32:13 -0400 | [diff] [blame] | 394 | |
| 395 | radeon_dummy_page_fini(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 396 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 397 | |
| 398 | /* |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 399 | * GPUVM |
| 400 | * GPUVM is similar to the legacy gart on older asics, however |
| 401 | * rather than there being a single global gart table |
| 402 | * for the entire GPU, there are multiple VM page tables active |
| 403 | * at any given time. The VM page tables can contain a mix |
| 404 | * vram pages and system memory pages and system memory pages |
| 405 | * can be mapped as snooped (cached system pages) or unsnooped |
| 406 | * (uncached system pages). |
| 407 | * Each VM has an ID associated with it and there is a page table |
| 408 | * associated with each VMID. When execting a command buffer, |
| 409 | * the kernel tells the the ring what VMID to use for that command |
| 410 | * buffer. VMIDs are allocated dynamically as commands are submitted. |
| 411 | * The userspace drivers maintain their own address space and the kernel |
| 412 | * sets up their pages tables accordingly when they submit their |
| 413 | * command buffers and a VMID is assigned. |
| 414 | * Cayman/Trinity support up to 8 active VMs at any given time; |
| 415 | * SI supports 16. |
| 416 | */ |
| 417 | |
| 418 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 419 | * vm helpers |
| 420 | * |
| 421 | * TODO bind a default page at vm initialization for default address |
| 422 | */ |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 423 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 424 | /** |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 425 | * radeon_vm_num_pde - return the number of page directory entries |
| 426 | * |
| 427 | * @rdev: radeon_device pointer |
| 428 | * |
| 429 | * Calculate the number of page directory entries (cayman+). |
| 430 | */ |
| 431 | static unsigned radeon_vm_num_pdes(struct radeon_device *rdev) |
| 432 | { |
| 433 | return rdev->vm_manager.max_pfn >> RADEON_VM_BLOCK_SIZE; |
| 434 | } |
| 435 | |
| 436 | /** |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 437 | * radeon_vm_directory_size - returns the size of the page directory in bytes |
| 438 | * |
| 439 | * @rdev: radeon_device pointer |
| 440 | * |
| 441 | * Calculate the size of the page directory in bytes (cayman+). |
| 442 | */ |
| 443 | static unsigned radeon_vm_directory_size(struct radeon_device *rdev) |
| 444 | { |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 445 | return RADEON_GPU_PAGE_ALIGN(radeon_vm_num_pdes(rdev) * 8); |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | /** |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 449 | * radeon_vm_manager_init - init the vm manager |
| 450 | * |
| 451 | * @rdev: radeon_device pointer |
| 452 | * |
| 453 | * Init the vm manager (cayman+). |
| 454 | * Returns 0 for success, error for failure. |
| 455 | */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 456 | int radeon_vm_manager_init(struct radeon_device *rdev) |
| 457 | { |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 458 | struct radeon_vm *vm; |
| 459 | struct radeon_bo_va *bo_va; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 460 | int r; |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 461 | unsigned size; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 462 | |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 463 | if (!rdev->vm_manager.enabled) { |
Dave Airlie | e6b0b6a | 2012-07-20 00:53:28 -0400 | [diff] [blame] | 464 | /* allocate enough for 2 full VM pts */ |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 465 | size = radeon_vm_directory_size(rdev); |
| 466 | size += rdev->vm_manager.max_pfn * 8; |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 467 | size *= 2; |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 468 | r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager, |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 469 | RADEON_GPU_PAGE_ALIGN(size), |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 470 | RADEON_GEM_DOMAIN_VRAM); |
| 471 | if (r) { |
| 472 | dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n", |
| 473 | (rdev->vm_manager.max_pfn * 8) >> 10); |
| 474 | return r; |
| 475 | } |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 476 | |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 477 | r = radeon_asic_vm_init(rdev); |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 478 | if (r) |
| 479 | return r; |
Christian König | 089a786 | 2012-08-11 11:54:05 +0200 | [diff] [blame] | 480 | |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 481 | rdev->vm_manager.enabled = true; |
| 482 | |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 483 | r = radeon_sa_bo_manager_start(rdev, &rdev->vm_manager.sa_manager); |
| 484 | if (r) |
| 485 | return r; |
| 486 | } |
| 487 | |
| 488 | /* restore page table */ |
| 489 | list_for_each_entry(vm, &rdev->vm_manager.lru_vm, list) { |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 490 | if (vm->page_directory == NULL) |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 491 | continue; |
| 492 | |
| 493 | list_for_each_entry(bo_va, &vm->va, vm_list) { |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 494 | bo_va->valid = false; |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 495 | } |
| 496 | } |
| 497 | return 0; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 498 | } |
| 499 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 500 | /** |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 501 | * radeon_vm_free_pt - free the page table for a specific vm |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 502 | * |
| 503 | * @rdev: radeon_device pointer |
| 504 | * @vm: vm to unbind |
| 505 | * |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 506 | * Free the page table of a specific vm (cayman+). |
| 507 | * |
| 508 | * Global and local mutex must be lock! |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 509 | */ |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 510 | static void radeon_vm_free_pt(struct radeon_device *rdev, |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 511 | struct radeon_vm *vm) |
| 512 | { |
| 513 | struct radeon_bo_va *bo_va; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 514 | int i; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 515 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 516 | if (!vm->page_directory) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 517 | return; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 518 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 519 | list_del_init(&vm->list); |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 520 | radeon_sa_bo_free(rdev, &vm->page_directory, vm->fence); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 521 | |
| 522 | list_for_each_entry(bo_va, &vm->va, vm_list) { |
| 523 | bo_va->valid = false; |
| 524 | } |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 525 | |
| 526 | if (vm->page_tables == NULL) |
| 527 | return; |
| 528 | |
| 529 | for (i = 0; i < radeon_vm_num_pdes(rdev); i++) |
| 530 | radeon_sa_bo_free(rdev, &vm->page_tables[i], vm->fence); |
| 531 | |
| 532 | kfree(vm->page_tables); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 533 | } |
| 534 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 535 | /** |
| 536 | * radeon_vm_manager_fini - tear down the vm manager |
| 537 | * |
| 538 | * @rdev: radeon_device pointer |
| 539 | * |
| 540 | * Tear down the VM manager (cayman+). |
| 541 | */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 542 | void radeon_vm_manager_fini(struct radeon_device *rdev) |
| 543 | { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 544 | struct radeon_vm *vm, *tmp; |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 545 | int i; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 546 | |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 547 | if (!rdev->vm_manager.enabled) |
| 548 | return; |
| 549 | |
Christian König | 36ff39c | 2012-05-09 10:07:08 +0200 | [diff] [blame] | 550 | mutex_lock(&rdev->vm_manager.lock); |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 551 | /* free all allocated page tables */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 552 | list_for_each_entry_safe(vm, tmp, &rdev->vm_manager.lru_vm, list) { |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 553 | mutex_lock(&vm->mutex); |
| 554 | radeon_vm_free_pt(rdev, vm); |
| 555 | mutex_unlock(&vm->mutex); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 556 | } |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 557 | for (i = 0; i < RADEON_NUM_VM; ++i) { |
| 558 | radeon_fence_unref(&rdev->vm_manager.active[i]); |
| 559 | } |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 560 | radeon_asic_vm_fini(rdev); |
Christian König | 36ff39c | 2012-05-09 10:07:08 +0200 | [diff] [blame] | 561 | mutex_unlock(&rdev->vm_manager.lock); |
Christian König | c6105f2 | 2012-07-05 14:32:00 +0200 | [diff] [blame] | 562 | |
| 563 | radeon_sa_bo_manager_suspend(rdev, &rdev->vm_manager.sa_manager); |
| 564 | radeon_sa_bo_manager_fini(rdev, &rdev->vm_manager.sa_manager); |
| 565 | rdev->vm_manager.enabled = false; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 566 | } |
| 567 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 568 | /** |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 569 | * radeon_vm_evict - evict page table to make room for new one |
| 570 | * |
| 571 | * @rdev: radeon_device pointer |
| 572 | * @vm: VM we want to allocate something for |
| 573 | * |
| 574 | * Evict a VM from the lru, making sure that it isn't @vm. (cayman+). |
| 575 | * Returns 0 for success, -ENOMEM for failure. |
| 576 | * |
| 577 | * Global and local mutex must be locked! |
| 578 | */ |
Alex Deucher | 1518d7f | 2012-10-17 12:42:13 -0400 | [diff] [blame] | 579 | static int radeon_vm_evict(struct radeon_device *rdev, struct radeon_vm *vm) |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 580 | { |
| 581 | struct radeon_vm *vm_evict; |
| 582 | |
| 583 | if (list_empty(&rdev->vm_manager.lru_vm)) |
| 584 | return -ENOMEM; |
| 585 | |
| 586 | vm_evict = list_first_entry(&rdev->vm_manager.lru_vm, |
| 587 | struct radeon_vm, list); |
| 588 | if (vm_evict == vm) |
| 589 | return -ENOMEM; |
| 590 | |
| 591 | mutex_lock(&vm_evict->mutex); |
| 592 | radeon_vm_free_pt(rdev, vm_evict); |
| 593 | mutex_unlock(&vm_evict->mutex); |
| 594 | return 0; |
| 595 | } |
| 596 | |
| 597 | /** |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 598 | * radeon_vm_alloc_pt - allocates a page table for a VM |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 599 | * |
| 600 | * @rdev: radeon_device pointer |
| 601 | * @vm: vm to bind |
| 602 | * |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 603 | * Allocate a page table for the requested vm (cayman+). |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 604 | * Returns 0 for success, error for failure. |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 605 | * |
| 606 | * Global and local mutex must be locked! |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 607 | */ |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 608 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 609 | { |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 610 | unsigned pd_size, pts_size; |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 611 | u64 *pd_addr; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 612 | int r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 613 | |
| 614 | if (vm == NULL) { |
| 615 | return -EINVAL; |
| 616 | } |
| 617 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 618 | if (vm->page_directory != NULL) { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 619 | return 0; |
| 620 | } |
| 621 | |
| 622 | retry: |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 623 | pd_size = RADEON_GPU_PAGE_ALIGN(radeon_vm_directory_size(rdev)); |
| 624 | r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager, |
| 625 | &vm->page_directory, pd_size, |
| 626 | RADEON_GPU_PAGE_SIZE, false); |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 627 | if (r == -ENOMEM) { |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 628 | r = radeon_vm_evict(rdev, vm); |
| 629 | if (r) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 630 | return r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 631 | goto retry; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 632 | |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 633 | } else if (r) { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 634 | return r; |
| 635 | } |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 636 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 637 | vm->pd_gpu_addr = radeon_sa_bo_gpu_addr(vm->page_directory); |
| 638 | |
| 639 | /* Initially clear the page directory */ |
| 640 | pd_addr = radeon_sa_bo_cpu_addr(vm->page_directory); |
| 641 | memset(pd_addr, 0, pd_size); |
| 642 | |
| 643 | pts_size = radeon_vm_num_pdes(rdev) * sizeof(struct radeon_sa_bo *); |
| 644 | vm->page_tables = kzalloc(pts_size, GFP_KERNEL); |
| 645 | |
| 646 | if (vm->page_tables == NULL) { |
| 647 | DRM_ERROR("Cannot allocate memory for page table array\n"); |
| 648 | radeon_sa_bo_free(rdev, &vm->page_directory, vm->fence); |
| 649 | return -ENOMEM; |
| 650 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 651 | |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 652 | return 0; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 653 | } |
| 654 | |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 655 | /** |
Christian König | 13e55c3 | 2012-10-09 13:31:19 +0200 | [diff] [blame] | 656 | * radeon_vm_add_to_lru - add VMs page table to LRU list |
| 657 | * |
| 658 | * @rdev: radeon_device pointer |
| 659 | * @vm: vm to add to LRU |
| 660 | * |
| 661 | * Add the allocated page table to the LRU list (cayman+). |
| 662 | * |
| 663 | * Global mutex must be locked! |
| 664 | */ |
| 665 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm) |
| 666 | { |
| 667 | list_del_init(&vm->list); |
| 668 | list_add_tail(&vm->list, &rdev->vm_manager.lru_vm); |
| 669 | } |
| 670 | |
| 671 | /** |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 672 | * radeon_vm_grab_id - allocate the next free VMID |
| 673 | * |
| 674 | * @rdev: radeon_device pointer |
| 675 | * @vm: vm to allocate id for |
| 676 | * @ring: ring we want to submit job to |
| 677 | * |
| 678 | * Allocate an id for the vm (cayman+). |
| 679 | * Returns the fence we need to sync to (if any). |
| 680 | * |
| 681 | * Global and local mutex must be locked! |
| 682 | */ |
| 683 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
| 684 | struct radeon_vm *vm, int ring) |
| 685 | { |
| 686 | struct radeon_fence *best[RADEON_NUM_RINGS] = {}; |
| 687 | unsigned choices[2] = {}; |
| 688 | unsigned i; |
| 689 | |
| 690 | /* check if the id is still valid */ |
| 691 | if (vm->fence && vm->fence == rdev->vm_manager.active[vm->id]) |
| 692 | return NULL; |
| 693 | |
| 694 | /* we definately need to flush */ |
| 695 | radeon_fence_unref(&vm->last_flush); |
| 696 | |
| 697 | /* skip over VMID 0, since it is the system VM */ |
| 698 | for (i = 1; i < rdev->vm_manager.nvm; ++i) { |
| 699 | struct radeon_fence *fence = rdev->vm_manager.active[i]; |
| 700 | |
| 701 | if (fence == NULL) { |
| 702 | /* found a free one */ |
| 703 | vm->id = i; |
| 704 | return NULL; |
| 705 | } |
| 706 | |
| 707 | if (radeon_fence_is_earlier(fence, best[fence->ring])) { |
| 708 | best[fence->ring] = fence; |
| 709 | choices[fence->ring == ring ? 0 : 1] = i; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | for (i = 0; i < 2; ++i) { |
| 714 | if (choices[i]) { |
| 715 | vm->id = choices[i]; |
| 716 | return rdev->vm_manager.active[choices[i]]; |
| 717 | } |
| 718 | } |
| 719 | |
| 720 | /* should never happen */ |
| 721 | BUG(); |
| 722 | return NULL; |
| 723 | } |
| 724 | |
| 725 | /** |
| 726 | * radeon_vm_fence - remember fence for vm |
| 727 | * |
| 728 | * @rdev: radeon_device pointer |
| 729 | * @vm: vm we want to fence |
| 730 | * @fence: fence to remember |
| 731 | * |
| 732 | * Fence the vm (cayman+). |
| 733 | * Set the fence used to protect page table and id. |
| 734 | * |
| 735 | * Global and local mutex must be locked! |
| 736 | */ |
| 737 | void radeon_vm_fence(struct radeon_device *rdev, |
| 738 | struct radeon_vm *vm, |
| 739 | struct radeon_fence *fence) |
| 740 | { |
| 741 | radeon_fence_unref(&rdev->vm_manager.active[vm->id]); |
| 742 | rdev->vm_manager.active[vm->id] = radeon_fence_ref(fence); |
| 743 | |
| 744 | radeon_fence_unref(&vm->fence); |
| 745 | vm->fence = radeon_fence_ref(fence); |
| 746 | } |
| 747 | |
Christian König | 421ca7a | 2012-09-11 16:10:00 +0200 | [diff] [blame] | 748 | /** |
| 749 | * radeon_vm_bo_find - find the bo_va for a specific vm & bo |
| 750 | * |
| 751 | * @vm: requested vm |
| 752 | * @bo: requested buffer object |
| 753 | * |
| 754 | * Find @bo inside the requested vm (cayman+). |
| 755 | * Search inside the @bos vm list for the requested vm |
| 756 | * Returns the found bo_va or NULL if none is found |
| 757 | * |
| 758 | * Object has to be reserved! |
| 759 | */ |
| 760 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
| 761 | struct radeon_bo *bo) |
| 762 | { |
| 763 | struct radeon_bo_va *bo_va; |
| 764 | |
| 765 | list_for_each_entry(bo_va, &bo->va, bo_list) { |
| 766 | if (bo_va->vm == vm) { |
| 767 | return bo_va; |
| 768 | } |
| 769 | } |
| 770 | return NULL; |
| 771 | } |
| 772 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 773 | /** |
| 774 | * radeon_vm_bo_add - add a bo to a specific vm |
| 775 | * |
| 776 | * @rdev: radeon_device pointer |
| 777 | * @vm: requested vm |
| 778 | * @bo: radeon buffer object |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 779 | * |
| 780 | * Add @bo into the requested vm (cayman+). |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 781 | * Add @bo to the list of bos associated with the vm |
| 782 | * Returns newly added bo_va or NULL for failure |
| 783 | * |
| 784 | * Object has to be reserved! |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 785 | */ |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 786 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
| 787 | struct radeon_vm *vm, |
| 788 | struct radeon_bo *bo) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 789 | { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 790 | struct radeon_bo_va *bo_va; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 791 | |
| 792 | bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); |
| 793 | if (bo_va == NULL) { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 794 | return NULL; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 795 | } |
| 796 | bo_va->vm = vm; |
| 797 | bo_va->bo = bo; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 798 | bo_va->soffset = 0; |
| 799 | bo_va->eoffset = 0; |
| 800 | bo_va->flags = 0; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 801 | bo_va->valid = false; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 802 | bo_va->ref_count = 1; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 803 | INIT_LIST_HEAD(&bo_va->bo_list); |
| 804 | INIT_LIST_HEAD(&bo_va->vm_list); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 805 | |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 806 | mutex_lock(&vm->mutex); |
| 807 | list_add(&bo_va->vm_list, &vm->va); |
| 808 | list_add_tail(&bo_va->bo_list, &bo->va); |
| 809 | mutex_unlock(&vm->mutex); |
| 810 | |
| 811 | return bo_va; |
| 812 | } |
| 813 | |
| 814 | /** |
| 815 | * radeon_vm_bo_set_addr - set bos virtual address inside a vm |
| 816 | * |
| 817 | * @rdev: radeon_device pointer |
| 818 | * @bo_va: bo_va to store the address |
| 819 | * @soffset: requested offset of the buffer in the VM address space |
| 820 | * @flags: attributes of pages (read/write/valid/etc.) |
| 821 | * |
| 822 | * Set offset of @bo_va (cayman+). |
| 823 | * Validate and set the offset requested within the vm address space. |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 824 | * Returns 0 for success, error for failure. |
Christian König | 421ca7a | 2012-09-11 16:10:00 +0200 | [diff] [blame] | 825 | * |
| 826 | * Object has to be reserved! |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 827 | */ |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 828 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
| 829 | struct radeon_bo_va *bo_va, |
| 830 | uint64_t soffset, |
| 831 | uint32_t flags) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 832 | { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 833 | uint64_t size = radeon_bo_size(bo_va->bo); |
| 834 | uint64_t eoffset, last_offset = 0; |
| 835 | struct radeon_vm *vm = bo_va->vm; |
| 836 | struct radeon_bo_va *tmp; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 837 | struct list_head *head; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 838 | unsigned last_pfn; |
| 839 | |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 840 | if (soffset) { |
| 841 | /* make sure object fit at this offset */ |
| 842 | eoffset = soffset + size; |
| 843 | if (soffset >= eoffset) { |
| 844 | return -EINVAL; |
| 845 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 846 | |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 847 | last_pfn = eoffset / RADEON_GPU_PAGE_SIZE; |
| 848 | if (last_pfn > rdev->vm_manager.max_pfn) { |
| 849 | dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n", |
| 850 | last_pfn, rdev->vm_manager.max_pfn); |
| 851 | return -EINVAL; |
| 852 | } |
| 853 | |
| 854 | } else { |
| 855 | eoffset = last_pfn = 0; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 856 | } |
| 857 | |
| 858 | mutex_lock(&vm->mutex); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 859 | head = &vm->va; |
| 860 | last_offset = 0; |
| 861 | list_for_each_entry(tmp, &vm->va, vm_list) { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 862 | if (bo_va == tmp) { |
| 863 | /* skip over currently modified bo */ |
| 864 | continue; |
| 865 | } |
| 866 | |
| 867 | if (soffset >= last_offset && eoffset <= tmp->soffset) { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 868 | /* bo can be added before this one */ |
| 869 | break; |
| 870 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 871 | if (eoffset > tmp->soffset && soffset < tmp->eoffset) { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 872 | /* bo and tmp overlap, invalid offset */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 873 | dev_err(rdev->dev, "bo %p va 0x%08X conflict with (bo %p 0x%08X 0x%08X)\n", |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 874 | bo_va->bo, (unsigned)bo_va->soffset, tmp->bo, |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 875 | (unsigned)tmp->soffset, (unsigned)tmp->eoffset); |
| 876 | mutex_unlock(&vm->mutex); |
| 877 | return -EINVAL; |
| 878 | } |
| 879 | last_offset = tmp->eoffset; |
| 880 | head = &tmp->vm_list; |
| 881 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 882 | |
| 883 | bo_va->soffset = soffset; |
| 884 | bo_va->eoffset = eoffset; |
| 885 | bo_va->flags = flags; |
| 886 | bo_va->valid = false; |
| 887 | list_move(&bo_va->vm_list, head); |
| 888 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 889 | mutex_unlock(&vm->mutex); |
| 890 | return 0; |
| 891 | } |
| 892 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 893 | /** |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 894 | * radeon_vm_map_gart - get the physical address of a gart page |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 895 | * |
| 896 | * @rdev: radeon_device pointer |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 897 | * @addr: the unmapped addr |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 898 | * |
| 899 | * Look up the physical address of the page that the pte resolves |
| 900 | * to (cayman+). |
| 901 | * Returns the physical address of the page. |
| 902 | */ |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 903 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 904 | { |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 905 | uint64_t result; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 906 | |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 907 | /* page table offset */ |
| 908 | result = rdev->gart.pages_addr[addr >> PAGE_SHIFT]; |
| 909 | |
| 910 | /* in case cpu page size != gpu page size*/ |
| 911 | result |= addr & (~PAGE_MASK); |
| 912 | |
| 913 | return result; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 914 | } |
| 915 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 916 | /** |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 917 | * radeon_vm_update_pdes - make sure that page directory is valid |
| 918 | * |
| 919 | * @rdev: radeon_device pointer |
| 920 | * @vm: requested vm |
| 921 | * @start: start of GPU address range |
| 922 | * @end: end of GPU address range |
| 923 | * |
| 924 | * Allocates new page tables if necessary |
| 925 | * and updates the page directory (cayman+). |
| 926 | * Returns 0 for success, error for failure. |
| 927 | * |
| 928 | * Global and local mutex must be locked! |
| 929 | */ |
| 930 | static int radeon_vm_update_pdes(struct radeon_device *rdev, |
| 931 | struct radeon_vm *vm, |
| 932 | uint64_t start, uint64_t end) |
| 933 | { |
| 934 | static const uint32_t incr = RADEON_VM_PTE_COUNT * 8; |
| 935 | |
| 936 | uint64_t last_pde = ~0, last_pt = ~0; |
| 937 | unsigned count = 0; |
| 938 | uint64_t pt_idx; |
| 939 | int r; |
| 940 | |
| 941 | start = (start / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE; |
| 942 | end = (end / RADEON_GPU_PAGE_SIZE) >> RADEON_VM_BLOCK_SIZE; |
| 943 | |
| 944 | /* walk over the address space and update the page directory */ |
| 945 | for (pt_idx = start; pt_idx <= end; ++pt_idx) { |
| 946 | uint64_t pde, pt; |
| 947 | |
| 948 | if (vm->page_tables[pt_idx]) |
| 949 | continue; |
| 950 | |
| 951 | retry: |
| 952 | r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager, |
| 953 | &vm->page_tables[pt_idx], |
| 954 | RADEON_VM_PTE_COUNT * 8, |
| 955 | RADEON_GPU_PAGE_SIZE, false); |
| 956 | |
| 957 | if (r == -ENOMEM) { |
| 958 | r = radeon_vm_evict(rdev, vm); |
| 959 | if (r) |
| 960 | return r; |
| 961 | goto retry; |
| 962 | } else if (r) { |
| 963 | return r; |
| 964 | } |
| 965 | |
| 966 | pde = vm->pd_gpu_addr + pt_idx * 8; |
| 967 | |
| 968 | pt = radeon_sa_bo_gpu_addr(vm->page_tables[pt_idx]); |
| 969 | |
| 970 | if (((last_pde + 8 * count) != pde) || |
| 971 | ((last_pt + incr * count) != pt)) { |
| 972 | |
| 973 | if (count) { |
| 974 | radeon_asic_vm_set_page(rdev, last_pde, |
| 975 | last_pt, count, incr, |
| 976 | RADEON_VM_PAGE_VALID); |
| 977 | } |
| 978 | |
| 979 | count = 1; |
| 980 | last_pde = pde; |
| 981 | last_pt = pt; |
| 982 | } else { |
| 983 | ++count; |
| 984 | } |
| 985 | } |
| 986 | |
| 987 | if (count) { |
| 988 | radeon_asic_vm_set_page(rdev, last_pde, last_pt, count, |
| 989 | incr, RADEON_VM_PAGE_VALID); |
| 990 | |
| 991 | } |
| 992 | |
| 993 | return 0; |
| 994 | } |
| 995 | |
| 996 | /** |
| 997 | * radeon_vm_update_ptes - make sure that page tables are valid |
| 998 | * |
| 999 | * @rdev: radeon_device pointer |
| 1000 | * @vm: requested vm |
| 1001 | * @start: start of GPU address range |
| 1002 | * @end: end of GPU address range |
| 1003 | * @dst: destination address to map to |
| 1004 | * @flags: mapping flags |
| 1005 | * |
| 1006 | * Update the page tables in the range @start - @end (cayman+). |
| 1007 | * |
| 1008 | * Global and local mutex must be locked! |
| 1009 | */ |
| 1010 | static void radeon_vm_update_ptes(struct radeon_device *rdev, |
| 1011 | struct radeon_vm *vm, |
| 1012 | uint64_t start, uint64_t end, |
| 1013 | uint64_t dst, uint32_t flags) |
| 1014 | { |
| 1015 | static const uint64_t mask = RADEON_VM_PTE_COUNT - 1; |
| 1016 | |
| 1017 | uint64_t last_pte = ~0, last_dst = ~0; |
| 1018 | unsigned count = 0; |
| 1019 | uint64_t addr; |
| 1020 | |
| 1021 | start = start / RADEON_GPU_PAGE_SIZE; |
| 1022 | end = end / RADEON_GPU_PAGE_SIZE; |
| 1023 | |
| 1024 | /* walk over the address space and update the page tables */ |
| 1025 | for (addr = start; addr < end; ) { |
| 1026 | uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE; |
| 1027 | unsigned nptes; |
| 1028 | uint64_t pte; |
| 1029 | |
| 1030 | if ((addr & ~mask) == (end & ~mask)) |
| 1031 | nptes = end - addr; |
| 1032 | else |
| 1033 | nptes = RADEON_VM_PTE_COUNT - (addr & mask); |
| 1034 | |
| 1035 | pte = radeon_sa_bo_gpu_addr(vm->page_tables[pt_idx]); |
| 1036 | pte += (addr & mask) * 8; |
| 1037 | |
Christian König | 204a393 | 2012-10-22 17:42:38 +0200 | [diff] [blame] | 1038 | if ((last_pte + 8 * count) != pte) { |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1039 | |
| 1040 | if (count) { |
| 1041 | radeon_asic_vm_set_page(rdev, last_pte, |
| 1042 | last_dst, count, |
| 1043 | RADEON_GPU_PAGE_SIZE, |
| 1044 | flags); |
| 1045 | } |
| 1046 | |
| 1047 | count = nptes; |
| 1048 | last_pte = pte; |
| 1049 | last_dst = dst; |
| 1050 | } else { |
| 1051 | count += nptes; |
| 1052 | } |
| 1053 | |
| 1054 | addr += nptes; |
| 1055 | dst += nptes * RADEON_GPU_PAGE_SIZE; |
| 1056 | } |
| 1057 | |
| 1058 | if (count) { |
| 1059 | radeon_asic_vm_set_page(rdev, last_pte, last_dst, count, |
| 1060 | RADEON_GPU_PAGE_SIZE, flags); |
| 1061 | } |
| 1062 | } |
| 1063 | |
| 1064 | /** |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1065 | * radeon_vm_bo_update_pte - map a bo into the vm page table |
| 1066 | * |
| 1067 | * @rdev: radeon_device pointer |
| 1068 | * @vm: requested vm |
| 1069 | * @bo: radeon buffer object |
| 1070 | * @mem: ttm mem |
| 1071 | * |
| 1072 | * Fill in the page table entries for @bo (cayman+). |
| 1073 | * Returns 0 for success, -EINVAL for failure. |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1074 | * |
| 1075 | * Object have to be reserved & global and local mutex must be locked! |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1076 | */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1077 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
| 1078 | struct radeon_vm *vm, |
| 1079 | struct radeon_bo *bo, |
| 1080 | struct ttm_mem_reg *mem) |
| 1081 | { |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1082 | unsigned ridx = rdev->asic->vm.pt_ring_index; |
| 1083 | struct radeon_ring *ring = &rdev->ring[ridx]; |
| 1084 | struct radeon_semaphore *sem = NULL; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1085 | struct radeon_bo_va *bo_va; |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 1086 | unsigned nptes, npdes, ndw; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1087 | uint64_t addr; |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1088 | int r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1089 | |
| 1090 | /* nothing to do if vm isn't bound */ |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1091 | if (vm->page_directory == NULL) |
Jesper Juhl | 04bd27a | 2012-02-26 23:51:53 +0100 | [diff] [blame] | 1092 | return 0; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1093 | |
Christian König | 421ca7a | 2012-09-11 16:10:00 +0200 | [diff] [blame] | 1094 | bo_va = radeon_vm_bo_find(vm, bo); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1095 | if (bo_va == NULL) { |
| 1096 | dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm); |
| 1097 | return -EINVAL; |
| 1098 | } |
| 1099 | |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1100 | if (!bo_va->soffset) { |
| 1101 | dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n", |
| 1102 | bo, vm); |
| 1103 | return -EINVAL; |
| 1104 | } |
| 1105 | |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1106 | if ((bo_va->valid && mem) || (!bo_va->valid && mem == NULL)) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1107 | return 0; |
| 1108 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1109 | bo_va->flags &= ~RADEON_VM_PAGE_VALID; |
| 1110 | bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM; |
| 1111 | if (mem) { |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 1112 | addr = mem->start << PAGE_SHIFT; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1113 | if (mem->mem_type != TTM_PL_SYSTEM) { |
| 1114 | bo_va->flags |= RADEON_VM_PAGE_VALID; |
| 1115 | bo_va->valid = true; |
| 1116 | } |
| 1117 | if (mem->mem_type == TTM_PL_TT) { |
| 1118 | bo_va->flags |= RADEON_VM_PAGE_SYSTEM; |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 1119 | } else { |
| 1120 | addr += rdev->vm_manager.vram_base_offset; |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1121 | } |
| 1122 | } else { |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 1123 | addr = 0; |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1124 | bo_va->valid = false; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1125 | } |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1126 | |
| 1127 | if (vm->fence && radeon_fence_signaled(vm->fence)) { |
| 1128 | radeon_fence_unref(&vm->fence); |
| 1129 | } |
| 1130 | |
| 1131 | if (vm->fence && vm->fence->ring != ridx) { |
| 1132 | r = radeon_semaphore_create(rdev, &sem); |
| 1133 | if (r) { |
| 1134 | return r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1135 | } |
| 1136 | } |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1137 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 1138 | nptes = radeon_bo_ngpu_pages(bo); |
| 1139 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1140 | /* assume two extra pdes in case the mapping overlaps the borders */ |
| 1141 | npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 2; |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 1142 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1143 | /* estimate number of dw needed */ |
| 1144 | /* semaphore, fence and padding */ |
| 1145 | ndw = 32; |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 1146 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1147 | if (RADEON_VM_BLOCK_SIZE > 11) |
| 1148 | /* reserve space for one header for every 2k dwords */ |
Christian König | 08eda32 | 2012-10-22 17:42:39 +0200 | [diff] [blame] | 1149 | ndw += (nptes >> 11) * 4; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1150 | else |
| 1151 | /* reserve space for one header for |
| 1152 | every (1 << BLOCK_SIZE) entries */ |
Christian König | 08eda32 | 2012-10-22 17:42:39 +0200 | [diff] [blame] | 1153 | ndw += (nptes >> RADEON_VM_BLOCK_SIZE) * 4; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1154 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 1155 | /* reserve space for pte addresses */ |
| 1156 | ndw += nptes * 2; |
| 1157 | |
| 1158 | /* reserve space for one header for every 2k dwords */ |
Christian König | 08eda32 | 2012-10-22 17:42:39 +0200 | [diff] [blame] | 1159 | ndw += (npdes >> 11) * 4; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1160 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 1161 | /* reserve space for pde addresses */ |
| 1162 | ndw += npdes * 2; |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1163 | |
| 1164 | r = radeon_ring_lock(rdev, ring, ndw); |
| 1165 | if (r) { |
| 1166 | return r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1167 | } |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1168 | |
| 1169 | if (sem && radeon_fence_need_sync(vm->fence, ridx)) { |
| 1170 | radeon_semaphore_sync_rings(rdev, sem, vm->fence->ring, ridx); |
| 1171 | radeon_fence_note_sync(vm->fence, ridx); |
| 1172 | } |
| 1173 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1174 | r = radeon_vm_update_pdes(rdev, vm, bo_va->soffset, bo_va->eoffset); |
| 1175 | if (r) { |
| 1176 | radeon_ring_unlock_undo(rdev, ring); |
| 1177 | return r; |
| 1178 | } |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 1179 | |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1180 | radeon_vm_update_ptes(rdev, vm, bo_va->soffset, bo_va->eoffset, |
| 1181 | addr, bo_va->flags); |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1182 | |
| 1183 | radeon_fence_unref(&vm->fence); |
| 1184 | r = radeon_fence_emit(rdev, &vm->fence, ridx); |
| 1185 | if (r) { |
| 1186 | radeon_ring_unlock_undo(rdev, ring); |
| 1187 | return r; |
| 1188 | } |
| 1189 | radeon_ring_unlock_commit(rdev, ring); |
| 1190 | radeon_semaphore_free(rdev, &sem, vm->fence); |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 1191 | radeon_fence_unref(&vm->last_flush); |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 1192 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1193 | return 0; |
| 1194 | } |
| 1195 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1196 | /** |
| 1197 | * radeon_vm_bo_rmv - remove a bo to a specific vm |
| 1198 | * |
| 1199 | * @rdev: radeon_device pointer |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1200 | * @bo_va: requested bo_va |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1201 | * |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1202 | * Remove @bo_va->bo from the requested vm (cayman+). |
| 1203 | * Remove @bo_va->bo from the list of bos associated with the bo_va->vm and |
| 1204 | * remove the ptes for @bo_va in the page table. |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1205 | * Returns 0 for success. |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 1206 | * |
| 1207 | * Object have to be reserved! |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1208 | */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1209 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1210 | struct radeon_bo_va *bo_va) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1211 | { |
Jerome Glisse | e43b5ec | 2012-08-06 12:32:21 -0400 | [diff] [blame] | 1212 | int r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1213 | |
Christian König | 36ff39c | 2012-05-09 10:07:08 +0200 | [diff] [blame] | 1214 | mutex_lock(&rdev->vm_manager.lock); |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1215 | mutex_lock(&bo_va->vm->mutex); |
| 1216 | r = radeon_vm_bo_update_pte(rdev, bo_va->vm, bo_va->bo, NULL); |
Christian König | 36ff39c | 2012-05-09 10:07:08 +0200 | [diff] [blame] | 1217 | mutex_unlock(&rdev->vm_manager.lock); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1218 | list_del(&bo_va->vm_list); |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1219 | mutex_unlock(&bo_va->vm->mutex); |
Sebastian Biemueller | 108b0d3 | 2012-02-29 11:04:52 -0500 | [diff] [blame] | 1220 | list_del(&bo_va->bo_list); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1221 | |
| 1222 | kfree(bo_va); |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1223 | return r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1224 | } |
| 1225 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1226 | /** |
| 1227 | * radeon_vm_bo_invalidate - mark the bo as invalid |
| 1228 | * |
| 1229 | * @rdev: radeon_device pointer |
| 1230 | * @vm: requested vm |
| 1231 | * @bo: radeon buffer object |
| 1232 | * |
| 1233 | * Mark @bo as invalid (cayman+). |
| 1234 | */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1235 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
| 1236 | struct radeon_bo *bo) |
| 1237 | { |
| 1238 | struct radeon_bo_va *bo_va; |
| 1239 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1240 | list_for_each_entry(bo_va, &bo->va, bo_list) { |
| 1241 | bo_va->valid = false; |
| 1242 | } |
| 1243 | } |
| 1244 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1245 | /** |
| 1246 | * radeon_vm_init - initialize a vm instance |
| 1247 | * |
| 1248 | * @rdev: radeon_device pointer |
| 1249 | * @vm: requested vm |
| 1250 | * |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 1251 | * Init @vm fields (cayman+). |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1252 | */ |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 1253 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1254 | { |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 1255 | vm->id = 0; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1256 | vm->fence = NULL; |
| 1257 | mutex_init(&vm->mutex); |
| 1258 | INIT_LIST_HEAD(&vm->list); |
| 1259 | INIT_LIST_HEAD(&vm->va); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1260 | } |
| 1261 | |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1262 | /** |
Dmitrii Cherkasov | f59abbf | 2012-08-13 10:53:29 -0400 | [diff] [blame] | 1263 | * radeon_vm_fini - tear down a vm instance |
Alex Deucher | 09db864 | 2012-07-17 14:02:40 -0400 | [diff] [blame] | 1264 | * |
| 1265 | * @rdev: radeon_device pointer |
| 1266 | * @vm: requested vm |
| 1267 | * |
| 1268 | * Tear down @vm (cayman+). |
| 1269 | * Unbind the VM and remove all bos from the vm bo list |
| 1270 | */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1271 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm) |
| 1272 | { |
| 1273 | struct radeon_bo_va *bo_va, *tmp; |
| 1274 | int r; |
| 1275 | |
Christian König | 36ff39c | 2012-05-09 10:07:08 +0200 | [diff] [blame] | 1276 | mutex_lock(&rdev->vm_manager.lock); |
Christian König | bb40915 | 2012-06-03 16:09:43 +0200 | [diff] [blame] | 1277 | mutex_lock(&vm->mutex); |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 1278 | radeon_vm_free_pt(rdev, vm); |
Christian König | 36ff39c | 2012-05-09 10:07:08 +0200 | [diff] [blame] | 1279 | mutex_unlock(&rdev->vm_manager.lock); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1280 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1281 | if (!list_empty(&vm->va)) { |
| 1282 | dev_err(rdev->dev, "still active bo inside vm\n"); |
| 1283 | } |
| 1284 | list_for_each_entry_safe(bo_va, tmp, &vm->va, vm_list) { |
| 1285 | list_del_init(&bo_va->vm_list); |
| 1286 | r = radeon_bo_reserve(bo_va->bo, false); |
| 1287 | if (!r) { |
| 1288 | list_del_init(&bo_va->bo_list); |
| 1289 | radeon_bo_unreserve(bo_va->bo); |
| 1290 | kfree(bo_va); |
| 1291 | } |
| 1292 | } |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 1293 | radeon_fence_unref(&vm->fence); |
| 1294 | radeon_fence_unref(&vm->last_flush); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1295 | mutex_unlock(&vm->mutex); |
| 1296 | } |