Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 1 | /* |
| 2 | * DMM IOMMU driver support functions for TI OMAP processors. |
| 3 | * |
| 4 | * Author: Rob Clark <rob@ti.com> |
| 5 | * Andy Gross <andy.gross@ti.com> |
| 6 | * |
| 7 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation version 2. |
| 12 | * |
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 14 | * kind, whether express or implied; without even the implied warranty |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/platform_device.h> /* platform_device() */ |
| 21 | #include <linux/errno.h> |
| 22 | #include <linux/sched.h> |
| 23 | #include <linux/wait.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/dma-mapping.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/vmalloc.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mm.h> |
| 30 | #include <linux/time.h> |
| 31 | #include <linux/list.h> |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 32 | |
| 33 | #include "omap_dmm_tiler.h" |
| 34 | #include "omap_dmm_priv.h" |
| 35 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 36 | #define DMM_DRIVER_NAME "dmm" |
| 37 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 38 | /* mappings for associating views to luts */ |
| 39 | static struct tcm *containers[TILFMT_NFORMATS]; |
| 40 | static struct dmm *omap_dmm; |
| 41 | |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 42 | /* global spinlock for protecting lists */ |
| 43 | static DEFINE_SPINLOCK(list_lock); |
| 44 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 45 | /* Geometry table */ |
| 46 | #define GEOM(xshift, yshift, bytes_per_pixel) { \ |
| 47 | .x_shft = (xshift), \ |
| 48 | .y_shft = (yshift), \ |
| 49 | .cpp = (bytes_per_pixel), \ |
| 50 | .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \ |
| 51 | .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \ |
| 52 | } |
| 53 | |
| 54 | static const struct { |
| 55 | uint32_t x_shft; /* unused X-bits (as part of bpp) */ |
| 56 | uint32_t y_shft; /* unused Y-bits (as part of bpp) */ |
| 57 | uint32_t cpp; /* bytes/chars per pixel */ |
| 58 | uint32_t slot_w; /* width of each slot (in pixels) */ |
| 59 | uint32_t slot_h; /* height of each slot (in pixels) */ |
| 60 | } geom[TILFMT_NFORMATS] = { |
| 61 | [TILFMT_8BIT] = GEOM(0, 0, 1), |
| 62 | [TILFMT_16BIT] = GEOM(0, 1, 2), |
| 63 | [TILFMT_32BIT] = GEOM(1, 1, 4), |
| 64 | [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1), |
| 65 | }; |
| 66 | |
| 67 | |
| 68 | /* lookup table for registers w/ per-engine instances */ |
| 69 | static const uint32_t reg[][4] = { |
| 70 | [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1, |
| 71 | DMM_PAT_STATUS__2, DMM_PAT_STATUS__3}, |
| 72 | [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1, |
| 73 | DMM_PAT_DESCR__2, DMM_PAT_DESCR__3}, |
| 74 | }; |
| 75 | |
| 76 | /* simple allocator to grab next 16 byte aligned memory from txn */ |
| 77 | static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa) |
| 78 | { |
| 79 | void *ptr; |
| 80 | struct refill_engine *engine = txn->engine_handle; |
| 81 | |
| 82 | /* dmm programming requires 16 byte aligned addresses */ |
| 83 | txn->current_pa = round_up(txn->current_pa, 16); |
| 84 | txn->current_va = (void *)round_up((long)txn->current_va, 16); |
| 85 | |
| 86 | ptr = txn->current_va; |
| 87 | *pa = txn->current_pa; |
| 88 | |
| 89 | txn->current_pa += sz; |
| 90 | txn->current_va += sz; |
| 91 | |
| 92 | BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE); |
| 93 | |
| 94 | return ptr; |
| 95 | } |
| 96 | |
| 97 | /* check status and spin until wait_mask comes true */ |
| 98 | static int wait_status(struct refill_engine *engine, uint32_t wait_mask) |
| 99 | { |
| 100 | struct dmm *dmm = engine->dmm; |
| 101 | uint32_t r = 0, err, i; |
| 102 | |
| 103 | i = DMM_FIXED_RETRY_COUNT; |
| 104 | while (true) { |
| 105 | r = readl(dmm->base + reg[PAT_STATUS][engine->id]); |
| 106 | err = r & DMM_PATSTATUS_ERR; |
| 107 | if (err) |
| 108 | return -EFAULT; |
| 109 | |
| 110 | if ((r & wait_mask) == wait_mask) |
| 111 | break; |
| 112 | |
| 113 | if (--i == 0) |
| 114 | return -ETIMEDOUT; |
| 115 | |
| 116 | udelay(1); |
| 117 | } |
| 118 | |
| 119 | return 0; |
| 120 | } |
| 121 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 122 | static void release_engine(struct refill_engine *engine) |
| 123 | { |
| 124 | unsigned long flags; |
| 125 | |
| 126 | spin_lock_irqsave(&list_lock, flags); |
| 127 | list_add(&engine->idle_node, &omap_dmm->idle_head); |
| 128 | spin_unlock_irqrestore(&list_lock, flags); |
| 129 | |
| 130 | atomic_inc(&omap_dmm->engine_counter); |
| 131 | wake_up_interruptible(&omap_dmm->engine_queue); |
| 132 | } |
| 133 | |
Andy Gross | d7de993 | 2012-08-09 00:14:56 -0500 | [diff] [blame] | 134 | static irqreturn_t omap_dmm_irq_handler(int irq, void *arg) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 135 | { |
| 136 | struct dmm *dmm = arg; |
| 137 | uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS); |
| 138 | int i; |
| 139 | |
| 140 | /* ack IRQ */ |
| 141 | writel(status, dmm->base + DMM_PAT_IRQSTATUS); |
| 142 | |
| 143 | for (i = 0; i < dmm->num_engines; i++) { |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 144 | if (status & DMM_IRQSTAT_LST) { |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 145 | wake_up_interruptible(&dmm->engines[i].wait_for_refill); |
| 146 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 147 | if (dmm->engines[i].async) |
| 148 | release_engine(&dmm->engines[i]); |
| 149 | } |
| 150 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 151 | status >>= 8; |
| 152 | } |
| 153 | |
| 154 | return IRQ_HANDLED; |
| 155 | } |
| 156 | |
| 157 | /** |
| 158 | * Get a handle for a DMM transaction |
| 159 | */ |
| 160 | static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm) |
| 161 | { |
| 162 | struct dmm_txn *txn = NULL; |
| 163 | struct refill_engine *engine = NULL; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 164 | int ret; |
| 165 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 166 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 167 | |
| 168 | /* wait until an engine is available */ |
| 169 | ret = wait_event_interruptible(omap_dmm->engine_queue, |
| 170 | atomic_add_unless(&omap_dmm->engine_counter, -1, 0)); |
| 171 | if (ret) |
| 172 | return ERR_PTR(ret); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 173 | |
| 174 | /* grab an idle engine */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 175 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 176 | if (!list_empty(&dmm->idle_head)) { |
| 177 | engine = list_entry(dmm->idle_head.next, struct refill_engine, |
| 178 | idle_node); |
| 179 | list_del(&engine->idle_node); |
| 180 | } |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 181 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 182 | |
| 183 | BUG_ON(!engine); |
| 184 | |
| 185 | txn = &engine->txn; |
| 186 | engine->tcm = tcm; |
| 187 | txn->engine_handle = engine; |
| 188 | txn->last_pat = NULL; |
| 189 | txn->current_va = engine->refill_va; |
| 190 | txn->current_pa = engine->refill_pa; |
| 191 | |
| 192 | return txn; |
| 193 | } |
| 194 | |
| 195 | /** |
| 196 | * Add region to DMM transaction. If pages or pages[i] is NULL, then the |
| 197 | * corresponding slot is cleared (ie. dummy_pa is programmed) |
| 198 | */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 199 | static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area, |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 200 | struct page **pages, uint32_t npages, uint32_t roll) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 201 | { |
| 202 | dma_addr_t pat_pa = 0; |
| 203 | uint32_t *data; |
| 204 | struct pat *pat; |
| 205 | struct refill_engine *engine = txn->engine_handle; |
| 206 | int columns = (1 + area->x1 - area->x0); |
| 207 | int rows = (1 + area->y1 - area->y0); |
| 208 | int i = columns*rows; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 209 | |
| 210 | pat = alloc_dma(txn, sizeof(struct pat), &pat_pa); |
| 211 | |
| 212 | if (txn->last_pat) |
| 213 | txn->last_pat->next_pa = (uint32_t)pat_pa; |
| 214 | |
| 215 | pat->area = *area; |
| 216 | pat->ctrl = (struct pat_ctrl){ |
| 217 | .start = 1, |
| 218 | .lut_id = engine->tcm->lut_id, |
| 219 | }; |
| 220 | |
| 221 | data = alloc_dma(txn, 4*i, &pat->data_pa); |
| 222 | |
| 223 | while (i--) { |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 224 | int n = i + roll; |
| 225 | if (n >= npages) |
| 226 | n -= npages; |
| 227 | data[i] = (pages && pages[n]) ? |
| 228 | page_to_phys(pages[n]) : engine->dmm->dummy_pa; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 229 | } |
| 230 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 231 | txn->last_pat = pat; |
| 232 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 233 | return; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | /** |
| 237 | * Commit the DMM transaction. |
| 238 | */ |
| 239 | static int dmm_txn_commit(struct dmm_txn *txn, bool wait) |
| 240 | { |
| 241 | int ret = 0; |
| 242 | struct refill_engine *engine = txn->engine_handle; |
| 243 | struct dmm *dmm = engine->dmm; |
| 244 | |
| 245 | if (!txn->last_pat) { |
| 246 | dev_err(engine->dmm->dev, "need at least one txn\n"); |
| 247 | ret = -EINVAL; |
| 248 | goto cleanup; |
| 249 | } |
| 250 | |
| 251 | txn->last_pat->next_pa = 0; |
| 252 | |
| 253 | /* write to PAT_DESCR to clear out any pending transaction */ |
| 254 | writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]); |
| 255 | |
| 256 | /* wait for engine ready: */ |
| 257 | ret = wait_status(engine, DMM_PATSTATUS_READY); |
| 258 | if (ret) { |
| 259 | ret = -EFAULT; |
| 260 | goto cleanup; |
| 261 | } |
| 262 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 263 | /* mark whether it is async to denote list management in IRQ handler */ |
| 264 | engine->async = wait ? false : true; |
| 265 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 266 | /* kick reload */ |
| 267 | writel(engine->refill_pa, |
| 268 | dmm->base + reg[PAT_DESCR][engine->id]); |
| 269 | |
| 270 | if (wait) { |
| 271 | if (wait_event_interruptible_timeout(engine->wait_for_refill, |
| 272 | wait_status(engine, DMM_PATSTATUS_READY) == 0, |
| 273 | msecs_to_jiffies(1)) <= 0) { |
| 274 | dev_err(dmm->dev, "timed out waiting for done\n"); |
| 275 | ret = -ETIMEDOUT; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | cleanup: |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 280 | /* only place engine back on list if we are done with it */ |
| 281 | if (ret || wait) |
| 282 | release_engine(engine); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 283 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 284 | return ret; |
| 285 | } |
| 286 | |
| 287 | /* |
| 288 | * DMM programming |
| 289 | */ |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 290 | static int fill(struct tcm_area *area, struct page **pages, |
| 291 | uint32_t npages, uint32_t roll, bool wait) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 292 | { |
| 293 | int ret = 0; |
| 294 | struct tcm_area slice, area_s; |
| 295 | struct dmm_txn *txn; |
| 296 | |
| 297 | txn = dmm_txn_init(omap_dmm, area->tcm); |
| 298 | if (IS_ERR_OR_NULL(txn)) |
Andy Gross | 295c799 | 2012-11-16 13:10:57 -0600 | [diff] [blame] | 299 | return -ENOMEM; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 300 | |
| 301 | tcm_for_each_slice(slice, *area, area_s) { |
| 302 | struct pat_area p_area = { |
| 303 | .x0 = slice.p0.x, .y0 = slice.p0.y, |
| 304 | .x1 = slice.p1.x, .y1 = slice.p1.y, |
| 305 | }; |
| 306 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 307 | dmm_txn_append(txn, &p_area, pages, npages, roll); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 308 | |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 309 | roll += tcm_sizeof(slice); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | ret = dmm_txn_commit(txn, wait); |
| 313 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 314 | return ret; |
| 315 | } |
| 316 | |
| 317 | /* |
| 318 | * Pin/unpin |
| 319 | */ |
| 320 | |
| 321 | /* note: slots for which pages[i] == NULL are filled w/ dummy page |
| 322 | */ |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 323 | int tiler_pin(struct tiler_block *block, struct page **pages, |
| 324 | uint32_t npages, uint32_t roll, bool wait) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 325 | { |
| 326 | int ret; |
| 327 | |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 328 | ret = fill(&block->area, pages, npages, roll, wait); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 329 | |
| 330 | if (ret) |
| 331 | tiler_unpin(block); |
| 332 | |
| 333 | return ret; |
| 334 | } |
| 335 | |
| 336 | int tiler_unpin(struct tiler_block *block) |
| 337 | { |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 338 | return fill(&block->area, NULL, 0, 0, false); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 339 | } |
| 340 | |
| 341 | /* |
| 342 | * Reserve/release |
| 343 | */ |
| 344 | struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, |
| 345 | uint16_t h, uint16_t align) |
| 346 | { |
| 347 | struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); |
| 348 | u32 min_align = 128; |
| 349 | int ret; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 350 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 351 | |
| 352 | BUG_ON(!validfmt(fmt)); |
| 353 | |
| 354 | /* convert width/height to slots */ |
| 355 | w = DIV_ROUND_UP(w, geom[fmt].slot_w); |
| 356 | h = DIV_ROUND_UP(h, geom[fmt].slot_h); |
| 357 | |
| 358 | /* convert alignment to slots */ |
| 359 | min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp)); |
| 360 | align = ALIGN(align, min_align); |
| 361 | align /= geom[fmt].slot_w * geom[fmt].cpp; |
| 362 | |
| 363 | block->fmt = fmt; |
| 364 | |
| 365 | ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area); |
| 366 | if (ret) { |
| 367 | kfree(block); |
Rob Clark | 1c3a4dc | 2012-03-21 16:40:23 -0500 | [diff] [blame] | 368 | return ERR_PTR(-ENOMEM); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | /* add to allocation list */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 372 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 373 | list_add(&block->alloc_node, &omap_dmm->alloc_head); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 374 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 375 | |
| 376 | return block; |
| 377 | } |
| 378 | |
| 379 | struct tiler_block *tiler_reserve_1d(size_t size) |
| 380 | { |
| 381 | struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); |
| 382 | int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 383 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 384 | |
| 385 | if (!block) |
Andy Gross | d7de993 | 2012-08-09 00:14:56 -0500 | [diff] [blame] | 386 | return ERR_PTR(-ENOMEM); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 387 | |
| 388 | block->fmt = TILFMT_PAGE; |
| 389 | |
| 390 | if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages, |
| 391 | &block->area)) { |
| 392 | kfree(block); |
Rob Clark | 1c3a4dc | 2012-03-21 16:40:23 -0500 | [diff] [blame] | 393 | return ERR_PTR(-ENOMEM); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 394 | } |
| 395 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 396 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 397 | list_add(&block->alloc_node, &omap_dmm->alloc_head); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 398 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 399 | |
| 400 | return block; |
| 401 | } |
| 402 | |
| 403 | /* note: if you have pin'd pages, you should have already unpin'd first! */ |
| 404 | int tiler_release(struct tiler_block *block) |
| 405 | { |
| 406 | int ret = tcm_free(&block->area); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 407 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 408 | |
| 409 | if (block->area.tcm) |
| 410 | dev_err(omap_dmm->dev, "failed to release block\n"); |
| 411 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 412 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 413 | list_del(&block->alloc_node); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 414 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 415 | |
| 416 | kfree(block); |
| 417 | return ret; |
| 418 | } |
| 419 | |
| 420 | /* |
| 421 | * Utils |
| 422 | */ |
| 423 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 424 | /* calculate the tiler space address of a pixel in a view orientation... |
| 425 | * below description copied from the display subsystem section of TRM: |
| 426 | * |
| 427 | * When the TILER is addressed, the bits: |
| 428 | * [28:27] = 0x0 for 8-bit tiled |
| 429 | * 0x1 for 16-bit tiled |
| 430 | * 0x2 for 32-bit tiled |
| 431 | * 0x3 for page mode |
| 432 | * [31:29] = 0x0 for 0-degree view |
| 433 | * 0x1 for 180-degree view + mirroring |
| 434 | * 0x2 for 0-degree view + mirroring |
| 435 | * 0x3 for 180-degree view |
| 436 | * 0x4 for 270-degree view + mirroring |
| 437 | * 0x5 for 270-degree view |
| 438 | * 0x6 for 90-degree view |
| 439 | * 0x7 for 90-degree view + mirroring |
| 440 | * Otherwise the bits indicated the corresponding bit address to access |
| 441 | * the SDRAM. |
| 442 | */ |
| 443 | static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 444 | { |
| 445 | u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment; |
| 446 | |
| 447 | x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft; |
| 448 | y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft; |
| 449 | alignment = geom[fmt].x_shft + geom[fmt].y_shft; |
| 450 | |
| 451 | /* validate coordinate */ |
| 452 | x_mask = MASK(x_bits); |
| 453 | y_mask = MASK(y_bits); |
| 454 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 455 | if (x < 0 || x > x_mask || y < 0 || y > y_mask) { |
| 456 | DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u", |
| 457 | x, x, x_mask, y, y, y_mask); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 458 | return 0; |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 459 | } |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 460 | |
| 461 | /* account for mirroring */ |
| 462 | if (orient & MASK_X_INVERT) |
| 463 | x ^= x_mask; |
| 464 | if (orient & MASK_Y_INVERT) |
| 465 | y ^= y_mask; |
| 466 | |
| 467 | /* get coordinate address */ |
| 468 | if (orient & MASK_XY_FLIP) |
| 469 | tmp = ((x << y_bits) + y); |
| 470 | else |
| 471 | tmp = ((y << x_bits) + x); |
| 472 | |
| 473 | return TIL_ADDR((tmp << alignment), orient, fmt); |
| 474 | } |
| 475 | |
| 476 | dma_addr_t tiler_ssptr(struct tiler_block *block) |
| 477 | { |
| 478 | BUG_ON(!validfmt(block->fmt)); |
| 479 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 480 | return TILVIEW_8BIT + tiler_get_address(block->fmt, 0, |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 481 | block->area.p0.x * geom[block->fmt].slot_w, |
| 482 | block->area.p0.y * geom[block->fmt].slot_h); |
| 483 | } |
| 484 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 485 | dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient, |
| 486 | uint32_t x, uint32_t y) |
| 487 | { |
| 488 | struct tcm_pt *p = &block->area.p0; |
| 489 | BUG_ON(!validfmt(block->fmt)); |
| 490 | |
| 491 | return tiler_get_address(block->fmt, orient, |
| 492 | (p->x * geom[block->fmt].slot_w) + x, |
| 493 | (p->y * geom[block->fmt].slot_h) + y); |
| 494 | } |
| 495 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 496 | void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h) |
| 497 | { |
| 498 | BUG_ON(!validfmt(fmt)); |
| 499 | *w = round_up(*w, geom[fmt].slot_w); |
| 500 | *h = round_up(*h, geom[fmt].slot_h); |
| 501 | } |
| 502 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 503 | uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 504 | { |
| 505 | BUG_ON(!validfmt(fmt)); |
| 506 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 507 | if (orient & MASK_XY_FLIP) |
| 508 | return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft); |
| 509 | else |
| 510 | return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h) |
| 514 | { |
| 515 | tiler_align(fmt, &w, &h); |
| 516 | return geom[fmt].cpp * w * h; |
| 517 | } |
| 518 | |
| 519 | size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h) |
| 520 | { |
| 521 | BUG_ON(!validfmt(fmt)); |
| 522 | return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h; |
| 523 | } |
| 524 | |
Andy Gross | e5e4e9b | 2012-10-17 00:30:03 -0500 | [diff] [blame] | 525 | bool dmm_is_available(void) |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 526 | { |
| 527 | return omap_dmm ? true : false; |
| 528 | } |
| 529 | |
| 530 | static int omap_dmm_remove(struct platform_device *dev) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 531 | { |
| 532 | struct tiler_block *block, *_block; |
| 533 | int i; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 534 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 535 | |
| 536 | if (omap_dmm) { |
| 537 | /* free all area regions */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 538 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 539 | list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head, |
| 540 | alloc_node) { |
| 541 | list_del(&block->alloc_node); |
| 542 | kfree(block); |
| 543 | } |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 544 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 545 | |
| 546 | for (i = 0; i < omap_dmm->num_lut; i++) |
| 547 | if (omap_dmm->tcm && omap_dmm->tcm[i]) |
| 548 | omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]); |
| 549 | kfree(omap_dmm->tcm); |
| 550 | |
| 551 | kfree(omap_dmm->engines); |
| 552 | if (omap_dmm->refill_va) |
Andy Gross | fe4fc16 | 2012-10-11 23:07:36 -0500 | [diff] [blame] | 553 | dma_free_writecombine(omap_dmm->dev, |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 554 | REFILL_BUFFER_SIZE * omap_dmm->num_engines, |
| 555 | omap_dmm->refill_va, |
| 556 | omap_dmm->refill_pa); |
| 557 | if (omap_dmm->dummy_page) |
| 558 | __free_page(omap_dmm->dummy_page); |
| 559 | |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 560 | if (omap_dmm->irq > 0) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 561 | free_irq(omap_dmm->irq, omap_dmm); |
| 562 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 563 | iounmap(omap_dmm->base); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 564 | kfree(omap_dmm); |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 565 | omap_dmm = NULL; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 566 | } |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 571 | static int omap_dmm_probe(struct platform_device *dev) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 572 | { |
| 573 | int ret = -EFAULT, i; |
| 574 | struct tcm_area area = {0}; |
Andy Gross | 0f562d1 | 2012-10-11 23:06:43 -0500 | [diff] [blame] | 575 | u32 hwinfo, pat_geom; |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 576 | struct resource *mem; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 577 | |
| 578 | omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL); |
| 579 | if (!omap_dmm) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 580 | dev_err(&dev->dev, "failed to allocate driver data section\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 581 | goto fail; |
| 582 | } |
| 583 | |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 584 | /* initialize lists */ |
| 585 | INIT_LIST_HEAD(&omap_dmm->alloc_head); |
| 586 | INIT_LIST_HEAD(&omap_dmm->idle_head); |
| 587 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 588 | init_waitqueue_head(&omap_dmm->engine_queue); |
| 589 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 590 | /* lookup hwmod data - base address and irq */ |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 591 | mem = platform_get_resource(dev, IORESOURCE_MEM, 0); |
| 592 | if (!mem) { |
| 593 | dev_err(&dev->dev, "failed to get base address resource\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 594 | goto fail; |
| 595 | } |
| 596 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 597 | omap_dmm->base = ioremap(mem->start, SZ_2K); |
| 598 | |
| 599 | if (!omap_dmm->base) { |
| 600 | dev_err(&dev->dev, "failed to get dmm base address\n"); |
| 601 | goto fail; |
| 602 | } |
| 603 | |
| 604 | omap_dmm->irq = platform_get_irq(dev, 0); |
| 605 | if (omap_dmm->irq < 0) { |
| 606 | dev_err(&dev->dev, "failed to get IRQ resource\n"); |
| 607 | goto fail; |
| 608 | } |
| 609 | |
| 610 | omap_dmm->dev = &dev->dev; |
| 611 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 612 | hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO); |
| 613 | omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; |
| 614 | omap_dmm->num_lut = (hwinfo >> 16) & 0x1F; |
| 615 | omap_dmm->container_width = 256; |
| 616 | omap_dmm->container_height = 128; |
| 617 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 618 | atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); |
| 619 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 620 | /* read out actual LUT width and height */ |
| 621 | pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY); |
| 622 | omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5; |
| 623 | omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5; |
| 624 | |
| 625 | /* initialize DMM registers */ |
| 626 | writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0); |
| 627 | writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1); |
| 628 | writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0); |
| 629 | writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE); |
| 630 | writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0); |
| 631 | writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1); |
| 632 | |
| 633 | ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED, |
| 634 | "omap_dmm_irq_handler", omap_dmm); |
| 635 | |
| 636 | if (ret) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 637 | dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n", |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 638 | omap_dmm->irq, ret); |
| 639 | omap_dmm->irq = -1; |
| 640 | goto fail; |
| 641 | } |
| 642 | |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 643 | /* Enable all interrupts for each refill engine except |
| 644 | * ERR_LUT_MISS<n> (which is just advisory, and we don't care |
| 645 | * about because we want to be able to refill live scanout |
| 646 | * buffers for accelerated pan/scroll) and FILL_DSC<n> which |
| 647 | * we just generally don't care about. |
| 648 | */ |
| 649 | writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 650 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 651 | omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32); |
| 652 | if (!omap_dmm->dummy_page) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 653 | dev_err(&dev->dev, "could not allocate dummy page\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 654 | ret = -ENOMEM; |
| 655 | goto fail; |
| 656 | } |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 657 | |
| 658 | /* set dma mask for device */ |
| 659 | /* NOTE: this is a workaround for the hwmod not initializing properly */ |
| 660 | dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
| 661 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 662 | omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page); |
| 663 | |
| 664 | /* alloc refill memory */ |
Andy Gross | fe4fc16 | 2012-10-11 23:07:36 -0500 | [diff] [blame] | 665 | omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev, |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 666 | REFILL_BUFFER_SIZE * omap_dmm->num_engines, |
| 667 | &omap_dmm->refill_pa, GFP_KERNEL); |
| 668 | if (!omap_dmm->refill_va) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 669 | dev_err(&dev->dev, "could not allocate refill memory\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 670 | goto fail; |
| 671 | } |
| 672 | |
| 673 | /* alloc engines */ |
| 674 | omap_dmm->engines = kzalloc( |
| 675 | omap_dmm->num_engines * sizeof(struct refill_engine), |
| 676 | GFP_KERNEL); |
| 677 | if (!omap_dmm->engines) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 678 | dev_err(&dev->dev, "could not allocate engines\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 679 | ret = -ENOMEM; |
| 680 | goto fail; |
| 681 | } |
| 682 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 683 | for (i = 0; i < omap_dmm->num_engines; i++) { |
| 684 | omap_dmm->engines[i].id = i; |
| 685 | omap_dmm->engines[i].dmm = omap_dmm; |
| 686 | omap_dmm->engines[i].refill_va = omap_dmm->refill_va + |
| 687 | (REFILL_BUFFER_SIZE * i); |
| 688 | omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa + |
| 689 | (REFILL_BUFFER_SIZE * i); |
| 690 | init_waitqueue_head(&omap_dmm->engines[i].wait_for_refill); |
| 691 | |
| 692 | list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head); |
| 693 | } |
| 694 | |
| 695 | omap_dmm->tcm = kzalloc(omap_dmm->num_lut * sizeof(*omap_dmm->tcm), |
| 696 | GFP_KERNEL); |
| 697 | if (!omap_dmm->tcm) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 698 | dev_err(&dev->dev, "failed to allocate lut ptrs\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 699 | ret = -ENOMEM; |
| 700 | goto fail; |
| 701 | } |
| 702 | |
| 703 | /* init containers */ |
| 704 | for (i = 0; i < omap_dmm->num_lut; i++) { |
| 705 | omap_dmm->tcm[i] = sita_init(omap_dmm->container_width, |
| 706 | omap_dmm->container_height, |
| 707 | NULL); |
| 708 | |
| 709 | if (!omap_dmm->tcm[i]) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 710 | dev_err(&dev->dev, "failed to allocate container\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 711 | ret = -ENOMEM; |
| 712 | goto fail; |
| 713 | } |
| 714 | |
| 715 | omap_dmm->tcm[i]->lut_id = i; |
| 716 | } |
| 717 | |
| 718 | /* assign access mode containers to applicable tcm container */ |
| 719 | /* OMAP 4 has 1 container for all 4 views */ |
| 720 | containers[TILFMT_8BIT] = omap_dmm->tcm[0]; |
| 721 | containers[TILFMT_16BIT] = omap_dmm->tcm[0]; |
| 722 | containers[TILFMT_32BIT] = omap_dmm->tcm[0]; |
| 723 | containers[TILFMT_PAGE] = omap_dmm->tcm[0]; |
| 724 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 725 | area = (struct tcm_area) { |
| 726 | .is2d = true, |
| 727 | .tcm = NULL, |
| 728 | .p1.x = omap_dmm->container_width - 1, |
| 729 | .p1.y = omap_dmm->container_height - 1, |
| 730 | }; |
| 731 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 732 | /* initialize all LUTs to dummy page entries */ |
| 733 | for (i = 0; i < omap_dmm->num_lut; i++) { |
| 734 | area.tcm = omap_dmm->tcm[i]; |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 735 | if (fill(&area, NULL, 0, 0, true)) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 736 | dev_err(omap_dmm->dev, "refill failed"); |
| 737 | } |
| 738 | |
| 739 | dev_info(omap_dmm->dev, "initialized all PAT entries\n"); |
| 740 | |
| 741 | return 0; |
| 742 | |
| 743 | fail: |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 744 | if (omap_dmm_remove(dev)) |
| 745 | dev_err(&dev->dev, "cleanup failed\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 746 | return ret; |
| 747 | } |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 748 | |
| 749 | /* |
| 750 | * debugfs support |
| 751 | */ |
| 752 | |
| 753 | #ifdef CONFIG_DEBUG_FS |
| 754 | |
| 755 | static const char *alphabet = "abcdefghijklmnopqrstuvwxyz" |
| 756 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; |
| 757 | static const char *special = ".,:;'\"`~!^-+"; |
| 758 | |
| 759 | static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a, |
| 760 | char c, bool ovw) |
| 761 | { |
| 762 | int x, y; |
| 763 | for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++) |
| 764 | for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++) |
| 765 | if (map[y][x] == ' ' || ovw) |
| 766 | map[y][x] = c; |
| 767 | } |
| 768 | |
| 769 | static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p, |
| 770 | char c) |
| 771 | { |
| 772 | map[p->y / ydiv][p->x / xdiv] = c; |
| 773 | } |
| 774 | |
| 775 | static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p) |
| 776 | { |
| 777 | return map[p->y / ydiv][p->x / xdiv]; |
| 778 | } |
| 779 | |
| 780 | static int map_width(int xdiv, int x0, int x1) |
| 781 | { |
| 782 | return (x1 / xdiv) - (x0 / xdiv) + 1; |
| 783 | } |
| 784 | |
| 785 | static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1) |
| 786 | { |
| 787 | char *p = map[yd] + (x0 / xdiv); |
| 788 | int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2; |
| 789 | if (w >= 0) { |
| 790 | p += w; |
| 791 | while (*nice) |
| 792 | *p++ = *nice++; |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | static void map_1d_info(char **map, int xdiv, int ydiv, char *nice, |
| 797 | struct tcm_area *a) |
| 798 | { |
| 799 | sprintf(nice, "%dK", tcm_sizeof(*a) * 4); |
| 800 | if (a->p0.y + 1 < a->p1.y) { |
| 801 | text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0, |
| 802 | 256 - 1); |
| 803 | } else if (a->p0.y < a->p1.y) { |
| 804 | if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1)) |
| 805 | text_map(map, xdiv, nice, a->p0.y / ydiv, |
| 806 | a->p0.x + xdiv, 256 - 1); |
| 807 | else if (strlen(nice) < map_width(xdiv, 0, a->p1.x)) |
| 808 | text_map(map, xdiv, nice, a->p1.y / ydiv, |
| 809 | 0, a->p1.y - xdiv); |
| 810 | } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) { |
| 811 | text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x); |
| 812 | } |
| 813 | } |
| 814 | |
| 815 | static void map_2d_info(char **map, int xdiv, int ydiv, char *nice, |
| 816 | struct tcm_area *a) |
| 817 | { |
| 818 | sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a)); |
| 819 | if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) |
| 820 | text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, |
| 821 | a->p0.x, a->p1.x); |
| 822 | } |
| 823 | |
| 824 | int tiler_map_show(struct seq_file *s, void *arg) |
| 825 | { |
| 826 | int xdiv = 2, ydiv = 1; |
| 827 | char **map = NULL, *global_map; |
| 828 | struct tiler_block *block; |
| 829 | struct tcm_area a, p; |
| 830 | int i; |
| 831 | const char *m2d = alphabet; |
| 832 | const char *a2d = special; |
| 833 | const char *m2dp = m2d, *a2dp = a2d; |
| 834 | char nice[128]; |
Andy Gross | 02646fb | 2012-03-05 10:48:38 -0600 | [diff] [blame] | 835 | int h_adj; |
| 836 | int w_adj; |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 837 | unsigned long flags; |
| 838 | |
Andy Gross | 02646fb | 2012-03-05 10:48:38 -0600 | [diff] [blame] | 839 | if (!omap_dmm) { |
| 840 | /* early return if dmm/tiler device is not initialized */ |
| 841 | return 0; |
| 842 | } |
| 843 | |
| 844 | h_adj = omap_dmm->lut_height / ydiv; |
| 845 | w_adj = omap_dmm->lut_width / xdiv; |
| 846 | |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 847 | map = kzalloc(h_adj * sizeof(*map), GFP_KERNEL); |
| 848 | global_map = kzalloc((w_adj + 1) * h_adj, GFP_KERNEL); |
| 849 | |
| 850 | if (!map || !global_map) |
| 851 | goto error; |
| 852 | |
| 853 | memset(global_map, ' ', (w_adj + 1) * h_adj); |
| 854 | for (i = 0; i < omap_dmm->lut_height; i++) { |
| 855 | map[i] = global_map + i * (w_adj + 1); |
| 856 | map[i][w_adj] = 0; |
| 857 | } |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 858 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 859 | |
| 860 | list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) { |
| 861 | if (block->fmt != TILFMT_PAGE) { |
| 862 | fill_map(map, xdiv, ydiv, &block->area, *m2dp, true); |
| 863 | if (!*++a2dp) |
| 864 | a2dp = a2d; |
| 865 | if (!*++m2dp) |
| 866 | m2dp = m2d; |
| 867 | map_2d_info(map, xdiv, ydiv, nice, &block->area); |
| 868 | } else { |
| 869 | bool start = read_map_pt(map, xdiv, ydiv, |
| 870 | &block->area.p0) |
| 871 | == ' '; |
| 872 | bool end = read_map_pt(map, xdiv, ydiv, &block->area.p1) |
| 873 | == ' '; |
| 874 | tcm_for_each_slice(a, block->area, p) |
| 875 | fill_map(map, xdiv, ydiv, &a, '=', true); |
| 876 | fill_map_pt(map, xdiv, ydiv, &block->area.p0, |
| 877 | start ? '<' : 'X'); |
| 878 | fill_map_pt(map, xdiv, ydiv, &block->area.p1, |
| 879 | end ? '>' : 'X'); |
| 880 | map_1d_info(map, xdiv, ydiv, nice, &block->area); |
| 881 | } |
| 882 | } |
| 883 | |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 884 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 885 | |
| 886 | if (s) { |
| 887 | seq_printf(s, "BEGIN DMM TILER MAP\n"); |
| 888 | for (i = 0; i < 128; i++) |
| 889 | seq_printf(s, "%03d:%s\n", i, map[i]); |
| 890 | seq_printf(s, "END TILER MAP\n"); |
| 891 | } else { |
| 892 | dev_dbg(omap_dmm->dev, "BEGIN DMM TILER MAP\n"); |
| 893 | for (i = 0; i < 128; i++) |
| 894 | dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]); |
| 895 | dev_dbg(omap_dmm->dev, "END TILER MAP\n"); |
| 896 | } |
| 897 | |
| 898 | error: |
| 899 | kfree(map); |
| 900 | kfree(global_map); |
| 901 | |
| 902 | return 0; |
| 903 | } |
| 904 | #endif |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 905 | |
| 906 | struct platform_driver omap_dmm_driver = { |
| 907 | .probe = omap_dmm_probe, |
| 908 | .remove = omap_dmm_remove, |
| 909 | .driver = { |
| 910 | .owner = THIS_MODULE, |
| 911 | .name = DMM_DRIVER_NAME, |
| 912 | }, |
| 913 | }; |
| 914 | |
| 915 | MODULE_LICENSE("GPL v2"); |
| 916 | MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>"); |
| 917 | MODULE_DESCRIPTION("OMAP DMM/Tiler Driver"); |
| 918 | MODULE_ALIAS("platform:" DMM_DRIVER_NAME); |