Marcin Kościelnicki | 304424e | 2010-03-01 00:18:39 +0000 | [diff] [blame] | 1 | #include "drmP.h" |
| 2 | #include "drm.h" |
| 3 | #include "nouveau_drv.h" |
| 4 | #include "nouveau_drm.h" |
| 5 | |
| 6 | int |
| 7 | nv50_fb_init(struct drm_device *dev) |
| 8 | { |
Marcin Kościelnicki | 304424e | 2010-03-01 00:18:39 +0000 | [diff] [blame] | 9 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 10 | |
Ben Skeggs | 4eb3033 | 2010-06-07 13:59:40 +1000 | [diff] [blame] | 11 | /* Not a clue what this is exactly. Without pointing it at a |
| 12 | * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) |
| 13 | * cause IOMMU "read from address 0" errors (rh#561267) |
| 14 | */ |
| 15 | nv_wr32(dev, 0x100c08, dev_priv->gart_info.sg_dummy_bus >> 8); |
| 16 | |
| 17 | /* This is needed to get meaningful information from 100c90 |
| 18 | * on traps. No idea what these values mean exactly. */ |
Marcin Kościelnicki | 304424e | 2010-03-01 00:18:39 +0000 | [diff] [blame] | 19 | switch (dev_priv->chipset) { |
| 20 | case 0x50: |
| 21 | nv_wr32(dev, 0x100c90, 0x0707ff); |
| 22 | break; |
| 23 | case 0xa5: |
| 24 | case 0xa8: |
| 25 | nv_wr32(dev, 0x100c90, 0x0d0fff); |
| 26 | break; |
| 27 | default: |
| 28 | nv_wr32(dev, 0x100c90, 0x1d07ff); |
| 29 | break; |
| 30 | } |
| 31 | |
| 32 | return 0; |
| 33 | } |
| 34 | |
| 35 | void |
| 36 | nv50_fb_takedown(struct drm_device *dev) |
| 37 | { |
| 38 | } |