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Chris Metcalf867e3592010-05-28 23:09:12 -04001/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_PCI_H
16#define _ASM_TILE_PCI_H
17
Chris Metcalff02cbbe2010-11-02 12:05:10 -040018#include <linux/pci.h>
Chris Metcalf12962262012-04-07 17:10:17 -040019#include <linux/numa.h>
Michael S. Tsirkin84550122011-11-29 20:42:56 +020020#include <asm-generic/pci_iomap.h>
Chris Metcalff02cbbe2010-11-02 12:05:10 -040021
Chris Metcalf12962262012-04-07 17:10:17 -040022#ifndef __tilegx__
23
Chris Metcalff02cbbe2010-11-02 12:05:10 -040024/*
25 * Structure of a PCI controller (host bridge)
26 */
27struct pci_controller {
28 int index; /* PCI domain number */
29 struct pci_bus *root_bus;
30
31 int first_busno;
32 int last_busno;
33
34 int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
35 int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
36
37 struct pci_ops *ops;
38
39 int irq_base; /* Base IRQ from the Hypervisor */
40 int plx_gen1; /* flag for PLX Gen 1 configuration */
41
42 /* Address ranges that are routed to this controller/bridge. */
43 struct resource mem_resources[3];
44};
Chris Metcalf867e3592010-05-28 23:09:12 -040045
46/*
Chris Metcalf12962262012-04-07 17:10:17 -040047 * This flag tells if the platform is TILEmpower that needs
48 * special configuration for the PLX switch chip.
49 */
50extern int tile_plx_gen1;
51
52static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
53
54#define TILE_NUM_PCIE 2
55
56#else
57
58#include <asm/page.h>
59#include <gxio/trio.h>
60
61/**
62 * We reserve the hugepage-size address range at the top of the 64-bit address
63 * space to serve as the PCI window, emulating the BAR0 space of an endpoint
64 * device. This window is used by the chip-to-chip applications running on
65 * the RC node. The reason for carving out this window is that Mem-Maps that
66 * back up this window will not overlap with those that map the real physical
67 * memory.
68 */
69#define PCIE_HOST_BAR0_SIZE HPAGE_SIZE
70#define PCIE_HOST_BAR0_START HPAGE_MASK
71
72/**
73 * The first PAGE_SIZE of the above "BAR" window is mapped to the
74 * gxpci_host_regs structure.
75 */
76#define PCIE_HOST_REGS_SIZE PAGE_SIZE
77
78/*
79 * This is the PCI address where the Mem-Map interrupt regions start.
80 * We use the 2nd to the last huge page of the 64-bit address space.
81 * The last huge page is used for the rootcomplex "bar", for C2C purpose.
82 */
83#define MEM_MAP_INTR_REGIONS_BASE (HPAGE_MASK - HPAGE_SIZE)
84
85/*
86 * Each Mem-Map interrupt region occupies 4KB.
87 */
88#define MEM_MAP_INTR_REGION_SIZE (1<< TRIO_MAP_MEM_LIM__ADDR_SHIFT)
89
90/*
91 * Structure of a PCI controller (host bridge) on Gx.
92 */
93struct pci_controller {
94
95 /* Pointer back to the TRIO that this PCIe port is connected to. */
96 gxio_trio_context_t *trio;
97 int mac; /* PCIe mac index on the TRIO shim */
98 int trio_index; /* Index of TRIO shim that contains the MAC. */
99
100 int pio_mem_index; /* PIO region index for memory access */
101
102 /*
103 * Mem-Map regions for all the memory controllers so that Linux can
104 * map all of its physical memory space to the PCI bus.
105 */
106 int mem_maps[MAX_NUMNODES];
107
108 int index; /* PCI domain number */
109 struct pci_bus *root_bus;
110
111 int last_busno;
112
113 struct pci_ops *ops;
114
115 /* Table that maps the INTx numbers to Linux irq numbers. */
116 int irq_intx_table[4];
117
118 struct resource mem_space;
119
120 /* Address ranges that are routed to this controller/bridge. */
121 struct resource mem_resources[3];
122};
123
124extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
125extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
126
127extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
128
129#endif /* __tilegx__ */
130
131/*
Chris Metcalf867e3592010-05-28 23:09:12 -0400132 * The hypervisor maps the entirety of CPA-space as bus addresses, so
133 * bus addresses are physical addresses. The networking and block
134 * device layers use this boolean for bounce buffer decisions.
135 */
136#define PCI_DMA_BUS_IS_PHYS 1
137
Chris Metcalf05ef1b72012-04-25 12:45:26 -0400138int __init tile_pci_init(void);
139int __init pcibios_init(void);
Chris Metcalff02cbbe2010-11-02 12:05:10 -0400140
Chris Metcalf867e3592010-05-28 23:09:12 -0400141void __devinit pcibios_fixup_bus(struct pci_bus *bus);
142
Chris Metcalf867e3592010-05-28 23:09:12 -0400143#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
144
145/*
146 * This decides whether to display the domain number in /proc.
147 */
148static inline int pci_proc_domain(struct pci_bus *bus)
149{
150 return 1;
151}
152
153/*
Chris Metcalff02cbbe2010-11-02 12:05:10 -0400154 * pcibios_assign_all_busses() tells whether or not the bus numbers
155 * should be reassigned, in case the BIOS didn't do it correctly, or
156 * in case we don't have a BIOS and we want to let Linux do it.
Chris Metcalf867e3592010-05-28 23:09:12 -0400157 */
Chris Metcalff02cbbe2010-11-02 12:05:10 -0400158static inline int pcibios_assign_all_busses(void)
159{
160 return 1;
161}
Chris Metcalf867e3592010-05-28 23:09:12 -0400162
Chris Metcalf867e3592010-05-28 23:09:12 -0400163#define PCIBIOS_MIN_MEM 0
Chris Metcalff02cbbe2010-11-02 12:05:10 -0400164#define PCIBIOS_MIN_IO 0
Chris Metcalf867e3592010-05-28 23:09:12 -0400165
Chris Metcalff02cbbe2010-11-02 12:05:10 -0400166/* Use any cpu for PCI. */
167#define cpumask_of_pcibus(bus) cpu_online_mask
Chris Metcalf867e3592010-05-28 23:09:12 -0400168
169/* implement the pci_ DMA API in terms of the generic device dma_ one */
170#include <asm-generic/pci-dma-compat.h>
171
172/* generic pci stuff */
173#include <asm-generic/pci.h>
174
Chris Metcalf867e3592010-05-28 23:09:12 -0400175#endif /* _ASM_TILE_PCI_H */