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Paul Walmsley657ebfa2010-02-22 22:09:20 -07001/*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/kernel.h>
20#include <linux/errno.h>
Paul Walmsley657ebfa2010-02-22 22:09:20 -070021#include <linux/clk.h>
22#include <linux/io.h>
Paul Walmsley657ebfa2010-02-22 22:09:20 -070023
Paul Walmsley657ebfa2010-02-22 22:09:20 -070024#include <plat/clock.h>
25
26#include "clock.h"
27#include "clock3xxx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070028#include "prm2xxx_3xxx.h"
Paul Walmsley657ebfa2010-02-22 22:09:20 -070029#include "prm-regbits-34xx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070030#include "cm2xxx_3xxx.h"
Paul Walmsley657ebfa2010-02-22 22:09:20 -070031#include "cm-regbits-34xx.h"
32
33/*
34 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
35 * that are sourced by DPLL5, and both of these require this clock
36 * to be at 120 MHz for proper operation.
37 */
38#define DPLL5_FREQ_FOR_USBHOST 120000000
39
40/* needed by omap3_core_dpll_m2_set_rate() */
41struct clk *sdrc_ick_p, *arm_fck_p;
42
43int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
44{
45 /*
46 * According to the 12-5 CDP code from TI, "Limitation 2.5"
47 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
48 * on DPLL4.
49 */
50 if (omap_rev() == OMAP3430_REV_ES1_0) {
51 pr_err("clock: DPLL4 cannot change rate due to "
52 "silicon 'Limitation 2.5' on 3430ES1.\n");
53 return -EINVAL;
54 }
55
56 return omap3_noncore_dpll_set_rate(clk, rate);
57}
58
59void __init omap3_clk_lock_dpll5(void)
60{
61 struct clk *dpll5_clk;
62 struct clk *dpll5_m2_clk;
63
64 dpll5_clk = clk_get(NULL, "dpll5_ck");
65 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
66 clk_enable(dpll5_clk);
67
Paul Walmsley657ebfa2010-02-22 22:09:20 -070068 /* Program dpll5_m2_clk divider for no division */
69 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
70 clk_enable(dpll5_m2_clk);
71 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
72
73 clk_disable(dpll5_m2_clk);
74 clk_disable(dpll5_clk);
75 return;
76}
77
78/* Common clock code */
79
Paul Walmsley657ebfa2010-02-22 22:09:20 -070080/*
Paul Walmsley4d30e822010-02-22 22:09:36 -070081 * Switch the MPU rate if specified on cmdline. We cannot do this
82 * early until cmdline is parsed. XXX This should be removed from the
83 * clock code and handled by the OPP layer code in the near future.
Paul Walmsley657ebfa2010-02-22 22:09:20 -070084 */
85static int __init omap3xxx_clk_arch_init(void)
86{
Paul Walmsley4d30e822010-02-22 22:09:36 -070087 int ret;
Paul Walmsley657ebfa2010-02-22 22:09:20 -070088
89 if (!cpu_is_omap34xx())
90 return 0;
91
Paul Walmsley4d30e822010-02-22 22:09:36 -070092 ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
93 if (!ret)
Paul Walmsleyf1f4b772010-12-21 21:08:14 -070094 omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
Paul Walmsley657ebfa2010-02-22 22:09:20 -070095
Paul Walmsley4d30e822010-02-22 22:09:36 -070096 return ret;
Paul Walmsley657ebfa2010-02-22 22:09:20 -070097}
Paul Walmsley4d30e822010-02-22 22:09:36 -070098
Paul Walmsley657ebfa2010-02-22 22:09:20 -070099arch_initcall(omap3xxx_clk_arch_init);
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