Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Maxime Coquelin 2015 |
| 3 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> |
| 4 | * License terms: GNU General Public License (GPL), version 2 |
| 5 | * |
| 6 | * Heavily based on Mediatek's pinctrl driver |
| 7 | */ |
| 8 | #include <linux/clk.h> |
Linus Walleij | 1300568 | 2016-02-05 23:47:13 +0100 | [diff] [blame^] | 9 | #include <linux/gpio/driver.h> |
Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 10 | #include <linux/io.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/of.h> |
| 13 | #include <linux/of_address.h> |
| 14 | #include <linux/of_device.h> |
| 15 | #include <linux/of_irq.h> |
| 16 | #include <linux/pinctrl/consumer.h> |
| 17 | #include <linux/pinctrl/machine.h> |
| 18 | #include <linux/pinctrl/pinconf.h> |
| 19 | #include <linux/pinctrl/pinconf-generic.h> |
| 20 | #include <linux/pinctrl/pinctrl.h> |
| 21 | #include <linux/pinctrl/pinmux.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/reset.h> |
| 24 | #include <linux/slab.h> |
| 25 | |
| 26 | #include <dt-bindings/pinctrl/pinctrl-stm32.h> |
| 27 | |
| 28 | #include "../core.h" |
| 29 | #include "../pinconf.h" |
| 30 | #include "../pinctrl-utils.h" |
| 31 | #include "pinctrl-stm32.h" |
| 32 | |
| 33 | #define STM32_GPIO_MODER 0x00 |
| 34 | #define STM32_GPIO_TYPER 0x04 |
| 35 | #define STM32_GPIO_SPEEDR 0x08 |
| 36 | #define STM32_GPIO_PUPDR 0x0c |
| 37 | #define STM32_GPIO_IDR 0x10 |
| 38 | #define STM32_GPIO_ODR 0x14 |
| 39 | #define STM32_GPIO_BSRR 0x18 |
| 40 | #define STM32_GPIO_LCKR 0x1c |
| 41 | #define STM32_GPIO_AFRL 0x20 |
| 42 | #define STM32_GPIO_AFRH 0x24 |
| 43 | |
| 44 | #define STM32_GPIO_PINS_PER_BANK 16 |
| 45 | |
| 46 | #define gpio_range_to_bank(chip) \ |
| 47 | container_of(chip, struct stm32_gpio_bank, range) |
| 48 | |
Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 49 | static const char * const stm32_gpio_functions[] = { |
| 50 | "gpio", "af0", "af1", |
| 51 | "af2", "af3", "af4", |
| 52 | "af5", "af6", "af7", |
| 53 | "af8", "af9", "af10", |
| 54 | "af11", "af12", "af13", |
| 55 | "af14", "af15", "analog", |
| 56 | }; |
| 57 | |
| 58 | struct stm32_pinctrl_group { |
| 59 | const char *name; |
| 60 | unsigned long config; |
| 61 | unsigned pin; |
| 62 | }; |
| 63 | |
| 64 | struct stm32_gpio_bank { |
| 65 | void __iomem *base; |
| 66 | struct clk *clk; |
| 67 | spinlock_t lock; |
| 68 | struct gpio_chip gpio_chip; |
| 69 | struct pinctrl_gpio_range range; |
| 70 | }; |
| 71 | |
| 72 | struct stm32_pinctrl { |
| 73 | struct device *dev; |
| 74 | struct pinctrl_dev *pctl_dev; |
| 75 | struct pinctrl_desc pctl_desc; |
| 76 | struct stm32_pinctrl_group *groups; |
| 77 | unsigned ngroups; |
| 78 | const char **grp_names; |
| 79 | struct stm32_gpio_bank *banks; |
| 80 | unsigned nbanks; |
| 81 | const struct stm32_pinctrl_match_data *match_data; |
| 82 | }; |
| 83 | |
| 84 | static inline int stm32_gpio_pin(int gpio) |
| 85 | { |
| 86 | return gpio % STM32_GPIO_PINS_PER_BANK; |
| 87 | } |
| 88 | |
| 89 | static inline u32 stm32_gpio_get_mode(u32 function) |
| 90 | { |
| 91 | switch (function) { |
| 92 | case STM32_PIN_GPIO: |
| 93 | return 0; |
| 94 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): |
| 95 | return 2; |
| 96 | case STM32_PIN_ANALOG: |
| 97 | return 3; |
| 98 | } |
| 99 | |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static inline u32 stm32_gpio_get_alt(u32 function) |
| 104 | { |
| 105 | switch (function) { |
| 106 | case STM32_PIN_GPIO: |
| 107 | return 0; |
| 108 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): |
| 109 | return function - 1; |
| 110 | case STM32_PIN_ANALOG: |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /* GPIO functions */ |
| 118 | |
| 119 | static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, |
| 120 | unsigned offset, int value) |
| 121 | { |
| 122 | if (!value) |
| 123 | offset += STM32_GPIO_PINS_PER_BANK; |
| 124 | |
| 125 | clk_enable(bank->clk); |
| 126 | |
| 127 | writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); |
| 128 | |
| 129 | clk_disable(bank->clk); |
| 130 | } |
| 131 | |
| 132 | static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 133 | { |
| 134 | return pinctrl_request_gpio(chip->base + offset); |
| 135 | } |
| 136 | |
| 137 | static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 138 | { |
| 139 | pinctrl_free_gpio(chip->base + offset); |
| 140 | } |
| 141 | |
| 142 | static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 143 | { |
Linus Walleij | 1300568 | 2016-02-05 23:47:13 +0100 | [diff] [blame^] | 144 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 145 | int ret; |
| 146 | |
| 147 | clk_enable(bank->clk); |
| 148 | |
| 149 | ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); |
| 150 | |
| 151 | clk_disable(bank->clk); |
| 152 | |
| 153 | return ret; |
| 154 | } |
| 155 | |
| 156 | static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 157 | { |
Linus Walleij | 1300568 | 2016-02-05 23:47:13 +0100 | [diff] [blame^] | 158 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 159 | |
| 160 | __stm32_gpio_set(bank, offset, value); |
| 161 | } |
| 162 | |
| 163 | static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 164 | { |
| 165 | return pinctrl_gpio_direction_input(chip->base + offset); |
| 166 | } |
| 167 | |
| 168 | static int stm32_gpio_direction_output(struct gpio_chip *chip, |
| 169 | unsigned offset, int value) |
| 170 | { |
Linus Walleij | 1300568 | 2016-02-05 23:47:13 +0100 | [diff] [blame^] | 171 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 172 | |
| 173 | __stm32_gpio_set(bank, offset, value); |
| 174 | pinctrl_gpio_direction_output(chip->base + offset); |
| 175 | |
| 176 | return 0; |
| 177 | } |
| 178 | |
| 179 | static struct gpio_chip stm32_gpio_template = { |
| 180 | .request = stm32_gpio_request, |
| 181 | .free = stm32_gpio_free, |
| 182 | .get = stm32_gpio_get, |
| 183 | .set = stm32_gpio_set, |
| 184 | .direction_input = stm32_gpio_direction_input, |
| 185 | .direction_output = stm32_gpio_direction_output, |
| 186 | }; |
| 187 | |
| 188 | /* Pinctrl functions */ |
| 189 | |
| 190 | static struct stm32_pinctrl_group * |
| 191 | stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) |
| 192 | { |
| 193 | int i; |
| 194 | |
| 195 | for (i = 0; i < pctl->ngroups; i++) { |
| 196 | struct stm32_pinctrl_group *grp = pctl->groups + i; |
| 197 | |
| 198 | if (grp->pin == pin) |
| 199 | return grp; |
| 200 | } |
| 201 | |
| 202 | return NULL; |
| 203 | } |
| 204 | |
| 205 | static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, |
| 206 | u32 pin_num, u32 fnum) |
| 207 | { |
| 208 | int i; |
| 209 | |
| 210 | for (i = 0; i < pctl->match_data->npins; i++) { |
| 211 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; |
| 212 | const struct stm32_desc_function *func = pin->functions; |
| 213 | |
| 214 | if (pin->pin.number != pin_num) |
| 215 | continue; |
| 216 | |
| 217 | while (func && func->name) { |
| 218 | if (func->num == fnum) |
| 219 | return true; |
| 220 | func++; |
| 221 | } |
| 222 | |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | return false; |
| 227 | } |
| 228 | |
| 229 | static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, |
| 230 | u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, |
| 231 | struct pinctrl_map **map, unsigned *reserved_maps, |
| 232 | unsigned *num_maps) |
| 233 | { |
| 234 | if (*num_maps == *reserved_maps) |
| 235 | return -ENOSPC; |
| 236 | |
| 237 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; |
| 238 | (*map)[*num_maps].data.mux.group = grp->name; |
| 239 | |
| 240 | if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { |
| 241 | dev_err(pctl->dev, "invalid function %d on pin %d .\n", |
| 242 | fnum, pin); |
| 243 | return -EINVAL; |
| 244 | } |
| 245 | |
| 246 | (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; |
| 247 | (*num_maps)++; |
| 248 | |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
| 253 | struct device_node *node, |
| 254 | struct pinctrl_map **map, |
| 255 | unsigned *reserved_maps, |
| 256 | unsigned *num_maps) |
| 257 | { |
| 258 | struct stm32_pinctrl *pctl; |
| 259 | struct stm32_pinctrl_group *grp; |
| 260 | struct property *pins; |
| 261 | u32 pinfunc, pin, func; |
| 262 | unsigned long *configs; |
| 263 | unsigned int num_configs; |
| 264 | bool has_config = 0; |
| 265 | unsigned reserve = 0; |
| 266 | int num_pins, num_funcs, maps_per_pin, i, err; |
| 267 | |
| 268 | pctl = pinctrl_dev_get_drvdata(pctldev); |
| 269 | |
| 270 | pins = of_find_property(node, "pinmux", NULL); |
| 271 | if (!pins) { |
| 272 | dev_err(pctl->dev, "missing pins property in node %s .\n", |
| 273 | node->name); |
| 274 | return -EINVAL; |
| 275 | } |
| 276 | |
| 277 | err = pinconf_generic_parse_dt_config(node, pctldev, &configs, |
| 278 | &num_configs); |
| 279 | if (err) |
| 280 | return err; |
| 281 | |
| 282 | if (num_configs) |
| 283 | has_config = 1; |
| 284 | |
| 285 | num_pins = pins->length / sizeof(u32); |
| 286 | num_funcs = num_pins; |
| 287 | maps_per_pin = 0; |
| 288 | if (num_funcs) |
| 289 | maps_per_pin++; |
| 290 | if (has_config && num_pins >= 1) |
| 291 | maps_per_pin++; |
| 292 | |
| 293 | if (!num_pins || !maps_per_pin) |
| 294 | return -EINVAL; |
| 295 | |
| 296 | reserve = num_pins * maps_per_pin; |
| 297 | |
| 298 | err = pinctrl_utils_reserve_map(pctldev, map, |
| 299 | reserved_maps, num_maps, reserve); |
| 300 | if (err) |
| 301 | return err; |
| 302 | |
| 303 | for (i = 0; i < num_pins; i++) { |
| 304 | err = of_property_read_u32_index(node, "pinmux", |
| 305 | i, &pinfunc); |
| 306 | if (err) |
| 307 | return err; |
| 308 | |
| 309 | pin = STM32_GET_PIN_NO(pinfunc); |
| 310 | func = STM32_GET_PIN_FUNC(pinfunc); |
| 311 | |
| 312 | if (pin >= pctl->match_data->npins) { |
| 313 | dev_err(pctl->dev, "invalid pin number.\n"); |
| 314 | return -EINVAL; |
| 315 | } |
| 316 | |
| 317 | if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { |
| 318 | dev_err(pctl->dev, "invalid function.\n"); |
| 319 | return -EINVAL; |
| 320 | } |
| 321 | |
| 322 | grp = stm32_pctrl_find_group_by_pin(pctl, pin); |
| 323 | if (!grp) { |
| 324 | dev_err(pctl->dev, "unable to match pin %d to group\n", |
| 325 | pin); |
| 326 | return -EINVAL; |
| 327 | } |
| 328 | |
| 329 | err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, |
| 330 | reserved_maps, num_maps); |
| 331 | if (err) |
| 332 | return err; |
| 333 | |
| 334 | if (has_config) { |
| 335 | err = pinctrl_utils_add_map_configs(pctldev, map, |
| 336 | reserved_maps, num_maps, grp->name, |
| 337 | configs, num_configs, |
| 338 | PIN_MAP_TYPE_CONFIGS_GROUP); |
| 339 | if (err) |
| 340 | return err; |
| 341 | } |
| 342 | } |
| 343 | |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
| 348 | struct device_node *np_config, |
| 349 | struct pinctrl_map **map, unsigned *num_maps) |
| 350 | { |
| 351 | struct device_node *np; |
| 352 | unsigned reserved_maps; |
| 353 | int ret; |
| 354 | |
| 355 | *map = NULL; |
| 356 | *num_maps = 0; |
| 357 | reserved_maps = 0; |
| 358 | |
| 359 | for_each_child_of_node(np_config, np) { |
| 360 | ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, |
| 361 | &reserved_maps, num_maps); |
| 362 | if (ret < 0) { |
| 363 | pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); |
| 364 | return ret; |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
| 371 | static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
| 372 | { |
| 373 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 374 | |
| 375 | return pctl->ngroups; |
| 376 | } |
| 377 | |
| 378 | static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, |
| 379 | unsigned group) |
| 380 | { |
| 381 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 382 | |
| 383 | return pctl->groups[group].name; |
| 384 | } |
| 385 | |
| 386 | static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, |
| 387 | unsigned group, |
| 388 | const unsigned **pins, |
| 389 | unsigned *num_pins) |
| 390 | { |
| 391 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 392 | |
| 393 | *pins = (unsigned *)&pctl->groups[group].pin; |
| 394 | *num_pins = 1; |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | static const struct pinctrl_ops stm32_pctrl_ops = { |
| 400 | .dt_node_to_map = stm32_pctrl_dt_node_to_map, |
| 401 | .dt_free_map = pinctrl_utils_dt_free_map, |
| 402 | .get_groups_count = stm32_pctrl_get_groups_count, |
| 403 | .get_group_name = stm32_pctrl_get_group_name, |
| 404 | .get_group_pins = stm32_pctrl_get_group_pins, |
| 405 | }; |
| 406 | |
| 407 | |
| 408 | /* Pinmux functions */ |
| 409 | |
| 410 | static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
| 411 | { |
| 412 | return ARRAY_SIZE(stm32_gpio_functions); |
| 413 | } |
| 414 | |
| 415 | static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, |
| 416 | unsigned selector) |
| 417 | { |
| 418 | return stm32_gpio_functions[selector]; |
| 419 | } |
| 420 | |
| 421 | static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, |
| 422 | unsigned function, |
| 423 | const char * const **groups, |
| 424 | unsigned * const num_groups) |
| 425 | { |
| 426 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 427 | |
| 428 | *groups = pctl->grp_names; |
| 429 | *num_groups = pctl->ngroups; |
| 430 | |
| 431 | return 0; |
| 432 | } |
| 433 | |
| 434 | static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, |
| 435 | int pin, u32 mode, u32 alt) |
| 436 | { |
| 437 | u32 val; |
| 438 | int alt_shift = (pin % 8) * 4; |
| 439 | int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; |
| 440 | unsigned long flags; |
| 441 | |
| 442 | clk_enable(bank->clk); |
| 443 | spin_lock_irqsave(&bank->lock, flags); |
| 444 | |
| 445 | val = readl_relaxed(bank->base + alt_offset); |
| 446 | val &= ~GENMASK(alt_shift + 3, alt_shift); |
| 447 | val |= (alt << alt_shift); |
| 448 | writel_relaxed(val, bank->base + alt_offset); |
| 449 | |
| 450 | val = readl_relaxed(bank->base + STM32_GPIO_MODER); |
| 451 | val &= ~GENMASK(pin * 2 + 1, pin * 2); |
| 452 | val |= mode << (pin * 2); |
| 453 | writel_relaxed(val, bank->base + STM32_GPIO_MODER); |
| 454 | |
| 455 | spin_unlock_irqrestore(&bank->lock, flags); |
| 456 | clk_disable(bank->clk); |
| 457 | } |
| 458 | |
| 459 | static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, |
| 460 | unsigned function, |
| 461 | unsigned group) |
| 462 | { |
| 463 | bool ret; |
| 464 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 465 | struct stm32_pinctrl_group *g = pctl->groups + group; |
| 466 | struct pinctrl_gpio_range *range; |
| 467 | struct stm32_gpio_bank *bank; |
| 468 | u32 mode, alt; |
| 469 | int pin; |
| 470 | |
| 471 | ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); |
| 472 | if (!ret) { |
| 473 | dev_err(pctl->dev, "invalid function %d on group %d .\n", |
| 474 | function, group); |
| 475 | return -EINVAL; |
| 476 | } |
| 477 | |
| 478 | range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); |
| 479 | bank = gpio_range_to_bank(range); |
| 480 | pin = stm32_gpio_pin(g->pin); |
| 481 | |
| 482 | mode = stm32_gpio_get_mode(function); |
| 483 | alt = stm32_gpio_get_alt(function); |
| 484 | |
| 485 | stm32_pmx_set_mode(bank, pin, mode, alt); |
| 486 | |
| 487 | return 0; |
| 488 | } |
| 489 | |
| 490 | static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 491 | struct pinctrl_gpio_range *range, unsigned gpio, |
| 492 | bool input) |
| 493 | { |
| 494 | struct stm32_gpio_bank *bank = gpio_range_to_bank(range); |
| 495 | int pin = stm32_gpio_pin(gpio); |
| 496 | |
| 497 | stm32_pmx_set_mode(bank, pin, !input, 0); |
| 498 | |
| 499 | return 0; |
| 500 | } |
| 501 | |
| 502 | static const struct pinmux_ops stm32_pmx_ops = { |
| 503 | .get_functions_count = stm32_pmx_get_funcs_cnt, |
| 504 | .get_function_name = stm32_pmx_get_func_name, |
| 505 | .get_function_groups = stm32_pmx_get_func_groups, |
| 506 | .set_mux = stm32_pmx_set_mux, |
| 507 | .gpio_set_direction = stm32_pmx_gpio_set_direction, |
| 508 | }; |
| 509 | |
| 510 | /* Pinconf functions */ |
| 511 | |
| 512 | static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, |
| 513 | unsigned offset, u32 drive) |
| 514 | { |
| 515 | unsigned long flags; |
| 516 | u32 val; |
| 517 | |
| 518 | clk_enable(bank->clk); |
| 519 | spin_lock_irqsave(&bank->lock, flags); |
| 520 | |
| 521 | val = readl_relaxed(bank->base + STM32_GPIO_TYPER); |
| 522 | val &= ~BIT(offset); |
| 523 | val |= drive << offset; |
| 524 | writel_relaxed(val, bank->base + STM32_GPIO_TYPER); |
| 525 | |
| 526 | spin_unlock_irqrestore(&bank->lock, flags); |
| 527 | clk_disable(bank->clk); |
| 528 | } |
| 529 | |
| 530 | static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, |
| 531 | unsigned offset, u32 speed) |
| 532 | { |
| 533 | unsigned long flags; |
| 534 | u32 val; |
| 535 | |
| 536 | clk_enable(bank->clk); |
| 537 | spin_lock_irqsave(&bank->lock, flags); |
| 538 | |
| 539 | val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); |
| 540 | val &= ~GENMASK(offset * 2 + 1, offset * 2); |
| 541 | val |= speed << (offset * 2); |
| 542 | writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); |
| 543 | |
| 544 | spin_unlock_irqrestore(&bank->lock, flags); |
| 545 | clk_disable(bank->clk); |
| 546 | } |
| 547 | |
| 548 | static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, |
| 549 | unsigned offset, u32 bias) |
| 550 | { |
| 551 | unsigned long flags; |
| 552 | u32 val; |
| 553 | |
| 554 | clk_enable(bank->clk); |
| 555 | spin_lock_irqsave(&bank->lock, flags); |
| 556 | |
| 557 | val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); |
| 558 | val &= ~GENMASK(offset * 2 + 1, offset * 2); |
| 559 | val |= bias << (offset * 2); |
| 560 | writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); |
| 561 | |
| 562 | spin_unlock_irqrestore(&bank->lock, flags); |
| 563 | clk_disable(bank->clk); |
| 564 | } |
| 565 | |
| 566 | static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, |
| 567 | unsigned int pin, enum pin_config_param param, |
| 568 | enum pin_config_param arg) |
| 569 | { |
| 570 | struct pinctrl_gpio_range *range; |
| 571 | struct stm32_gpio_bank *bank; |
| 572 | int offset, ret = 0; |
| 573 | |
| 574 | range = pinctrl_find_gpio_range_from_pin(pctldev, pin); |
| 575 | bank = gpio_range_to_bank(range); |
| 576 | offset = stm32_gpio_pin(pin); |
| 577 | |
| 578 | switch (param) { |
| 579 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
| 580 | stm32_pconf_set_driving(bank, offset, 0); |
| 581 | break; |
| 582 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 583 | stm32_pconf_set_driving(bank, offset, 1); |
| 584 | break; |
| 585 | case PIN_CONFIG_SLEW_RATE: |
| 586 | stm32_pconf_set_speed(bank, offset, arg); |
| 587 | break; |
| 588 | case PIN_CONFIG_BIAS_DISABLE: |
| 589 | stm32_pconf_set_bias(bank, offset, 0); |
| 590 | break; |
| 591 | case PIN_CONFIG_BIAS_PULL_UP: |
| 592 | stm32_pconf_set_bias(bank, offset, 1); |
| 593 | break; |
| 594 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 595 | stm32_pconf_set_bias(bank, offset, 2); |
| 596 | break; |
| 597 | case PIN_CONFIG_OUTPUT: |
| 598 | __stm32_gpio_set(bank, offset, arg); |
| 599 | ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); |
| 600 | break; |
| 601 | default: |
| 602 | ret = -EINVAL; |
| 603 | } |
| 604 | |
| 605 | return ret; |
| 606 | } |
| 607 | |
| 608 | static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, |
| 609 | unsigned group, |
| 610 | unsigned long *config) |
| 611 | { |
| 612 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 613 | |
| 614 | *config = pctl->groups[group].config; |
| 615 | |
| 616 | return 0; |
| 617 | } |
| 618 | |
| 619 | static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, |
| 620 | unsigned long *configs, unsigned num_configs) |
| 621 | { |
| 622 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 623 | struct stm32_pinctrl_group *g = &pctl->groups[group]; |
| 624 | int i, ret; |
| 625 | |
| 626 | for (i = 0; i < num_configs; i++) { |
| 627 | ret = stm32_pconf_parse_conf(pctldev, g->pin, |
| 628 | pinconf_to_config_param(configs[i]), |
| 629 | pinconf_to_config_argument(configs[i])); |
| 630 | if (ret < 0) |
| 631 | return ret; |
| 632 | |
| 633 | g->config = configs[i]; |
| 634 | } |
| 635 | |
| 636 | return 0; |
| 637 | } |
| 638 | |
| 639 | static const struct pinconf_ops stm32_pconf_ops = { |
| 640 | .pin_config_group_get = stm32_pconf_group_get, |
| 641 | .pin_config_group_set = stm32_pconf_group_set, |
| 642 | }; |
| 643 | |
| 644 | static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, |
| 645 | struct device_node *np) |
| 646 | { |
| 647 | int bank_nr = pctl->nbanks; |
| 648 | struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; |
| 649 | struct pinctrl_gpio_range *range = &bank->range; |
| 650 | struct device *dev = pctl->dev; |
| 651 | struct resource res; |
| 652 | struct reset_control *rstc; |
| 653 | int err, npins; |
| 654 | |
| 655 | rstc = of_reset_control_get(np, NULL); |
| 656 | if (!IS_ERR(rstc)) |
| 657 | reset_control_deassert(rstc); |
| 658 | |
| 659 | if (of_address_to_resource(np, 0, &res)) |
| 660 | return -ENODEV; |
| 661 | |
| 662 | bank->base = devm_ioremap_resource(dev, &res); |
| 663 | if (IS_ERR(bank->base)) |
| 664 | return PTR_ERR(bank->base); |
| 665 | |
| 666 | bank->clk = of_clk_get_by_name(np, NULL); |
| 667 | if (IS_ERR(bank->clk)) { |
| 668 | dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); |
| 669 | return PTR_ERR(bank->clk); |
| 670 | } |
| 671 | |
| 672 | err = clk_prepare(bank->clk); |
| 673 | if (err) { |
| 674 | dev_err(dev, "failed to prepare clk (%d)\n", err); |
| 675 | return err; |
| 676 | } |
| 677 | |
| 678 | npins = pctl->match_data->npins; |
| 679 | npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; |
| 680 | if (npins < 0) |
| 681 | return -EINVAL; |
| 682 | else if (npins > STM32_GPIO_PINS_PER_BANK) |
| 683 | npins = STM32_GPIO_PINS_PER_BANK; |
| 684 | |
| 685 | bank->gpio_chip = stm32_gpio_template; |
| 686 | bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; |
| 687 | bank->gpio_chip.ngpio = npins; |
| 688 | bank->gpio_chip.of_node = np; |
Linus Walleij | 1300568 | 2016-02-05 23:47:13 +0100 | [diff] [blame^] | 689 | bank->gpio_chip.parent = dev; |
Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 690 | spin_lock_init(&bank->lock); |
| 691 | |
| 692 | of_property_read_string(np, "st,bank-name", &range->name); |
| 693 | bank->gpio_chip.label = range->name; |
| 694 | |
| 695 | range->id = bank_nr; |
| 696 | range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; |
| 697 | range->npins = bank->gpio_chip.ngpio; |
| 698 | range->gc = &bank->gpio_chip; |
Linus Walleij | 1300568 | 2016-02-05 23:47:13 +0100 | [diff] [blame^] | 699 | err = gpiochip_add_data(&bank->gpio_chip, bank); |
Maxime Coquelin | aceb16d | 2016-01-14 13:16:30 +0100 | [diff] [blame] | 700 | if (err) { |
| 701 | dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); |
| 702 | return err; |
| 703 | } |
| 704 | |
| 705 | dev_info(dev, "%s bank added\n", range->name); |
| 706 | return 0; |
| 707 | } |
| 708 | |
| 709 | static int stm32_pctrl_build_state(struct platform_device *pdev) |
| 710 | { |
| 711 | struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); |
| 712 | int i; |
| 713 | |
| 714 | pctl->ngroups = pctl->match_data->npins; |
| 715 | |
| 716 | /* Allocate groups */ |
| 717 | pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, |
| 718 | sizeof(*pctl->groups), GFP_KERNEL); |
| 719 | if (!pctl->groups) |
| 720 | return -ENOMEM; |
| 721 | |
| 722 | /* We assume that one pin is one group, use pin name as group name. */ |
| 723 | pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, |
| 724 | sizeof(*pctl->grp_names), GFP_KERNEL); |
| 725 | if (!pctl->grp_names) |
| 726 | return -ENOMEM; |
| 727 | |
| 728 | for (i = 0; i < pctl->match_data->npins; i++) { |
| 729 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; |
| 730 | struct stm32_pinctrl_group *group = pctl->groups + i; |
| 731 | |
| 732 | group->name = pin->pin.name; |
| 733 | group->pin = pin->pin.number; |
| 734 | |
| 735 | pctl->grp_names[i] = pin->pin.name; |
| 736 | } |
| 737 | |
| 738 | return 0; |
| 739 | } |
| 740 | |
| 741 | int stm32_pctl_probe(struct platform_device *pdev) |
| 742 | { |
| 743 | struct device_node *np = pdev->dev.of_node; |
| 744 | struct device_node *child; |
| 745 | const struct of_device_id *match; |
| 746 | struct device *dev = &pdev->dev; |
| 747 | struct stm32_pinctrl *pctl; |
| 748 | struct pinctrl_pin_desc *pins; |
| 749 | int i, ret, banks = 0; |
| 750 | |
| 751 | if (!np) |
| 752 | return -EINVAL; |
| 753 | |
| 754 | match = of_match_device(dev->driver->of_match_table, dev); |
| 755 | if (!match || !match->data) |
| 756 | return -EINVAL; |
| 757 | |
| 758 | if (!of_find_property(np, "pins-are-numbered", NULL)) { |
| 759 | dev_err(dev, "only support pins-are-numbered format\n"); |
| 760 | return -EINVAL; |
| 761 | } |
| 762 | |
| 763 | pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); |
| 764 | if (!pctl) |
| 765 | return -ENOMEM; |
| 766 | |
| 767 | platform_set_drvdata(pdev, pctl); |
| 768 | |
| 769 | pctl->dev = dev; |
| 770 | pctl->match_data = match->data; |
| 771 | ret = stm32_pctrl_build_state(pdev); |
| 772 | if (ret) { |
| 773 | dev_err(dev, "build state failed: %d\n", ret); |
| 774 | return -EINVAL; |
| 775 | } |
| 776 | |
| 777 | for_each_child_of_node(np, child) |
| 778 | if (of_property_read_bool(child, "gpio-controller")) |
| 779 | banks++; |
| 780 | |
| 781 | if (!banks) { |
| 782 | dev_err(dev, "at least one GPIO bank is required\n"); |
| 783 | return -EINVAL; |
| 784 | } |
| 785 | |
| 786 | pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), |
| 787 | GFP_KERNEL); |
| 788 | if (!pctl->banks) |
| 789 | return -ENOMEM; |
| 790 | |
| 791 | for_each_child_of_node(np, child) { |
| 792 | if (of_property_read_bool(child, "gpio-controller")) { |
| 793 | ret = stm32_gpiolib_register_bank(pctl, child); |
| 794 | if (ret) |
| 795 | return ret; |
| 796 | |
| 797 | pctl->nbanks++; |
| 798 | } |
| 799 | } |
| 800 | |
| 801 | pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), |
| 802 | GFP_KERNEL); |
| 803 | if (!pins) |
| 804 | return -ENOMEM; |
| 805 | |
| 806 | for (i = 0; i < pctl->match_data->npins; i++) |
| 807 | pins[i] = pctl->match_data->pins[i].pin; |
| 808 | |
| 809 | pctl->pctl_desc.name = dev_name(&pdev->dev); |
| 810 | pctl->pctl_desc.owner = THIS_MODULE; |
| 811 | pctl->pctl_desc.pins = pins; |
| 812 | pctl->pctl_desc.npins = pctl->match_data->npins; |
| 813 | pctl->pctl_desc.confops = &stm32_pconf_ops; |
| 814 | pctl->pctl_desc.pctlops = &stm32_pctrl_ops; |
| 815 | pctl->pctl_desc.pmxops = &stm32_pmx_ops; |
| 816 | pctl->dev = &pdev->dev; |
| 817 | |
| 818 | pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl); |
| 819 | if (!pctl->pctl_dev) { |
| 820 | dev_err(&pdev->dev, "Failed pinctrl registration\n"); |
| 821 | return -EINVAL; |
| 822 | } |
| 823 | |
| 824 | for (i = 0; i < pctl->nbanks; i++) |
| 825 | pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); |
| 826 | |
| 827 | dev_info(dev, "Pinctrl STM32 initialized\n"); |
| 828 | |
| 829 | return 0; |
| 830 | } |
| 831 | |