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Shawn Guodfcd04b2011-09-08 15:09:35 +08001* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
2
3Required properties:
Jingchang Lue66ff0a2013-08-21 10:11:59 +08004- compatible :
5 - "fsl,imx1-i2c" for I2C compatible with the one integrated on i.MX1 SoC
6 - "fsl,imx21-i2c" for I2C compatible with the one integrated on i.MX21 SoC
7 - "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC
Shawn Guodfcd04b2011-09-08 15:09:35 +08008- reg : Should contain I2C/HS-I2C registers location and length
9- interrupts : Should contain I2C/HS-I2C interrupt
Matt Porter5d232112015-03-03 11:57:08 -050010- clocks : Should contain the I2C/HS-I2C clock specifier
Shawn Guodfcd04b2011-09-08 15:09:35 +080011
12Optional properties:
13- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
14 The absence of the propoerty indicates the default frequency 100 kHz.
Yao Yuance1a7882014-11-18 18:31:06 +080015- dmas: A list of two dma specifiers, one for each entry in dma-names.
16- dma-names: should contain "tx" and "rx".
Shawn Guodfcd04b2011-09-08 15:09:35 +080017
18Examples:
19
20i2c@83fc4000 { /* I2C2 on i.MX51 */
Shawn Guo5bdfba22012-09-14 15:19:00 +080021 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guodfcd04b2011-09-08 15:09:35 +080022 reg = <0x83fc4000 0x4000>;
23 interrupts = <63>;
24};
25
26i2c@70038000 { /* HS-I2C on i.MX51 */
Shawn Guo5bdfba22012-09-14 15:19:00 +080027 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guodfcd04b2011-09-08 15:09:35 +080028 reg = <0x70038000 0x4000>;
29 interrupts = <64>;
30 clock-frequency = <400000>;
31};
Yao Yuance1a7882014-11-18 18:31:06 +080032
33i2c0: i2c@40066000 { /* i2c0 on vf610 */
34 compatible = "fsl,vf610-i2c";
35 reg = <0x40066000 0x1000>;
36 interrupts =<0 71 0x04>;
37 dmas = <&edma0 0 50>,
38 <&edma0 0 51>;
39 dma-names = "rx","tx";
40};