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Andrew Victor877d7722007-05-11 20:49:56 +01001/*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12#include <linux/module.h>
13
Nicolas Pitrec9dfafb2011-08-02 10:21:36 -040014#include <asm/proc-fns.h>
Russell King80b02c12009-01-08 10:01:47 +000015#include <asm/irq.h>
Andrew Victor877d7722007-05-11 20:49:56 +010016#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
David Howells9f97da72012-03-28 18:30:01 +010018#include <asm/system_misc.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010019#include <mach/cpu.h>
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +080020#include <mach/at91_dbgu.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010021#include <mach/at91sam9rl.h>
22#include <mach/at91_pmc.h>
Andrew Victor877d7722007-05-11 20:49:56 +010023
Jean-Christophe PLAGNIOL-VILLARDa510b9b2012-10-30 06:41:28 +080024#include "at91_aic.h"
Jean-Christophe PLAGNIOL-VILLARDf0995d02012-10-30 08:11:24 +080025#include "at91_rstc.h"
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080026#include "soc.h"
Andrew Victor877d7722007-05-11 20:49:56 +010027#include "generic.h"
28#include "clock.h"
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +080029#include "sam9_smc.h"
Andrew Victor877d7722007-05-11 20:49:56 +010030
Andrew Victor877d7722007-05-11 20:49:56 +010031/* --------------------------------------------------------------------
32 * Clocks
33 * -------------------------------------------------------------------- */
34
35/*
36 * The peripheral clocks.
37 */
38static struct clk pioA_clk = {
39 .name = "pioA_clk",
40 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk pioB_clk = {
44 .name = "pioB_clk",
45 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk pioC_clk = {
49 .name = "pioC_clk",
50 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk pioD_clk = {
54 .name = "pioD_clk",
55 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart0_clk = {
59 .name = "usart0_clk",
60 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk usart1_clk = {
64 .name = "usart1_clk",
65 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk usart2_clk = {
69 .name = "usart2_clk",
70 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk usart3_clk = {
74 .name = "usart3_clk",
75 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk mmc_clk = {
79 .name = "mci_clk",
80 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk twi0_clk = {
84 .name = "twi0_clk",
85 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk twi1_clk = {
89 .name = "twi1_clk",
90 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk spi_clk = {
94 .name = "spi_clk",
95 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk ssc0_clk = {
99 .name = "ssc0_clk",
100 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk ssc1_clk = {
104 .name = "ssc1_clk",
105 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk tc0_clk = {
109 .name = "tc0_clk",
110 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk tc1_clk = {
114 .name = "tc1_clk",
115 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk tc2_clk = {
119 .name = "tc2_clk",
120 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
121 .type = CLK_TYPE_PERIPHERAL,
122};
Andrew Victorbb1ad682008-09-18 19:42:37 +0100123static struct clk pwm_clk = {
124 .name = "pwm_clk",
Andrew Victor877d7722007-05-11 20:49:56 +0100125 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk tsc_clk = {
129 .name = "tsc_clk",
130 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk dma_clk = {
134 .name = "dma_clk",
135 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk udphs_clk = {
139 .name = "udphs_clk",
140 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk lcdc_clk = {
144 .name = "lcdc_clk",
145 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk ac97_clk = {
149 .name = "ac97_clk",
150 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153
154static struct clk *periph_clocks[] __initdata = {
155 &pioA_clk,
156 &pioB_clk,
157 &pioC_clk,
158 &pioD_clk,
159 &usart0_clk,
160 &usart1_clk,
161 &usart2_clk,
162 &usart3_clk,
163 &mmc_clk,
164 &twi0_clk,
165 &twi1_clk,
166 &spi_clk,
167 &ssc0_clk,
168 &ssc1_clk,
169 &tc0_clk,
170 &tc1_clk,
171 &tc2_clk,
Andrew Victorbb1ad682008-09-18 19:42:37 +0100172 &pwm_clk,
Andrew Victor877d7722007-05-11 20:49:56 +0100173 &tsc_clk,
174 &dma_clk,
175 &udphs_clk,
176 &lcdc_clk,
177 &ac97_clk,
178 // irq0
179};
180
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100181static struct clk_lookup periph_clocks_lookups[] = {
Jean-Christophe PLAGNIOL-VILLARD9d871592011-06-21 14:24:33 +0800182 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
183 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100184 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
185 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
186 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
Bo Shen636036d22012-11-06 13:57:51 +0800187 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
188 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
Bo Shen099343c2012-11-07 11:41:41 +0800189 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
190 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
Nikolaus Vossfac368a2011-11-08 11:49:46 +0100191 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
192 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
Jean-Christophe PLAGNIOL-VILLARD619d4a42011-11-13 13:00:58 +0800193 CLKDEV_CON_ID("pioA", &pioA_clk),
194 CLKDEV_CON_ID("pioB", &pioB_clk),
195 CLKDEV_CON_ID("pioC", &pioC_clk),
196 CLKDEV_CON_ID("pioD", &pioD_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100197};
198
199static struct clk_lookup usart_clocks_lookups[] = {
200 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
201 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
202 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
203 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
204 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
205};
206
Andrew Victor877d7722007-05-11 20:49:56 +0100207/*
208 * The two programmable clocks.
209 * You must configure pin multiplexing to bring these signals out.
210 */
211static struct clk pck0 = {
212 .name = "pck0",
213 .pmc_mask = AT91_PMC_PCK0,
214 .type = CLK_TYPE_PROGRAMMABLE,
215 .id = 0,
216};
217static struct clk pck1 = {
218 .name = "pck1",
219 .pmc_mask = AT91_PMC_PCK1,
220 .type = CLK_TYPE_PROGRAMMABLE,
221 .id = 1,
222};
223
224static void __init at91sam9rl_register_clocks(void)
225{
226 int i;
227
228 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
229 clk_register(periph_clocks[i]);
230
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100231 clkdev_add_table(periph_clocks_lookups,
232 ARRAY_SIZE(periph_clocks_lookups));
233 clkdev_add_table(usart_clocks_lookups,
234 ARRAY_SIZE(usart_clocks_lookups));
235
Andrew Victor877d7722007-05-11 20:49:56 +0100236 clk_register(&pck0);
237 clk_register(&pck1);
238}
239
240/* --------------------------------------------------------------------
241 * GPIO
242 * -------------------------------------------------------------------- */
243
Jean-Christophe PLAGNIOL-VILLARD1a2d9152011-10-17 14:28:38 +0800244static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
Andrew Victor877d7722007-05-11 20:49:56 +0100245 {
246 .id = AT91SAM9RL_ID_PIOA,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800247 .regbase = AT91SAM9RL_BASE_PIOA,
Andrew Victor877d7722007-05-11 20:49:56 +0100248 }, {
249 .id = AT91SAM9RL_ID_PIOB,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800250 .regbase = AT91SAM9RL_BASE_PIOB,
Andrew Victor877d7722007-05-11 20:49:56 +0100251 }, {
252 .id = AT91SAM9RL_ID_PIOC,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800253 .regbase = AT91SAM9RL_BASE_PIOC,
Andrew Victor877d7722007-05-11 20:49:56 +0100254 }, {
255 .id = AT91SAM9RL_ID_PIOD,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800256 .regbase = AT91SAM9RL_BASE_PIOD,
Andrew Victor877d7722007-05-11 20:49:56 +0100257 }
258};
259
Andrew Victor877d7722007-05-11 20:49:56 +0100260/* --------------------------------------------------------------------
261 * AT91SAM9RL processor initialization
262 * -------------------------------------------------------------------- */
263
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800264static void __init at91sam9rl_map_io(void)
Andrew Victor877d7722007-05-11 20:49:56 +0100265{
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800266 unsigned long sram_size;
Andrew Victor877d7722007-05-11 20:49:56 +0100267
Jean-Christophe PLAGNIOL-VILLARD8c3583b2011-04-23 22:12:57 +0800268 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
Andrew Victor877d7722007-05-11 20:49:56 +0100269 case AT91_CIDR_SRAMSIZ_32K:
270 sram_size = 2 * SZ_16K;
271 break;
272 case AT91_CIDR_SRAMSIZ_16K:
273 default:
274 sram_size = SZ_16K;
275 }
276
Andrew Victor877d7722007-05-11 20:49:56 +0100277 /* Map SRAM */
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800278 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800279}
Andrew Victor877d7722007-05-11 20:49:56 +0100280
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800281static void __init at91sam9rl_ioremap_registers(void)
282{
Jean-Christophe PLAGNIOL-VILLARDf22deee2011-11-01 01:23:20 +0800283 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
Jean-Christophe PLAGNIOL-VILLARDe9f68b52011-11-18 01:25:52 +0800284 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
Jean-Christophe PLAGNIOL-VILLARDf363c402012-02-13 12:58:53 +0800285 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +0800286 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +0800287 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
Jean-Christophe PLAGNIOL-VILLARD4342d642011-11-27 23:15:50 +0800288 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800289}
290
Jean-Christophe PLAGNIOL-VILLARD46539372011-04-24 18:20:28 +0800291static void __init at91sam9rl_initialize(void)
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800292{
Jean-Christophe PLAGNIOL-VILLARD0d781712012-02-05 20:25:32 +0800293 arm_pm_idle = at91sam9_idle;
Russell King1b2073e2011-11-03 09:53:29 +0000294 arm_pm_restart = at91sam9_alt_restart;
Andrew Victor877d7722007-05-11 20:49:56 +0100295 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
296
Andrew Victor877d7722007-05-11 20:49:56 +0100297 /* Register GPIO subsystem */
298 at91_gpio_init(at91sam9rl_gpio, 4);
299}
300
301/* --------------------------------------------------------------------
302 * Interrupt initialization
303 * -------------------------------------------------------------------- */
304
305/*
306 * The default interrupt priority levels (0 = lowest, 7 = highest).
307 */
308static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
309 7, /* Advanced Interrupt Controller */
310 7, /* System Peripherals */
311 1, /* Parallel IO Controller A */
312 1, /* Parallel IO Controller B */
313 1, /* Parallel IO Controller C */
314 1, /* Parallel IO Controller D */
315 5, /* USART 0 */
316 5, /* USART 1 */
317 5, /* USART 2 */
318 5, /* USART 3 */
319 0, /* Multimedia Card Interface */
320 6, /* Two-Wire Interface 0 */
321 6, /* Two-Wire Interface 1 */
322 5, /* Serial Peripheral Interface */
323 4, /* Serial Synchronous Controller 0 */
324 4, /* Serial Synchronous Controller 1 */
325 0, /* Timer Counter 0 */
326 0, /* Timer Counter 1 */
327 0, /* Timer Counter 2 */
328 0,
329 0, /* Touch Screen Controller */
330 0, /* DMA Controller */
331 2, /* USB Device High speed port */
332 2, /* LCD Controller */
333 6, /* AC97 Controller */
334 0,
335 0,
336 0,
337 0,
338 0,
339 0,
340 0, /* Advanced Interrupt Controller */
341};
342
Jean-Christophe PLAGNIOL-VILLARD8d39e0fd02012-08-16 17:36:55 +0800343AT91_SOC_START(sam9rl)
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800344 .map_io = at91sam9rl_map_io,
Jean-Christophe PLAGNIOL-VILLARD92100c12011-04-23 15:28:34 +0800345 .default_irq_priority = at91sam9rl_default_irq_priority,
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800346 .ioremap_registers = at91sam9rl_ioremap_registers,
Jean-Christophe PLAGNIOL-VILLARD51ddec72011-04-24 18:15:34 +0800347 .register_clocks = at91sam9rl_register_clocks,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800348 .init = at91sam9rl_initialize,
Jean-Christophe PLAGNIOL-VILLARD8d39e0fd02012-08-16 17:36:55 +0800349AT91_SOC_END