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Jeff Ohlsteine14411d2010-11-30 13:06:36 -08001/*
2 * Copyright (C) 2002 ARM Ltd.
3 * All Rights Reserved
4 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/errno.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/jiffies.h>
16#include <linux/smp.h>
17#include <linux/io.h>
Rob Herring520f7bd2012-12-27 13:10:24 -060018#include <linux/irqchip/arm-gic.h>
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080019
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080020#include <asm/cacheflush.h>
Jeff Ohlstein41ff4452011-04-07 17:41:09 -070021#include <asm/cputype.h>
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080022#include <asm/mach-types.h>
Will Deaconeb504392012-01-20 12:01:12 +010023#include <asm/smp_plat.h>
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080024
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080025#include "scm-boot.h"
David Brownbe2109e2012-09-12 16:01:40 -070026#include "common.h"
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080027
28#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
29#define SCSS_CPU1CORE_RESET 0xD80
30#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
31
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080032extern void msm_secondary_startup(void);
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080033
34static DEFINE_SPINLOCK(boot_lock);
35
Jeff Ohlstein41ff4452011-04-07 17:41:09 -070036static inline int get_core_count(void)
37{
38 /* 1 + the PART[1:0] field of MIDR */
39 return ((read_cpuid_id() >> 4) & 3) + 1;
40}
41
Marc Zyngier44ea3492011-09-08 13:15:22 +010042static void __cpuinit msm_secondary_init(unsigned int cpu)
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080043{
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080044 /*
45 * if any interrupts are already enabled for the primary
46 * core (e.g. timer irq), then they will not have been enabled
47 * for us: do so
48 */
49 gic_secondary_init(0);
50
51 /*
52 * let the primary processor know we're out of the
53 * pen, then head off into the C entry point
54 */
55 pen_release = -1;
56 smp_wmb();
57
58 /*
59 * Synchronise with the boot thread.
60 */
61 spin_lock(&boot_lock);
62 spin_unlock(&boot_lock);
63}
64
65static __cpuinit void prepare_cold_cpu(unsigned int cpu)
66{
67 int ret;
68 ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
69 SCM_FLAG_COLDBOOT_CPU1);
70 if (ret == 0) {
Stephen Boyd2b222a22011-09-19 10:54:04 -070071 void __iomem *sc1_base_ptr;
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080072 sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
73 if (sc1_base_ptr) {
74 writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
75 writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
76 writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
77 iounmap(sc1_base_ptr);
78 }
79 } else
80 printk(KERN_DEBUG "Failed to set secondary core boot "
81 "address\n");
82}
83
Marc Zyngier44ea3492011-09-08 13:15:22 +010084static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
Jeff Ohlsteine14411d2010-11-30 13:06:36 -080085{
86 unsigned long timeout;
87 static int cold_boot_done;
88
89 /* Only need to bring cpu out of reset this way once */
90 if (cold_boot_done == false) {
91 prepare_cold_cpu(cpu);
92 cold_boot_done = true;
93 }
94
95 /*
96 * set synchronisation state between this boot processor
97 * and the secondary one
98 */
99 spin_lock(&boot_lock);
100
101 /*
102 * The secondary processor is waiting to be released from
103 * the holding pen - release it, then wait for it to flag
104 * that it has been released by resetting pen_release.
105 *
106 * Note that "pen_release" is the hardware CPU ID, whereas
107 * "cpu" is Linux's internal ID.
108 */
Will Deacon1d3cfb32011-08-09 12:02:27 +0100109 pen_release = cpu_logical_map(cpu);
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800110 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
111 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
112
113 /*
114 * Send the secondary CPU a soft interrupt, thereby causing
115 * the boot monitor to read the system wide flags register,
116 * and branch to the address found there.
117 */
Rob Herringb1cffeb2012-11-26 15:05:48 -0600118 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800119
120 timeout = jiffies + (1 * HZ);
121 while (time_before(jiffies, timeout)) {
122 smp_rmb();
123 if (pen_release == -1)
124 break;
125
126 udelay(10);
127 }
128
129 /*
130 * now the secondary core is starting up let it run its
131 * calibrations, then wait for it to finish
132 */
133 spin_unlock(&boot_lock);
134
135 return pen_release != -1 ? -ENOSYS : 0;
136}
137
138/*
139 * Initialise the CPU possible map early - this describes the CPUs
140 * which may be present or become present in the system. The msm8x60
141 * does not support the ARM SCU, so just set the possible cpu mask to
142 * NR_CPUS.
143 */
Marc Zyngier44ea3492011-09-08 13:15:22 +0100144static void __init msm_smp_init_cpus(void)
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800145{
Jeff Ohlstein41ff4452011-04-07 17:41:09 -0700146 unsigned int i, ncores = get_core_count();
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800147
Russell Kinga06f9162011-10-20 22:04:18 +0100148 if (ncores > nr_cpu_ids) {
149 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
150 ncores, nr_cpu_ids);
151 ncores = nr_cpu_ids;
152 }
153
Jeff Ohlstein41ff4452011-04-07 17:41:09 -0700154 for (i = 0; i < ncores; i++)
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800155 set_cpu_possible(i, true);
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800156}
157
Marc Zyngier44ea3492011-09-08 13:15:22 +0100158static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800159{
Jeff Ohlsteine14411d2010-11-30 13:06:36 -0800160}
Marc Zyngier44ea3492011-09-08 13:15:22 +0100161
162struct smp_operations msm_smp_ops __initdata = {
163 .smp_init_cpus = msm_smp_init_cpus,
164 .smp_prepare_cpus = msm_smp_prepare_cpus,
165 .smp_secondary_init = msm_secondary_init,
166 .smp_boot_secondary = msm_boot_secondary,
167#ifdef CONFIG_HOTPLUG_CPU
168 .cpu_die = msm_cpu_die,
169#endif
170};