Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2003-2005 Silicon Graphics, Inc. All Rights Reserved. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/types.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/pci.h> |
| 12 | #include <asm/sn/sn_sal.h> |
| 13 | #include <asm/sn/addrs.h> |
Tony Luck | 1fa9295 | 2005-09-09 11:41:12 -0700 | [diff] [blame] | 14 | #include <asm/sn/io.h> |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 15 | #include <asm/sn/pcidev.h> |
| 16 | #include <asm/sn/pcibus_provider_defs.h> |
| 17 | #include <asm/sn/tioce_provider.h> |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 18 | #include <asm/sn/sn2/sn_hwperf.h> |
| 19 | |
| 20 | /* |
| 21 | * 1/26/2006 |
| 22 | * |
| 23 | * WAR for SGI PV 944642. For revA TIOCE, need to use the following recipe |
| 24 | * (taken from the above PV) before and after accessing tioce internal MMR's |
| 25 | * to avoid tioce lockups. |
| 26 | * |
| 27 | * The recipe as taken from the PV: |
| 28 | * |
| 29 | * if(mmr address < 0x45000) { |
| 30 | * if(mmr address == 0 or 0x80) |
| 31 | * mmr wrt or read address 0xc0 |
| 32 | * else if(mmr address == 0x148 or 0x200) |
| 33 | * mmr wrt or read address 0x28 |
| 34 | * else |
| 35 | * mmr wrt or read address 0x158 |
| 36 | * |
| 37 | * do desired mmr access (rd or wrt) |
| 38 | * |
| 39 | * if(mmr address == 0x100) |
| 40 | * mmr wrt or read address 0x38 |
| 41 | * mmr wrt or read address 0xb050 |
| 42 | * } else |
| 43 | * do desired mmr access |
| 44 | * |
| 45 | * According to hw, we can use reads instead of writes to the above addres |
| 46 | * |
| 47 | * Note this WAR can only to be used for accessing internal MMR's in the |
| 48 | * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the |
| 49 | * "Local CE Registers and Memories" and "PCI Compatible Config Space" address |
| 50 | * spaces from table 2-1 of the "CE Programmer's Reference Overview" document. |
| 51 | * |
| 52 | * All registers defined in struct tioce will meet that criteria. |
| 53 | */ |
| 54 | |
| 55 | static void inline |
| 56 | tioce_mmr_war_pre(struct tioce_kernel *kern, void *mmr_addr) |
| 57 | { |
| 58 | u64 mmr_base; |
| 59 | u64 mmr_offset; |
| 60 | |
| 61 | if (kern->ce_common->ce_rev != TIOCE_REV_A) |
| 62 | return; |
| 63 | |
| 64 | mmr_base = kern->ce_common->ce_pcibus.bs_base; |
| 65 | mmr_offset = (u64)mmr_addr - mmr_base; |
| 66 | |
| 67 | if (mmr_offset < 0x45000) { |
| 68 | u64 mmr_war_offset; |
| 69 | |
| 70 | if (mmr_offset == 0 || mmr_offset == 0x80) |
| 71 | mmr_war_offset = 0xc0; |
| 72 | else if (mmr_offset == 0x148 || mmr_offset == 0x200) |
| 73 | mmr_war_offset = 0x28; |
| 74 | else |
| 75 | mmr_war_offset = 0x158; |
| 76 | |
| 77 | readq_relaxed((void *)(mmr_base + mmr_war_offset)); |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | static void inline |
| 82 | tioce_mmr_war_post(struct tioce_kernel *kern, void *mmr_addr) |
| 83 | { |
| 84 | u64 mmr_base; |
| 85 | u64 mmr_offset; |
| 86 | |
| 87 | if (kern->ce_common->ce_rev != TIOCE_REV_A) |
| 88 | return; |
| 89 | |
| 90 | mmr_base = kern->ce_common->ce_pcibus.bs_base; |
| 91 | mmr_offset = (u64)mmr_addr - mmr_base; |
| 92 | |
| 93 | if (mmr_offset < 0x45000) { |
| 94 | if (mmr_offset == 0x100) |
| 95 | readq_relaxed((void *)(mmr_base + 0x38)); |
| 96 | readq_relaxed((void *)(mmr_base + 0xb050)); |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | /* load mmr contents into a variable */ |
| 101 | #define tioce_mmr_load(kern, mmrp, varp) do {\ |
| 102 | tioce_mmr_war_pre(kern, mmrp); \ |
| 103 | *(varp) = readq_relaxed(mmrp); \ |
| 104 | tioce_mmr_war_post(kern, mmrp); \ |
| 105 | } while (0) |
| 106 | |
| 107 | /* store variable contents into mmr */ |
| 108 | #define tioce_mmr_store(kern, mmrp, varp) do {\ |
| 109 | tioce_mmr_war_pre(kern, mmrp); \ |
| 110 | writeq(*varp, mmrp); \ |
| 111 | tioce_mmr_war_post(kern, mmrp); \ |
| 112 | } while (0) |
| 113 | |
| 114 | /* store immediate value into mmr */ |
| 115 | #define tioce_mmr_storei(kern, mmrp, val) do {\ |
| 116 | tioce_mmr_war_pre(kern, mmrp); \ |
| 117 | writeq(val, mmrp); \ |
| 118 | tioce_mmr_war_post(kern, mmrp); \ |
| 119 | } while (0) |
| 120 | |
| 121 | /* set bits (immediate value) into mmr */ |
| 122 | #define tioce_mmr_seti(kern, mmrp, bits) do {\ |
| 123 | u64 tmp; \ |
| 124 | tioce_mmr_load(kern, mmrp, &tmp); \ |
| 125 | tmp |= (bits); \ |
| 126 | tioce_mmr_store(kern, mmrp, &tmp); \ |
| 127 | } while (0) |
| 128 | |
| 129 | /* clear bits (immediate value) into mmr */ |
| 130 | #define tioce_mmr_clri(kern, mmrp, bits) do { \ |
| 131 | u64 tmp; \ |
| 132 | tioce_mmr_load(kern, mmrp, &tmp); \ |
| 133 | tmp &= ~(bits); \ |
| 134 | tioce_mmr_store(kern, mmrp, &tmp); \ |
| 135 | } while (0) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 136 | |
| 137 | /** |
| 138 | * Bus address ranges for the 5 flavors of TIOCE DMA |
| 139 | */ |
| 140 | |
| 141 | #define TIOCE_D64_MIN 0x8000000000000000UL |
| 142 | #define TIOCE_D64_MAX 0xffffffffffffffffUL |
| 143 | #define TIOCE_D64_ADDR(a) ((a) >= TIOCE_D64_MIN) |
| 144 | |
| 145 | #define TIOCE_D32_MIN 0x0000000080000000UL |
| 146 | #define TIOCE_D32_MAX 0x00000000ffffffffUL |
| 147 | #define TIOCE_D32_ADDR(a) ((a) >= TIOCE_D32_MIN && (a) <= TIOCE_D32_MAX) |
| 148 | |
| 149 | #define TIOCE_M32_MIN 0x0000000000000000UL |
| 150 | #define TIOCE_M32_MAX 0x000000007fffffffUL |
| 151 | #define TIOCE_M32_ADDR(a) ((a) >= TIOCE_M32_MIN && (a) <= TIOCE_M32_MAX) |
| 152 | |
| 153 | #define TIOCE_M40_MIN 0x0000004000000000UL |
| 154 | #define TIOCE_M40_MAX 0x0000007fffffffffUL |
| 155 | #define TIOCE_M40_ADDR(a) ((a) >= TIOCE_M40_MIN && (a) <= TIOCE_M40_MAX) |
| 156 | |
| 157 | #define TIOCE_M40S_MIN 0x0000008000000000UL |
| 158 | #define TIOCE_M40S_MAX 0x000000ffffffffffUL |
| 159 | #define TIOCE_M40S_ADDR(a) ((a) >= TIOCE_M40S_MIN && (a) <= TIOCE_M40S_MAX) |
| 160 | |
| 161 | /* |
| 162 | * ATE manipulation macros. |
| 163 | */ |
| 164 | |
| 165 | #define ATE_PAGESHIFT(ps) (__ffs(ps)) |
| 166 | #define ATE_PAGEMASK(ps) ((ps)-1) |
| 167 | |
| 168 | #define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps)) |
| 169 | #define ATE_NPAGES(start, len, pagesize) \ |
| 170 | (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1) |
| 171 | |
| 172 | #define ATE_VALID(ate) ((ate) & (1UL << 63)) |
| 173 | #define ATE_MAKE(addr, ps) (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63)) |
| 174 | |
| 175 | /* |
| 176 | * Flavors of ate-based mapping supported by tioce_alloc_map() |
| 177 | */ |
| 178 | |
| 179 | #define TIOCE_ATE_M32 1 |
| 180 | #define TIOCE_ATE_M40 2 |
| 181 | #define TIOCE_ATE_M40S 3 |
| 182 | |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 183 | #define KB(x) ((u64)(x) << 10) |
| 184 | #define MB(x) ((u64)(x) << 20) |
| 185 | #define GB(x) ((u64)(x) << 30) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 186 | |
| 187 | /** |
| 188 | * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode |
| 189 | * @ct_addr: system coretalk address |
| 190 | * |
| 191 | * Map @ct_addr into 64-bit CE bus space. No device context is necessary |
| 192 | * and no CE mapping are consumed. |
| 193 | * |
| 194 | * Bits 53:0 come from the coretalk address. The remaining bits are set as |
| 195 | * follows: |
| 196 | * |
| 197 | * 63 - must be 1 to indicate d64 mode to CE hardware |
| 198 | * 62 - barrier bit ... controlled with tioce_dma_barrier() |
| 199 | * 61 - 0 since this is not an MSI transaction |
| 200 | * 60:54 - reserved, MBZ |
| 201 | */ |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 202 | static u64 |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 203 | tioce_dma_d64(unsigned long ct_addr) |
| 204 | { |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 205 | u64 bus_addr; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 206 | |
| 207 | bus_addr = ct_addr | (1UL << 63); |
| 208 | |
| 209 | return bus_addr; |
| 210 | } |
| 211 | |
| 212 | /** |
| 213 | * pcidev_to_tioce - return misc ce related pointers given a pci_dev |
| 214 | * @pci_dev: pci device context |
| 215 | * @base: ptr to store struct tioce_mmr * for the CE holding this device |
| 216 | * @kernel: ptr to store struct tioce_kernel * for the CE holding this device |
| 217 | * @port: ptr to store the CE port number that this device is on |
| 218 | * |
| 219 | * Return pointers to various CE-related structures for the CE upstream of |
| 220 | * @pci_dev. |
| 221 | */ |
| 222 | static inline void |
| 223 | pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base, |
| 224 | struct tioce_kernel **kernel, int *port) |
| 225 | { |
| 226 | struct pcidev_info *pcidev_info; |
| 227 | struct tioce_common *ce_common; |
| 228 | struct tioce_kernel *ce_kernel; |
| 229 | |
| 230 | pcidev_info = SN_PCIDEV_INFO(pdev); |
| 231 | ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; |
| 232 | ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private; |
| 233 | |
| 234 | if (base) |
| 235 | *base = (struct tioce *)ce_common->ce_pcibus.bs_base; |
| 236 | if (kernel) |
| 237 | *kernel = ce_kernel; |
| 238 | |
| 239 | /* |
| 240 | * we use port as a zero-based value internally, even though the |
| 241 | * documentation is 1-based. |
| 242 | */ |
| 243 | if (port) |
| 244 | *port = |
| 245 | (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1; |
| 246 | } |
| 247 | |
| 248 | /** |
| 249 | * tioce_alloc_map - Given a coretalk address, map it to pcie bus address |
| 250 | * space using one of the various ATE-based address modes. |
| 251 | * @ce_kern: tioce context |
| 252 | * @type: map mode to use |
| 253 | * @port: 0-based port that the requesting device is downstream of |
| 254 | * @ct_addr: the coretalk address to map |
| 255 | * @len: number of bytes to map |
| 256 | * |
| 257 | * Given the addressing type, set up various paramaters that define the |
| 258 | * ATE pool to use. Search for a contiguous block of entries to cover the |
| 259 | * length, and if enough resources exist, fill in the ATE's and construct a |
| 260 | * tioce_dmamap struct to track the mapping. |
| 261 | */ |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 262 | static u64 |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 263 | tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 264 | u64 ct_addr, int len) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 265 | { |
| 266 | int i; |
| 267 | int j; |
| 268 | int first; |
| 269 | int last; |
| 270 | int entries; |
| 271 | int nates; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 272 | u64 pagesize; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 273 | u64 *ate_shadow; |
| 274 | u64 *ate_reg; |
| 275 | u64 addr; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 276 | struct tioce *ce_mmr; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 277 | u64 bus_base; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 278 | struct tioce_dmamap *map; |
| 279 | |
| 280 | ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base; |
| 281 | |
| 282 | switch (type) { |
| 283 | case TIOCE_ATE_M32: |
| 284 | /* |
| 285 | * The first 64 entries of the ate3240 pool are dedicated to |
| 286 | * super-page (TIOCE_ATE_M40S) mode. |
| 287 | */ |
| 288 | first = 64; |
| 289 | entries = TIOCE_NUM_M3240_ATES - 64; |
| 290 | ate_shadow = ce_kern->ce_ate3240_shadow; |
| 291 | ate_reg = ce_mmr->ce_ure_ate3240; |
| 292 | pagesize = ce_kern->ce_ate3240_pagesize; |
| 293 | bus_base = TIOCE_M32_MIN; |
| 294 | break; |
| 295 | case TIOCE_ATE_M40: |
| 296 | first = 0; |
| 297 | entries = TIOCE_NUM_M40_ATES; |
| 298 | ate_shadow = ce_kern->ce_ate40_shadow; |
| 299 | ate_reg = ce_mmr->ce_ure_ate40; |
| 300 | pagesize = MB(64); |
| 301 | bus_base = TIOCE_M40_MIN; |
| 302 | break; |
| 303 | case TIOCE_ATE_M40S: |
| 304 | /* |
| 305 | * ate3240 entries 0-31 are dedicated to port1 super-page |
| 306 | * mappings. ate3240 entries 32-63 are dedicated to port2. |
| 307 | */ |
| 308 | first = port * 32; |
| 309 | entries = 32; |
| 310 | ate_shadow = ce_kern->ce_ate3240_shadow; |
| 311 | ate_reg = ce_mmr->ce_ure_ate3240; |
| 312 | pagesize = GB(16); |
| 313 | bus_base = TIOCE_M40S_MIN; |
| 314 | break; |
| 315 | default: |
| 316 | return 0; |
| 317 | } |
| 318 | |
| 319 | nates = ATE_NPAGES(ct_addr, len, pagesize); |
| 320 | if (nates > entries) |
| 321 | return 0; |
| 322 | |
| 323 | last = first + entries - nates; |
| 324 | for (i = first; i <= last; i++) { |
| 325 | if (ATE_VALID(ate_shadow[i])) |
| 326 | continue; |
| 327 | |
| 328 | for (j = i; j < i + nates; j++) |
| 329 | if (ATE_VALID(ate_shadow[j])) |
| 330 | break; |
| 331 | |
| 332 | if (j >= i + nates) |
| 333 | break; |
| 334 | } |
| 335 | |
| 336 | if (i > last) |
| 337 | return 0; |
| 338 | |
Panagiotis Issaris | baf47fb | 2005-11-09 02:08:42 +0100 | [diff] [blame] | 339 | map = kzalloc(sizeof(struct tioce_dmamap), GFP_ATOMIC); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 340 | if (!map) |
| 341 | return 0; |
| 342 | |
| 343 | addr = ct_addr; |
| 344 | for (j = 0; j < nates; j++) { |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 345 | u64 ate; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 346 | |
| 347 | ate = ATE_MAKE(addr, pagesize); |
| 348 | ate_shadow[i + j] = ate; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 349 | tioce_mmr_storei(ce_kern, &ate_reg[i + j], ate); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 350 | addr += pagesize; |
| 351 | } |
| 352 | |
| 353 | map->refcnt = 1; |
| 354 | map->nbytes = nates * pagesize; |
| 355 | map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize); |
| 356 | map->pci_start = bus_base + (i * pagesize); |
| 357 | map->ate_hw = &ate_reg[i]; |
| 358 | map->ate_shadow = &ate_shadow[i]; |
| 359 | map->ate_count = nates; |
| 360 | |
| 361 | list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list); |
| 362 | |
| 363 | return (map->pci_start + (ct_addr - map->ct_start)); |
| 364 | } |
| 365 | |
| 366 | /** |
| 367 | * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode |
| 368 | * @pdev: linux pci_dev representing the function |
| 369 | * @paddr: system physical address |
| 370 | * |
| 371 | * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info. |
| 372 | */ |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 373 | static u64 |
| 374 | tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 375 | { |
| 376 | int dma_ok; |
| 377 | int port; |
| 378 | struct tioce *ce_mmr; |
| 379 | struct tioce_kernel *ce_kern; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 380 | u64 ct_upper; |
| 381 | u64 ct_lower; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 382 | dma_addr_t bus_addr; |
| 383 | |
| 384 | ct_upper = ct_addr & ~0x3fffffffUL; |
| 385 | ct_lower = ct_addr & 0x3fffffffUL; |
| 386 | |
| 387 | pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); |
| 388 | |
| 389 | if (ce_kern->ce_port[port].dirmap_refcnt == 0) { |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 390 | u64 tmp; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 391 | |
| 392 | ce_kern->ce_port[port].dirmap_shadow = ct_upper; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 393 | tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port], |
| 394 | ct_upper); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 395 | tmp = ce_mmr->ce_ure_dir_map[port]; |
| 396 | dma_ok = 1; |
| 397 | } else |
| 398 | dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper); |
| 399 | |
| 400 | if (dma_ok) { |
| 401 | ce_kern->ce_port[port].dirmap_refcnt++; |
| 402 | bus_addr = TIOCE_D32_MIN + ct_lower; |
| 403 | } else |
| 404 | bus_addr = 0; |
| 405 | |
| 406 | return bus_addr; |
| 407 | } |
| 408 | |
| 409 | /** |
| 410 | * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude |
| 411 | * the barrier bit. |
| 412 | * @bus_addr: bus address to swizzle |
| 413 | * |
| 414 | * Given a TIOCE bus address, set the appropriate bit to indicate barrier |
| 415 | * attributes. |
| 416 | */ |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 417 | static u64 |
| 418 | tioce_dma_barrier(u64 bus_addr, int on) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 419 | { |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 420 | u64 barrier_bit; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 421 | |
| 422 | /* barrier not supported in M40/M40S mode */ |
| 423 | if (TIOCE_M40_ADDR(bus_addr) || TIOCE_M40S_ADDR(bus_addr)) |
| 424 | return bus_addr; |
| 425 | |
| 426 | if (TIOCE_D64_ADDR(bus_addr)) |
| 427 | barrier_bit = (1UL << 62); |
| 428 | else /* must be m32 or d32 */ |
| 429 | barrier_bit = (1UL << 30); |
| 430 | |
| 431 | return (on) ? (bus_addr | barrier_bit) : (bus_addr & ~barrier_bit); |
| 432 | } |
| 433 | |
| 434 | /** |
| 435 | * tioce_dma_unmap - release CE mapping resources |
| 436 | * @pdev: linux pci_dev representing the function |
| 437 | * @bus_addr: bus address returned by an earlier tioce_dma_map |
| 438 | * @dir: mapping direction (unused) |
| 439 | * |
| 440 | * Locate mapping resources associated with @bus_addr and release them. |
| 441 | * For mappings created using the direct modes there are no resources |
| 442 | * to release. |
| 443 | */ |
| 444 | void |
| 445 | tioce_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) |
| 446 | { |
| 447 | int i; |
| 448 | int port; |
| 449 | struct tioce_kernel *ce_kern; |
| 450 | struct tioce *ce_mmr; |
| 451 | unsigned long flags; |
| 452 | |
| 453 | bus_addr = tioce_dma_barrier(bus_addr, 0); |
| 454 | pcidev_to_tioce(pdev, &ce_mmr, &ce_kern, &port); |
| 455 | |
| 456 | /* nothing to do for D64 */ |
| 457 | |
| 458 | if (TIOCE_D64_ADDR(bus_addr)) |
| 459 | return; |
| 460 | |
| 461 | spin_lock_irqsave(&ce_kern->ce_lock, flags); |
| 462 | |
| 463 | if (TIOCE_D32_ADDR(bus_addr)) { |
| 464 | if (--ce_kern->ce_port[port].dirmap_refcnt == 0) { |
| 465 | ce_kern->ce_port[port].dirmap_shadow = 0; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 466 | tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port], |
| 467 | 0); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 468 | } |
| 469 | } else { |
| 470 | struct tioce_dmamap *map; |
| 471 | |
| 472 | list_for_each_entry(map, &ce_kern->ce_dmamap_list, |
| 473 | ce_dmamap_list) { |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 474 | u64 last; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 475 | |
| 476 | last = map->pci_start + map->nbytes - 1; |
| 477 | if (bus_addr >= map->pci_start && bus_addr <= last) |
| 478 | break; |
| 479 | } |
| 480 | |
| 481 | if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) { |
| 482 | printk(KERN_WARNING |
| 483 | "%s: %s - no map found for bus_addr 0x%lx\n", |
| 484 | __FUNCTION__, pci_name(pdev), bus_addr); |
| 485 | } else if (--map->refcnt == 0) { |
| 486 | for (i = 0; i < map->ate_count; i++) { |
| 487 | map->ate_shadow[i] = 0; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 488 | tioce_mmr_storei(ce_kern, &map->ate_hw[i], 0); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | list_del(&map->ce_dmamap_list); |
| 492 | kfree(map); |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | spin_unlock_irqrestore(&ce_kern->ce_lock, flags); |
| 497 | } |
| 498 | |
| 499 | /** |
| 500 | * tioce_do_dma_map - map pages for PCI DMA |
| 501 | * @pdev: linux pci_dev representing the function |
| 502 | * @paddr: host physical address to map |
| 503 | * @byte_count: bytes to map |
| 504 | * |
| 505 | * This is the main wrapper for mapping host physical pages to CE PCI space. |
| 506 | * The mapping mode used is based on the device's dma_mask. |
| 507 | */ |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 508 | static u64 |
| 509 | tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 510 | int barrier) |
| 511 | { |
| 512 | unsigned long flags; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 513 | u64 ct_addr; |
| 514 | u64 mapaddr = 0; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 515 | struct tioce_kernel *ce_kern; |
| 516 | struct tioce_dmamap *map; |
| 517 | int port; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 518 | u64 dma_mask; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 519 | |
| 520 | dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask; |
| 521 | |
| 522 | /* cards must be able to address at least 31 bits */ |
| 523 | if (dma_mask < 0x7fffffffUL) |
| 524 | return 0; |
| 525 | |
| 526 | ct_addr = PHYS_TO_TIODMA(paddr); |
| 527 | |
| 528 | /* |
| 529 | * If the device can generate 64 bit addresses, create a D64 map. |
| 530 | * Since this should never fail, bypass the rest of the checks. |
| 531 | */ |
| 532 | if (dma_mask == ~0UL) { |
| 533 | mapaddr = tioce_dma_d64(ct_addr); |
| 534 | goto dma_map_done; |
| 535 | } |
| 536 | |
| 537 | pcidev_to_tioce(pdev, NULL, &ce_kern, &port); |
| 538 | |
| 539 | spin_lock_irqsave(&ce_kern->ce_lock, flags); |
| 540 | |
| 541 | /* |
| 542 | * D64 didn't work ... See if we have an existing map that covers |
| 543 | * this address range. Must account for devices dma_mask here since |
| 544 | * an existing map might have been done in a mode using more pci |
| 545 | * address bits than this device can support. |
| 546 | */ |
| 547 | list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) { |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 548 | u64 last; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 549 | |
| 550 | last = map->ct_start + map->nbytes - 1; |
| 551 | if (ct_addr >= map->ct_start && |
| 552 | ct_addr + byte_count - 1 <= last && |
| 553 | map->pci_start <= dma_mask) { |
| 554 | map->refcnt++; |
| 555 | mapaddr = map->pci_start + (ct_addr - map->ct_start); |
| 556 | break; |
| 557 | } |
| 558 | } |
| 559 | |
| 560 | /* |
| 561 | * If we don't have a map yet, and the card can generate 40 |
| 562 | * bit addresses, try the M40/M40S modes. Note these modes do not |
| 563 | * support a barrier bit, so if we need a consistent map these |
| 564 | * won't work. |
| 565 | */ |
| 566 | if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) { |
| 567 | /* |
| 568 | * We have two options for 40-bit mappings: 16GB "super" ATE's |
| 569 | * and 64MB "regular" ATE's. We'll try both if needed for a |
| 570 | * given mapping but which one we try first depends on the |
| 571 | * size. For requests >64MB, prefer to use a super page with |
| 572 | * regular as the fallback. Otherwise, try in the reverse order. |
| 573 | */ |
| 574 | |
| 575 | if (byte_count > MB(64)) { |
| 576 | mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, |
| 577 | port, ct_addr, byte_count); |
| 578 | if (!mapaddr) |
| 579 | mapaddr = |
| 580 | tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, |
| 581 | ct_addr, byte_count); |
| 582 | } else { |
| 583 | mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, |
| 584 | ct_addr, byte_count); |
| 585 | if (!mapaddr) |
| 586 | mapaddr = |
| 587 | tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, |
| 588 | port, ct_addr, byte_count); |
| 589 | } |
| 590 | } |
| 591 | |
| 592 | /* |
| 593 | * 32-bit direct is the next mode to try |
| 594 | */ |
| 595 | if (!mapaddr && dma_mask >= 0xffffffffUL) |
| 596 | mapaddr = tioce_dma_d32(pdev, ct_addr); |
| 597 | |
| 598 | /* |
| 599 | * Last resort, try 32-bit ATE-based map. |
| 600 | */ |
| 601 | if (!mapaddr) |
| 602 | mapaddr = |
| 603 | tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr, |
| 604 | byte_count); |
| 605 | |
| 606 | spin_unlock_irqrestore(&ce_kern->ce_lock, flags); |
| 607 | |
| 608 | dma_map_done: |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 609 | if (mapaddr && barrier) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 610 | mapaddr = tioce_dma_barrier(mapaddr, 1); |
| 611 | |
| 612 | return mapaddr; |
| 613 | } |
| 614 | |
| 615 | /** |
| 616 | * tioce_dma - standard pci dma map interface |
| 617 | * @pdev: pci device requesting the map |
| 618 | * @paddr: system physical address to map into pci space |
| 619 | * @byte_count: # bytes to map |
| 620 | * |
| 621 | * Simply call tioce_do_dma_map() to create a map with the barrier bit clear |
| 622 | * in the address. |
| 623 | */ |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 624 | static u64 |
| 625 | tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 626 | { |
| 627 | return tioce_do_dma_map(pdev, paddr, byte_count, 0); |
| 628 | } |
| 629 | |
| 630 | /** |
| 631 | * tioce_dma_consistent - consistent pci dma map interface |
| 632 | * @pdev: pci device requesting the map |
| 633 | * @paddr: system physical address to map into pci space |
| 634 | * @byte_count: # bytes to map |
| 635 | * |
| 636 | * Simply call tioce_do_dma_map() to create a map with the barrier bit set |
| 637 | * in the address. |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 638 | */ static u64 |
| 639 | tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count) |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 640 | { |
| 641 | return tioce_do_dma_map(pdev, paddr, byte_count, 1); |
| 642 | } |
| 643 | |
| 644 | /** |
| 645 | * tioce_error_intr_handler - SGI TIO CE error interrupt handler |
| 646 | * @irq: unused |
| 647 | * @arg: pointer to tioce_common struct for the given CE |
| 648 | * @pt: unused |
| 649 | * |
| 650 | * Handle a CE error interrupt. Simply a wrapper around a SAL call which |
| 651 | * defers processing to the SGI prom. |
| 652 | */ static irqreturn_t |
| 653 | tioce_error_intr_handler(int irq, void *arg, struct pt_regs *pt) |
| 654 | { |
| 655 | struct tioce_common *soft = arg; |
| 656 | struct ia64_sal_retval ret_stuff; |
| 657 | ret_stuff.status = 0; |
| 658 | ret_stuff.v0 = 0; |
| 659 | |
| 660 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_ERROR_INTERRUPT, |
| 661 | soft->ce_pcibus.bs_persist_segment, |
| 662 | soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0); |
| 663 | |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 664 | if (ret_stuff.v0) |
| 665 | panic("tioce_error_intr_handler: Fatal TIOCE error"); |
| 666 | |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 667 | return IRQ_HANDLED; |
| 668 | } |
| 669 | |
| 670 | /** |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 671 | * tioce_reserve_m32 - reserve M32 ate's for the indicated address range |
| 672 | * @tioce_kernel: TIOCE context to reserve ate's for |
| 673 | * @base: starting bus address to reserve |
| 674 | * @limit: last bus address to reserve |
| 675 | * |
| 676 | * If base/limit falls within the range of bus space mapped through the |
| 677 | * M32 space, reserve the resources corresponding to the range. |
| 678 | */ |
| 679 | static void |
| 680 | tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit) |
| 681 | { |
| 682 | int ate_index, last_ate, ps; |
| 683 | struct tioce *ce_mmr; |
| 684 | |
| 685 | if (!TIOCE_M32_ADDR(base)) |
| 686 | return; |
| 687 | |
| 688 | ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base; |
| 689 | ps = ce_kern->ce_ate3240_pagesize; |
| 690 | ate_index = ATE_PAGE(base, ps); |
| 691 | last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1; |
| 692 | |
| 693 | if (ate_index < 64) |
| 694 | ate_index = 64; |
| 695 | |
| 696 | while (ate_index <= last_ate) { |
| 697 | u64 ate; |
| 698 | |
| 699 | ate = ATE_MAKE(0xdeadbeef, ps); |
| 700 | ce_kern->ce_ate3240_shadow[ate_index] = ate; |
| 701 | tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index], |
| 702 | ate); |
| 703 | ate_index++; |
| 704 | } |
| 705 | } |
| 706 | |
| 707 | /** |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 708 | * tioce_kern_init - init kernel structures related to a given TIOCE |
| 709 | * @tioce_common: ptr to a cached tioce_common struct that originated in prom |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 710 | */ |
| 711 | static struct tioce_kernel * |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 712 | tioce_kern_init(struct tioce_common *tioce_common) |
| 713 | { |
| 714 | int i; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 715 | int ps; |
| 716 | int dev; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 717 | u32 tmp; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 718 | unsigned int seg, bus; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 719 | struct tioce *tioce_mmr; |
| 720 | struct tioce_kernel *tioce_kern; |
| 721 | |
Panagiotis Issaris | baf47fb | 2005-11-09 02:08:42 +0100 | [diff] [blame] | 722 | tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 723 | if (!tioce_kern) { |
| 724 | return NULL; |
| 725 | } |
| 726 | |
| 727 | tioce_kern->ce_common = tioce_common; |
| 728 | spin_lock_init(&tioce_kern->ce_lock); |
| 729 | INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list); |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 730 | tioce_common->ce_kernel_private = (u64) tioce_kern; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 731 | |
| 732 | /* |
| 733 | * Determine the secondary bus number of the port2 logical PPB. |
| 734 | * This is used to decide whether a given pci device resides on |
| 735 | * port1 or port2. Note: We don't have enough plumbing set up |
| 736 | * here to use pci_read_config_xxx() so use the raw_pci_ops vector. |
| 737 | */ |
| 738 | |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 739 | seg = tioce_common->ce_pcibus.bs_persist_segment; |
| 740 | bus = tioce_common->ce_pcibus.bs_persist_busnum; |
| 741 | |
| 742 | raw_pci_ops->read(seg, bus, PCI_DEVFN(2, 0), PCI_SECONDARY_BUS, 1,&tmp); |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 743 | tioce_kern->ce_port1_secondary = (u8) tmp; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 744 | |
| 745 | /* |
| 746 | * Set PMU pagesize to the largest size available, and zero out |
| 747 | * the ate's. |
| 748 | */ |
| 749 | |
| 750 | tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 751 | tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map, |
| 752 | CE_URE_PAGESIZE_MASK); |
| 753 | tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map, |
| 754 | CE_URE_256K_PAGESIZE); |
| 755 | ps = tioce_kern->ce_ate3240_pagesize = KB(256); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 756 | |
| 757 | for (i = 0; i < TIOCE_NUM_M40_ATES; i++) { |
| 758 | tioce_kern->ce_ate40_shadow[i] = 0; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 759 | tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate40[i], 0); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | for (i = 0; i < TIOCE_NUM_M3240_ATES; i++) { |
| 763 | tioce_kern->ce_ate3240_shadow[i] = 0; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 764 | tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate3240[i], 0); |
| 765 | } |
| 766 | |
| 767 | /* |
| 768 | * Reserve ATE's corresponding to reserved address ranges. These |
| 769 | * include: |
| 770 | * |
| 771 | * Memory space covered by each PPB mem base/limit register |
| 772 | * Memory space covered by each PPB prefetch base/limit register |
| 773 | * |
| 774 | * These bus ranges are for pio (downstream) traffic only, and so |
| 775 | * cannot be used for DMA. |
| 776 | */ |
| 777 | |
| 778 | for (dev = 1; dev <= 2; dev++) { |
| 779 | u64 base, limit; |
| 780 | |
| 781 | /* mem base/limit */ |
| 782 | |
| 783 | raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0), |
| 784 | PCI_MEMORY_BASE, 2, &tmp); |
| 785 | base = (u64)tmp << 16; |
| 786 | |
| 787 | raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0), |
| 788 | PCI_MEMORY_LIMIT, 2, &tmp); |
| 789 | limit = (u64)tmp << 16; |
| 790 | limit |= 0xfffffUL; |
| 791 | |
| 792 | if (base < limit) |
| 793 | tioce_reserve_m32(tioce_kern, base, limit); |
| 794 | |
| 795 | /* |
| 796 | * prefetch mem base/limit. The tioce ppb's have 64-bit |
| 797 | * decoders, so read the upper portions w/o checking the |
| 798 | * attributes. |
| 799 | */ |
| 800 | |
| 801 | raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0), |
| 802 | PCI_PREF_MEMORY_BASE, 2, &tmp); |
| 803 | base = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16; |
| 804 | |
| 805 | raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0), |
| 806 | PCI_PREF_BASE_UPPER32, 4, &tmp); |
| 807 | base |= (u64)tmp << 32; |
| 808 | |
| 809 | raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0), |
| 810 | PCI_PREF_MEMORY_LIMIT, 2, &tmp); |
| 811 | |
| 812 | limit = ((u64)tmp & PCI_PREF_RANGE_MASK) << 16; |
| 813 | limit |= 0xfffffUL; |
| 814 | |
| 815 | raw_pci_ops->read(seg, bus, PCI_DEVFN(dev, 0), |
| 816 | PCI_PREF_LIMIT_UPPER32, 4, &tmp); |
| 817 | limit |= (u64)tmp << 32; |
| 818 | |
| 819 | if ((base < limit) && TIOCE_M32_ADDR(base)) |
| 820 | tioce_reserve_m32(tioce_kern, base, limit); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 821 | } |
| 822 | |
| 823 | return tioce_kern; |
| 824 | } |
| 825 | |
| 826 | /** |
| 827 | * tioce_force_interrupt - implement altix force_interrupt() backend for CE |
| 828 | * @sn_irq_info: sn asic irq that we need an interrupt generated for |
| 829 | * |
| 830 | * Given an sn_irq_info struct, set the proper bit in ce_adm_force_int to |
| 831 | * force a secondary interrupt to be generated. This is to work around an |
| 832 | * asic issue where there is a small window of opportunity for a legacy device |
| 833 | * interrupt to be lost. |
| 834 | */ |
| 835 | static void |
| 836 | tioce_force_interrupt(struct sn_irq_info *sn_irq_info) |
| 837 | { |
| 838 | struct pcidev_info *pcidev_info; |
| 839 | struct tioce_common *ce_common; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 840 | struct tioce_kernel *ce_kern; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 841 | struct tioce *ce_mmr; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 842 | u64 force_int_val; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 843 | |
| 844 | if (!sn_irq_info->irq_bridge) |
| 845 | return; |
| 846 | |
| 847 | if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE) |
| 848 | return; |
| 849 | |
| 850 | pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; |
| 851 | if (!pcidev_info) |
| 852 | return; |
| 853 | |
| 854 | ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; |
| 855 | ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 856 | ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private; |
| 857 | |
| 858 | /* |
| 859 | * TIOCE Rev A workaround (PV 945826), force an interrupt by writing |
| 860 | * the TIO_INTx register directly (1/26/2006) |
| 861 | */ |
| 862 | if (ce_common->ce_rev == TIOCE_REV_A) { |
| 863 | u64 int_bit_mask = (1ULL << sn_irq_info->irq_int_bit); |
| 864 | u64 status; |
| 865 | |
| 866 | tioce_mmr_load(ce_kern, &ce_mmr->ce_adm_int_status, &status); |
| 867 | if (status & int_bit_mask) { |
| 868 | u64 force_irq = (1 << 8) | sn_irq_info->irq_irq; |
| 869 | u64 ctalk = sn_irq_info->irq_xtalkaddr; |
| 870 | u64 nasid, offset; |
| 871 | |
| 872 | nasid = (ctalk & CTALK_NASID_MASK) >> CTALK_NASID_SHFT; |
| 873 | offset = (ctalk & CTALK_NODE_OFFSET); |
| 874 | HUB_S(TIO_IOSPACE_ADDR(nasid, offset), force_irq); |
| 875 | } |
| 876 | |
| 877 | return; |
| 878 | } |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 879 | |
| 880 | /* |
| 881 | * irq_int_bit is originally set up by prom, and holds the interrupt |
| 882 | * bit shift (not mask) as defined by the bit definitions in the |
| 883 | * ce_adm_int mmr. These shifts are not the same for the |
| 884 | * ce_adm_force_int register, so do an explicit mapping here to make |
| 885 | * things clearer. |
| 886 | */ |
| 887 | |
| 888 | switch (sn_irq_info->irq_int_bit) { |
| 889 | case CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT: |
| 890 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT; |
| 891 | break; |
| 892 | case CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT: |
| 893 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT; |
| 894 | break; |
| 895 | case CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT: |
| 896 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT; |
| 897 | break; |
| 898 | case CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT: |
| 899 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT; |
| 900 | break; |
| 901 | case CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT: |
| 902 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT; |
| 903 | break; |
| 904 | case CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT: |
| 905 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT; |
| 906 | break; |
| 907 | case CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT: |
| 908 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT; |
| 909 | break; |
| 910 | case CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT: |
| 911 | force_int_val = 1UL << CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT; |
| 912 | break; |
| 913 | default: |
| 914 | return; |
| 915 | } |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 916 | tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_force_int, force_int_val); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 917 | } |
| 918 | |
| 919 | /** |
Mark Maule | 8409668 | 2005-08-25 11:45:00 -0700 | [diff] [blame] | 920 | * tioce_target_interrupt - implement set_irq_affinity for tioce resident |
| 921 | * functions. Note: only applies to line interrupts, not MSI's. |
| 922 | * |
| 923 | * @sn_irq_info: SN IRQ context |
| 924 | * |
| 925 | * Given an sn_irq_info, set the associated CE device's interrupt destination |
| 926 | * register. Since the interrupt destination registers are on a per-ce-slot |
| 927 | * basis, this will retarget line interrupts for all functions downstream of |
| 928 | * the slot. |
| 929 | */ |
| 930 | static void |
| 931 | tioce_target_interrupt(struct sn_irq_info *sn_irq_info) |
| 932 | { |
| 933 | struct pcidev_info *pcidev_info; |
| 934 | struct tioce_common *ce_common; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 935 | struct tioce_kernel *ce_kern; |
Mark Maule | 8409668 | 2005-08-25 11:45:00 -0700 | [diff] [blame] | 936 | struct tioce *ce_mmr; |
| 937 | int bit; |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 938 | u64 vector; |
Mark Maule | 8409668 | 2005-08-25 11:45:00 -0700 | [diff] [blame] | 939 | |
| 940 | pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; |
| 941 | if (!pcidev_info) |
| 942 | return; |
| 943 | |
| 944 | ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; |
| 945 | ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 946 | ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private; |
Mark Maule | 8409668 | 2005-08-25 11:45:00 -0700 | [diff] [blame] | 947 | |
| 948 | bit = sn_irq_info->irq_int_bit; |
| 949 | |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 950 | tioce_mmr_seti(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit)); |
Prarit Bhargava | 53493dc | 2006-01-16 19:54:40 -0800 | [diff] [blame] | 951 | vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT; |
Mark Maule | 5fbcf9a | 2005-09-06 13:03:51 -0500 | [diff] [blame] | 952 | vector |= sn_irq_info->irq_xtalkaddr; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 953 | tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_int_dest[bit], vector); |
| 954 | tioce_mmr_clri(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit)); |
Mark Maule | 8409668 | 2005-08-25 11:45:00 -0700 | [diff] [blame] | 955 | |
| 956 | tioce_force_interrupt(sn_irq_info); |
| 957 | } |
| 958 | |
| 959 | /** |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 960 | * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus |
| 961 | * @prom_bussoft: Common prom/kernel struct representing the bus |
| 962 | * |
| 963 | * Replicates the tioce_common pointed to by @prom_bussoft in kernel |
| 964 | * space. Allocates and initializes a kernel-only area for a given CE, |
| 965 | * and sets up an irq for handling CE error interrupts. |
| 966 | * |
| 967 | * On successful setup, returns the kernel version of tioce_common back to |
| 968 | * the caller. |
| 969 | */ |
| 970 | static void * |
| 971 | tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller) |
| 972 | { |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 973 | int my_nasid; |
| 974 | cnodeid_t my_cnode, mem_cnode; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 975 | struct tioce_common *tioce_common; |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 976 | struct tioce_kernel *tioce_kern; |
| 977 | struct tioce *tioce_mmr; |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 978 | |
| 979 | /* |
| 980 | * Allocate kernel bus soft and copy from prom. |
| 981 | */ |
| 982 | |
Panagiotis Issaris | baf47fb | 2005-11-09 02:08:42 +0100 | [diff] [blame] | 983 | tioce_common = kzalloc(sizeof(struct tioce_common), GFP_KERNEL); |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 984 | if (!tioce_common) |
| 985 | return NULL; |
| 986 | |
| 987 | memcpy(tioce_common, prom_bussoft, sizeof(struct tioce_common)); |
| 988 | tioce_common->ce_pcibus.bs_base |= __IA64_UNCACHED_OFFSET; |
| 989 | |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 990 | tioce_kern = tioce_kern_init(tioce_common); |
| 991 | if (tioce_kern == NULL) { |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 992 | kfree(tioce_common); |
| 993 | return NULL; |
| 994 | } |
| 995 | |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 996 | /* |
| 997 | * Clear out any transient errors before registering the error |
| 998 | * interrupt handler. |
| 999 | */ |
| 1000 | |
| 1001 | tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base; |
| 1002 | tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL); |
| 1003 | tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias, |
| 1004 | ~0ULL); |
| 1005 | tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_dre_comp_err_addr, ~0ULL); |
| 1006 | |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 1007 | if (request_irq(SGI_PCIASIC_ERROR, |
| 1008 | tioce_error_intr_handler, |
| 1009 | SA_SHIRQ, "TIOCE error", (void *)tioce_common)) |
| 1010 | printk(KERN_WARNING |
| 1011 | "%s: Unable to get irq %d. " |
| 1012 | "Error interrupts won't be routed for " |
| 1013 | "TIOCE bus %04x:%02x\n", |
| 1014 | __FUNCTION__, SGI_PCIASIC_ERROR, |
| 1015 | tioce_common->ce_pcibus.bs_persist_segment, |
| 1016 | tioce_common->ce_pcibus.bs_persist_busnum); |
| 1017 | |
Mark Maule | 13938ca | 2006-01-26 14:46:39 -0600 | [diff] [blame^] | 1018 | /* |
| 1019 | * identify closest nasid for memory allocations |
| 1020 | */ |
| 1021 | |
| 1022 | my_nasid = NASID_GET(tioce_common->ce_pcibus.bs_base); |
| 1023 | my_cnode = nasid_to_cnodeid(my_nasid); |
| 1024 | |
| 1025 | if (sn_hwperf_get_nearest_node(my_cnode, &mem_cnode, NULL) < 0) { |
| 1026 | printk(KERN_WARNING "tioce_bus_fixup: failed to find " |
| 1027 | "closest node with MEM to TIO node %d\n", my_cnode); |
| 1028 | mem_cnode = (cnodeid_t)-1; /* use any node */ |
| 1029 | } |
| 1030 | |
| 1031 | controller->node = mem_cnode; |
| 1032 | |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 1033 | return tioce_common; |
| 1034 | } |
| 1035 | |
| 1036 | static struct sn_pcibus_provider tioce_pci_interfaces = { |
| 1037 | .dma_map = tioce_dma, |
| 1038 | .dma_map_consistent = tioce_dma_consistent, |
| 1039 | .dma_unmap = tioce_dma_unmap, |
| 1040 | .bus_fixup = tioce_bus_fixup, |
Mark Maule | 8409668 | 2005-08-25 11:45:00 -0700 | [diff] [blame] | 1041 | .force_interrupt = tioce_force_interrupt, |
| 1042 | .target_interrupt = tioce_target_interrupt |
Mark Maule | c9221da | 2005-08-03 14:07:00 -0700 | [diff] [blame] | 1043 | }; |
| 1044 | |
| 1045 | /** |
| 1046 | * tioce_init_provider - init SN PCI provider ops for TIO CE |
| 1047 | */ |
| 1048 | int |
| 1049 | tioce_init_provider(void) |
| 1050 | { |
| 1051 | sn_pci_provider[PCIIO_ASIC_TYPE_TIOCE] = &tioce_pci_interfaces; |
| 1052 | return 0; |
| 1053 | } |