Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, Linaro Limited |
| 3 | * |
| 4 | * This software is licensed under the terms of the GNU General Public |
| 5 | * License version 2, as published by the Free Software Foundation, and |
| 6 | * may be copied, distributed, and modified under those terms. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | #ifndef __LINUX_ARM_SMCCC_H |
| 15 | #define __LINUX_ARM_SMCCC_H |
| 16 | |
Mark Rutland | 5d667c1 | 2018-04-12 12:11:35 +0100 | [diff] [blame] | 17 | #include <uapi/linux/const.h> |
| 18 | |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 19 | /* |
| 20 | * This file provides common defines for ARM SMC Calling Convention as |
| 21 | * specified in |
| 22 | * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html |
| 23 | */ |
| 24 | |
Mark Rutland | 5d667c1 | 2018-04-12 12:11:35 +0100 | [diff] [blame] | 25 | #define ARM_SMCCC_STD_CALL _AC(0,U) |
| 26 | #define ARM_SMCCC_FAST_CALL _AC(1,U) |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 27 | #define ARM_SMCCC_TYPE_SHIFT 31 |
| 28 | |
| 29 | #define ARM_SMCCC_SMC_32 0 |
| 30 | #define ARM_SMCCC_SMC_64 1 |
| 31 | #define ARM_SMCCC_CALL_CONV_SHIFT 30 |
| 32 | |
| 33 | #define ARM_SMCCC_OWNER_MASK 0x3F |
| 34 | #define ARM_SMCCC_OWNER_SHIFT 24 |
| 35 | |
| 36 | #define ARM_SMCCC_FUNC_MASK 0xFFFF |
| 37 | |
| 38 | #define ARM_SMCCC_IS_FAST_CALL(smc_val) \ |
| 39 | ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) |
| 40 | #define ARM_SMCCC_IS_64(smc_val) \ |
| 41 | ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) |
| 42 | #define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) |
| 43 | #define ARM_SMCCC_OWNER_NUM(smc_val) \ |
| 44 | (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) |
| 45 | |
| 46 | #define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ |
| 47 | (((type) << ARM_SMCCC_TYPE_SHIFT) | \ |
| 48 | ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ |
| 49 | (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ |
| 50 | ((func_num) & ARM_SMCCC_FUNC_MASK)) |
| 51 | |
| 52 | #define ARM_SMCCC_OWNER_ARCH 0 |
| 53 | #define ARM_SMCCC_OWNER_CPU 1 |
| 54 | #define ARM_SMCCC_OWNER_SIP 2 |
| 55 | #define ARM_SMCCC_OWNER_OEM 3 |
| 56 | #define ARM_SMCCC_OWNER_STANDARD 4 |
| 57 | #define ARM_SMCCC_OWNER_TRUSTED_APP 48 |
| 58 | #define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 |
| 59 | #define ARM_SMCCC_OWNER_TRUSTED_OS 50 |
| 60 | #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 |
| 61 | |
Andy Gross | bec9918 | 2017-04-04 19:32:32 +0000 | [diff] [blame] | 62 | #define ARM_SMCCC_QUIRK_NONE 0 |
| 63 | #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ |
| 64 | |
Mark Rutland | 6681f3c | 2018-04-12 12:11:28 +0100 | [diff] [blame] | 65 | #define ARM_SMCCC_VERSION_1_0 0x10000 |
| 66 | #define ARM_SMCCC_VERSION_1_1 0x10001 |
| 67 | |
| 68 | #define ARM_SMCCC_VERSION_FUNC_ID \ |
| 69 | ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ |
| 70 | ARM_SMCCC_SMC_32, \ |
| 71 | 0, 0) |
| 72 | |
| 73 | #define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ |
| 74 | ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ |
| 75 | ARM_SMCCC_SMC_32, \ |
| 76 | 0, 1) |
| 77 | |
Mark Rutland | c9ae3d5 | 2018-04-12 12:11:31 +0100 | [diff] [blame] | 78 | #define ARM_SMCCC_ARCH_WORKAROUND_1 \ |
| 79 | ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ |
| 80 | ARM_SMCCC_SMC_32, \ |
| 81 | 0, 0x8000) |
| 82 | |
Andy Gross | bec9918 | 2017-04-04 19:32:32 +0000 | [diff] [blame] | 83 | #ifndef __ASSEMBLY__ |
| 84 | |
| 85 | #include <linux/linkage.h> |
| 86 | #include <linux/types.h> |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 87 | /** |
| 88 | * struct arm_smccc_res - Result from SMC/HVC call |
| 89 | * @a0-a3 result values from registers 0 to 3 |
| 90 | */ |
| 91 | struct arm_smccc_res { |
| 92 | unsigned long a0; |
| 93 | unsigned long a1; |
| 94 | unsigned long a2; |
| 95 | unsigned long a3; |
| 96 | }; |
| 97 | |
| 98 | /** |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 99 | * struct arm_smccc_quirk - Contains quirk information |
| 100 | * @id: quirk identification |
| 101 | * @state: quirk specific information |
| 102 | * @a6: Qualcomm quirk entry for returning post-smc call contents of a6 |
| 103 | */ |
| 104 | struct arm_smccc_quirk { |
| 105 | int id; |
| 106 | union { |
| 107 | unsigned long a6; |
| 108 | } state; |
| 109 | }; |
| 110 | |
| 111 | /** |
| 112 | * __arm_smccc_smc() - make SMC calls |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 113 | * @a0-a7: arguments passed in registers 0 to 7 |
| 114 | * @res: result values from registers 0 to 3 |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 115 | * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 116 | * |
| 117 | * This function is used to make SMC calls following SMC Calling Convention. |
| 118 | * The content of the supplied param are copied to registers 0 to 7 prior |
| 119 | * to the SMC instruction. The return values are updated with the content |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 120 | * from register 0 to 3 on return from the SMC instruction. An optional |
| 121 | * quirk structure provides vendor specific behavior. |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 122 | */ |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 123 | asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1, |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 124 | unsigned long a2, unsigned long a3, unsigned long a4, |
| 125 | unsigned long a5, unsigned long a6, unsigned long a7, |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 126 | struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 127 | |
| 128 | /** |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 129 | * __arm_smccc_hvc() - make HVC calls |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 130 | * @a0-a7: arguments passed in registers 0 to 7 |
| 131 | * @res: result values from registers 0 to 3 |
Will Deacon | 35b366d | 2017-04-04 19:32:32 +0000 | [diff] [blame] | 132 | * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 133 | * |
| 134 | * This function is used to make HVC calls following SMC Calling |
| 135 | * Convention. The content of the supplied param are copied to registers 0 |
| 136 | * to 7 prior to the HVC instruction. The return values are updated with |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 137 | * the content from register 0 to 3 on return from the HVC instruction. An |
| 138 | * optional quirk structure provides vendor specific behavior. |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 139 | */ |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 140 | asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 141 | unsigned long a2, unsigned long a3, unsigned long a4, |
| 142 | unsigned long a5, unsigned long a6, unsigned long a7, |
Andy Gross | 007f0a2 | 2017-04-04 19:32:31 +0000 | [diff] [blame] | 143 | struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); |
| 144 | |
| 145 | #define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) |
| 146 | |
| 147 | #define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) |
| 148 | |
| 149 | #define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL) |
| 150 | |
| 151 | #define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__) |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 152 | |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 153 | /* SMCCC v1.1 implementation madness follows */ |
| 154 | #ifdef CONFIG_ARM64 |
| 155 | |
| 156 | #define SMCCC_SMC_INST "smc #0" |
| 157 | #define SMCCC_HVC_INST "hvc #0" |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 158 | #define SMCCC_REG(n) asm("x" # n) |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 159 | |
| 160 | #elif defined(CONFIG_ARM) |
| 161 | #include <asm/opcodes-sec.h> |
| 162 | #include <asm/opcodes-virt.h> |
| 163 | |
| 164 | #define SMCCC_SMC_INST __SMC(0) |
| 165 | #define SMCCC_HVC_INST __HVC(0) |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 166 | #define SMCCC_REG(n) asm("r" # n) |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 167 | |
| 168 | #endif |
| 169 | |
| 170 | #define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x |
| 171 | |
| 172 | #define __count_args(...) \ |
| 173 | ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) |
| 174 | |
| 175 | #define __constraint_write_0 \ |
| 176 | "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) |
| 177 | #define __constraint_write_1 \ |
| 178 | "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) |
| 179 | #define __constraint_write_2 \ |
| 180 | "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) |
| 181 | #define __constraint_write_3 \ |
| 182 | "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) |
| 183 | #define __constraint_write_4 __constraint_write_3 |
| 184 | #define __constraint_write_5 __constraint_write_4 |
| 185 | #define __constraint_write_6 __constraint_write_5 |
| 186 | #define __constraint_write_7 __constraint_write_6 |
| 187 | |
| 188 | #define __constraint_read_0 |
| 189 | #define __constraint_read_1 |
| 190 | #define __constraint_read_2 |
| 191 | #define __constraint_read_3 |
| 192 | #define __constraint_read_4 "r" (r4) |
| 193 | #define __constraint_read_5 __constraint_read_4, "r" (r5) |
| 194 | #define __constraint_read_6 __constraint_read_5, "r" (r6) |
| 195 | #define __constraint_read_7 __constraint_read_6, "r" (r7) |
| 196 | |
| 197 | #define __declare_arg_0(a0, res) \ |
| 198 | struct arm_smccc_res *___res = res; \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 199 | register u32 r0 SMCCC_REG(0) = a0; \ |
| 200 | register unsigned long r1 SMCCC_REG(1); \ |
| 201 | register unsigned long r2 SMCCC_REG(2); \ |
| 202 | register unsigned long r3 SMCCC_REG(3) |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 203 | |
| 204 | #define __declare_arg_1(a0, a1, res) \ |
| 205 | struct arm_smccc_res *___res = res; \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 206 | register u32 r0 SMCCC_REG(0) = a0; \ |
| 207 | register typeof(a1) r1 SMCCC_REG(1) = a1; \ |
| 208 | register unsigned long r2 SMCCC_REG(2); \ |
| 209 | register unsigned long r3 SMCCC_REG(3) |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 210 | |
| 211 | #define __declare_arg_2(a0, a1, a2, res) \ |
| 212 | struct arm_smccc_res *___res = res; \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 213 | register u32 r0 SMCCC_REG(0) = a0; \ |
| 214 | register typeof(a1) r1 SMCCC_REG(1) = a1; \ |
| 215 | register typeof(a2) r2 SMCCC_REG(2) = a2; \ |
| 216 | register unsigned long r3 SMCCC_REG(3) |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 217 | |
| 218 | #define __declare_arg_3(a0, a1, a2, a3, res) \ |
| 219 | struct arm_smccc_res *___res = res; \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 220 | register u32 r0 SMCCC_REG(0) = a0; \ |
| 221 | register typeof(a1) r1 SMCCC_REG(1) = a1; \ |
| 222 | register typeof(a2) r2 SMCCC_REG(2) = a2; \ |
| 223 | register typeof(a3) r3 SMCCC_REG(3) = a3 |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 224 | |
| 225 | #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ |
| 226 | __declare_arg_3(a0, a1, a2, a3, res); \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 227 | register typeof(a4) r4 SMCCC_REG(4) = a4 |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 228 | |
| 229 | #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ |
| 230 | __declare_arg_4(a0, a1, a2, a3, a4, res); \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 231 | register typeof(a5) r5 SMCCC_REG(5) = a5 |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 232 | |
| 233 | #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ |
| 234 | __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 235 | register typeof(a6) r6 SMCCC_REG(6) = a6 |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 236 | |
| 237 | #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ |
| 238 | __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ |
Greg Hackmann | 13cc540 | 2018-03-02 13:22:46 -0800 | [diff] [blame^] | 239 | register typeof(a7) r7 SMCCC_REG(7) = a7 |
Mark Rutland | eb90973 | 2018-04-12 12:11:36 +0100 | [diff] [blame] | 240 | |
| 241 | #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) |
| 242 | #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) |
| 243 | |
| 244 | #define ___constraints(count) \ |
| 245 | : __constraint_write_ ## count \ |
| 246 | : __constraint_read_ ## count \ |
| 247 | : "memory" |
| 248 | #define __constraints(count) ___constraints(count) |
| 249 | |
| 250 | /* |
| 251 | * We have an output list that is not necessarily used, and GCC feels |
| 252 | * entitled to optimise the whole sequence away. "volatile" is what |
| 253 | * makes it stick. |
| 254 | */ |
| 255 | #define __arm_smccc_1_1(inst, ...) \ |
| 256 | do { \ |
| 257 | __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ |
| 258 | asm volatile(inst "\n" \ |
| 259 | __constraints(__count_args(__VA_ARGS__))); \ |
| 260 | if (___res) \ |
| 261 | *___res = (typeof(*___res)){r0, r1, r2, r3}; \ |
| 262 | } while (0) |
| 263 | |
| 264 | /* |
| 265 | * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call |
| 266 | * |
| 267 | * This is a variadic macro taking one to eight source arguments, and |
| 268 | * an optional return structure. |
| 269 | * |
| 270 | * @a0-a7: arguments passed in registers 0 to 7 |
| 271 | * @res: result values from registers 0 to 3 |
| 272 | * |
| 273 | * This macro is used to make SMC calls following SMC Calling Convention v1.1. |
| 274 | * The content of the supplied param are copied to registers 0 to 7 prior |
| 275 | * to the SMC instruction. The return values are updated with the content |
| 276 | * from register 0 to 3 on return from the SMC instruction if not NULL. |
| 277 | */ |
| 278 | #define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) |
| 279 | |
| 280 | /* |
| 281 | * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call |
| 282 | * |
| 283 | * This is a variadic macro taking one to eight source arguments, and |
| 284 | * an optional return structure. |
| 285 | * |
| 286 | * @a0-a7: arguments passed in registers 0 to 7 |
| 287 | * @res: result values from registers 0 to 3 |
| 288 | * |
| 289 | * This macro is used to make HVC calls following SMC Calling Convention v1.1. |
| 290 | * The content of the supplied param are copied to registers 0 to 7 prior |
| 291 | * to the HVC instruction. The return values are updated with the content |
| 292 | * from register 0 to 3 on return from the HVC instruction if not NULL. |
| 293 | */ |
| 294 | #define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) |
| 295 | |
Andy Gross | bec9918 | 2017-04-04 19:32:32 +0000 | [diff] [blame] | 296 | #endif /*__ASSEMBLY__*/ |
Jens Wiklander | 98dd64f | 2016-01-04 15:37:32 +0100 | [diff] [blame] | 297 | #endif /*__LINUX_ARM_SMCCC_H*/ |