blob: 1ff6a37e893c423da523a945e0cf7c5d8f837152 [file] [log] [blame]
Dan Williams2492c842007-01-02 13:52:31 -07001/*
2 * platform device definitions for the iop3xx dma/xor engines
3 * Copyright © 2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19#include <linux/platform_device.h>
20#include <asm/hardware/iop3xx.h>
21#include <linux/dma-mapping.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010022#include <mach/adma.h>
Dan Williams2492c842007-01-02 13:52:31 -070023#include <asm/hardware/iop_adma.h>
24
25#ifdef CONFIG_ARCH_IOP32X
26#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
27#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
28#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
29
30#define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
31#define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
32#define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
33
34#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
35#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
36#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
37#endif
38#ifdef CONFIG_ARCH_IOP33X
39#define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
40#define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
41#define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
42
43#define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
44#define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
45#define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
46
47#define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
48#define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
49#define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
50#endif
51/* AAU and DMA Channels */
52static struct resource iop3xx_dma_0_resources[] = {
53 [0] = {
54 .start = IOP3XX_DMA_PHYS_BASE(0),
55 .end = IOP3XX_DMA_UPPER_PA(0),
56 .flags = IORESOURCE_MEM,
57 },
58 [1] = {
59 .start = IRQ_DMA0_EOT,
60 .end = IRQ_DMA0_EOT,
61 .flags = IORESOURCE_IRQ
62 },
63 [2] = {
64 .start = IRQ_DMA0_EOC,
65 .end = IRQ_DMA0_EOC,
66 .flags = IORESOURCE_IRQ
67 },
68 [3] = {
69 .start = IRQ_DMA0_ERR,
70 .end = IRQ_DMA0_ERR,
71 .flags = IORESOURCE_IRQ
72 }
73};
74
75static struct resource iop3xx_dma_1_resources[] = {
76 [0] = {
77 .start = IOP3XX_DMA_PHYS_BASE(1),
78 .end = IOP3XX_DMA_UPPER_PA(1),
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = {
82 .start = IRQ_DMA1_EOT,
83 .end = IRQ_DMA1_EOT,
84 .flags = IORESOURCE_IRQ
85 },
86 [2] = {
87 .start = IRQ_DMA1_EOC,
88 .end = IRQ_DMA1_EOC,
89 .flags = IORESOURCE_IRQ
90 },
91 [3] = {
92 .start = IRQ_DMA1_ERR,
93 .end = IRQ_DMA1_ERR,
94 .flags = IORESOURCE_IRQ
95 }
96};
97
98
99static struct resource iop3xx_aau_resources[] = {
100 [0] = {
101 .start = IOP3XX_AAU_PHYS_BASE,
102 .end = IOP3XX_AAU_UPPER_PA,
103 .flags = IORESOURCE_MEM,
104 },
105 [1] = {
106 .start = IRQ_AA_EOT,
107 .end = IRQ_AA_EOT,
108 .flags = IORESOURCE_IRQ
109 },
110 [2] = {
111 .start = IRQ_AA_EOC,
112 .end = IRQ_AA_EOC,
113 .flags = IORESOURCE_IRQ
114 },
115 [3] = {
116 .start = IRQ_AA_ERR,
117 .end = IRQ_AA_ERR,
118 .flags = IORESOURCE_IRQ
119 }
120};
121
Yang Hongyang284901a2009-04-06 19:01:15 -0700122static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
Dan Williams2492c842007-01-02 13:52:31 -0700123
124static struct iop_adma_platform_data iop3xx_dma_0_data = {
125 .hw_id = DMA0_ID,
126 .pool_size = PAGE_SIZE,
127};
128
129static struct iop_adma_platform_data iop3xx_dma_1_data = {
130 .hw_id = DMA1_ID,
131 .pool_size = PAGE_SIZE,
132};
133
134static struct iop_adma_platform_data iop3xx_aau_data = {
135 .hw_id = AAU_ID,
136 .pool_size = 3 * PAGE_SIZE,
137};
138
139struct platform_device iop3xx_dma_0_channel = {
140 .name = "iop-adma",
141 .id = 0,
142 .num_resources = 4,
143 .resource = iop3xx_dma_0_resources,
144 .dev = {
145 .dma_mask = &iop3xx_adma_dmamask,
Yang Hongyang6a355282009-04-06 19:01:13 -0700146 .coherent_dma_mask = DMA_BIT_MASK(64),
Dan Williams2492c842007-01-02 13:52:31 -0700147 .platform_data = (void *) &iop3xx_dma_0_data,
148 },
149};
150
151struct platform_device iop3xx_dma_1_channel = {
152 .name = "iop-adma",
153 .id = 1,
154 .num_resources = 4,
155 .resource = iop3xx_dma_1_resources,
156 .dev = {
157 .dma_mask = &iop3xx_adma_dmamask,
Yang Hongyang6a355282009-04-06 19:01:13 -0700158 .coherent_dma_mask = DMA_BIT_MASK(64),
Dan Williams2492c842007-01-02 13:52:31 -0700159 .platform_data = (void *) &iop3xx_dma_1_data,
160 },
161};
162
163struct platform_device iop3xx_aau_channel = {
164 .name = "iop-adma",
165 .id = 2,
166 .num_resources = 4,
167 .resource = iop3xx_aau_resources,
168 .dev = {
169 .dma_mask = &iop3xx_adma_dmamask,
Yang Hongyang6a355282009-04-06 19:01:13 -0700170 .coherent_dma_mask = DMA_BIT_MASK(64),
Dan Williams2492c842007-01-02 13:52:31 -0700171 .platform_data = (void *) &iop3xx_aau_data,
172 },
173};
174
175static int __init iop3xx_adma_cap_init(void)
176{
177 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
178 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
179 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
180 #else
181 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
Dan Williams2492c842007-01-02 13:52:31 -0700182 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
183 #endif
184
185 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
186 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
187 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
188 #else
189 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
Dan Williams2492c842007-01-02 13:52:31 -0700190 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
191 #endif
192
193 #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
194 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
195 dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
196 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
197 #else
198 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
Dan Williams099f53c2009-04-08 14:28:37 -0700199 dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
Dan Williams2492c842007-01-02 13:52:31 -0700200 dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
201 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
202 #endif
203
204 return 0;
205}
206
207arch_initcall(iop3xx_adma_cap_init);