Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is dual-licensed: you can use it either under the terms |
| 3 | * of the GPL or the X11 license, at your option. Note that this dual |
| 4 | * licensing only applies to this file, and not this project as a |
| 5 | * whole. |
| 6 | * |
| 7 | * a) This file is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of the |
| 10 | * License, or (at your option) any later version. |
| 11 | * |
| 12 | * This file is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * Or, alternatively, |
| 18 | * |
| 19 | * b) Permission is hereby granted, free of charge, to any person |
| 20 | * obtaining a copy of this software and associated documentation |
| 21 | * files (the "Software"), to deal in the Software without |
| 22 | * restriction, including without limitation the rights to use, |
| 23 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 24 | * sell copies of the Software, and to permit persons to whom the |
| 25 | * Software is furnished to do so, subject to the following |
| 26 | * conditions: |
| 27 | * |
| 28 | * The above copyright notice and this permission notice shall be |
| 29 | * included in all copies or substantial portions of the Software. |
| 30 | * |
| 31 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 32 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 33 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 34 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 35 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 36 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 37 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 38 | * OTHER DEALINGS IN THE SOFTWARE. |
| 39 | */ |
| 40 | |
| 41 | #include <dt-bindings/gpio/gpio.h> |
| 42 | #include <dt-bindings/interrupt-controller/irq.h> |
| 43 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 44 | #include <dt-bindings/pinctrl/rockchip.h> |
| 45 | #include <dt-bindings/clock/rk3036-cru.h> |
Andy Yan | b60ab70 | 2016-07-06 21:28:34 +0800 | [diff] [blame] | 46 | #include <dt-bindings/soc/rockchip,boot-mode.h> |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 47 | #include "skeleton.dtsi" |
| 48 | |
| 49 | / { |
| 50 | compatible = "rockchip,rk3036"; |
| 51 | |
| 52 | interrupt-parent = <&gic>; |
| 53 | |
| 54 | aliases { |
| 55 | i2c0 = &i2c0; |
| 56 | i2c1 = &i2c1; |
| 57 | i2c2 = &i2c2; |
| 58 | mshc0 = &emmc; |
Caesar Wang | 187d796 | 2015-12-17 22:21:49 +0800 | [diff] [blame] | 59 | mshc1 = &sdmmc; |
| 60 | mshc2 = &sdio; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 61 | serial0 = &uart0; |
| 62 | serial1 = &uart1; |
| 63 | serial2 = &uart2; |
Caesar Wang | f629fcf | 2016-02-02 11:40:53 +0800 | [diff] [blame] | 64 | spi = &spi; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 65 | }; |
| 66 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 67 | cpus { |
| 68 | #address-cells = <1>; |
| 69 | #size-cells = <0>; |
| 70 | enable-method = "rockchip,rk3036-smp"; |
| 71 | |
| 72 | cpu0: cpu@f00 { |
| 73 | device_type = "cpu"; |
| 74 | compatible = "arm,cortex-a7"; |
| 75 | reg = <0xf00>; |
| 76 | resets = <&cru SRST_CORE0>; |
| 77 | operating-points = < |
| 78 | /* KHz uV */ |
| 79 | 816000 1000000 |
| 80 | >; |
| 81 | clock-latency = <40000>; |
| 82 | clocks = <&cru ARMCLK>; |
| 83 | }; |
| 84 | |
| 85 | cpu1: cpu@f01 { |
| 86 | device_type = "cpu"; |
| 87 | compatible = "arm,cortex-a7"; |
| 88 | reg = <0xf01>; |
| 89 | resets = <&cru SRST_CORE1>; |
| 90 | }; |
| 91 | }; |
| 92 | |
| 93 | amba { |
Masahiro Yamada | 2ef7d5f | 2016-03-09 13:26:45 +0900 | [diff] [blame] | 94 | compatible = "simple-bus"; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 95 | #address-cells = <1>; |
| 96 | #size-cells = <1>; |
| 97 | ranges; |
| 98 | |
| 99 | pdma: pdma@20078000 { |
| 100 | compatible = "arm,pl330", "arm,primecell"; |
| 101 | reg = <0x20078000 0x4000>; |
| 102 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 103 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| 104 | #dma-cells = <1>; |
Caesar Wang | 29f12bb | 2016-01-22 19:06:49 +0800 | [diff] [blame] | 105 | arm,pl330-broken-no-flushp; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 106 | clocks = <&cru ACLK_DMAC2>; |
| 107 | clock-names = "apb_pclk"; |
| 108 | }; |
| 109 | }; |
| 110 | |
| 111 | arm-pmu { |
| 112 | compatible = "arm,cortex-a7-pmu"; |
| 113 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, |
| 114 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 115 | interrupt-affinity = <&cpu0>, <&cpu1>; |
| 116 | }; |
| 117 | |
Caesar Wang | d9abae3 | 2016-02-02 11:40:50 +0800 | [diff] [blame] | 118 | display-subsystem { |
| 119 | compatible = "rockchip,display-subsystem"; |
| 120 | ports = <&vop_out>; |
| 121 | }; |
| 122 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 123 | timer { |
| 124 | compatible = "arm,armv7-timer"; |
| 125 | arm,cpu-registers-not-fw-configured; |
| 126 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, |
| 127 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, |
| 128 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, |
| 129 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 130 | clock-frequency = <24000000>; |
| 131 | }; |
| 132 | |
| 133 | xin24m: oscillator { |
| 134 | compatible = "fixed-clock"; |
| 135 | clock-frequency = <24000000>; |
| 136 | clock-output-names = "xin24m"; |
| 137 | #clock-cells = <0>; |
| 138 | }; |
| 139 | |
| 140 | bus_intmem@10080000 { |
| 141 | compatible = "mmio-sram"; |
| 142 | reg = <0x10080000 0x2000>; |
| 143 | #address-cells = <1>; |
| 144 | #size-cells = <1>; |
| 145 | ranges = <0 0x10080000 0x2000>; |
| 146 | |
| 147 | smp-sram@0 { |
| 148 | compatible = "rockchip,rk3066-smp-sram"; |
| 149 | reg = <0x00 0x10>; |
| 150 | }; |
| 151 | }; |
| 152 | |
Caesar Wang | d9abae3 | 2016-02-02 11:40:50 +0800 | [diff] [blame] | 153 | vop: vop@10118000 { |
| 154 | compatible = "rockchip,rk3036-vop"; |
| 155 | reg = <0x10118000 0x19c>; |
| 156 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 157 | clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; |
| 158 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; |
| 159 | resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; |
| 160 | reset-names = "axi", "ahb", "dclk"; |
| 161 | iommus = <&vop_mmu>; |
| 162 | status = "disabled"; |
| 163 | |
| 164 | vop_out: port { |
| 165 | #address-cells = <1>; |
| 166 | #size-cells = <0>; |
Caesar Wang | b7217cf | 2016-02-02 11:40:50 +0800 | [diff] [blame] | 167 | vop_out_hdmi: endpoint@0 { |
| 168 | reg = <0>; |
| 169 | remote-endpoint = <&hdmi_in_vop>; |
| 170 | }; |
Caesar Wang | d9abae3 | 2016-02-02 11:40:50 +0800 | [diff] [blame] | 171 | }; |
| 172 | }; |
| 173 | |
| 174 | vop_mmu: iommu@10118300 { |
| 175 | compatible = "rockchip,iommu"; |
| 176 | reg = <0x10118300 0x100>; |
| 177 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 178 | interrupt-names = "vop_mmu"; |
| 179 | #iommu-cells = <0>; |
| 180 | status = "disabled"; |
| 181 | }; |
| 182 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 183 | gic: interrupt-controller@10139000 { |
| 184 | compatible = "arm,gic-400"; |
| 185 | interrupt-controller; |
| 186 | #interrupt-cells = <3>; |
| 187 | #address-cells = <0>; |
| 188 | |
| 189 | reg = <0x10139000 0x1000>, |
| 190 | <0x1013a000 0x1000>, |
| 191 | <0x1013c000 0x2000>, |
| 192 | <0x1013e000 0x2000>; |
| 193 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 194 | }; |
| 195 | |
| 196 | usb_otg: usb@10180000 { |
Caesar Wang | 0082180 | 2016-01-14 09:08:41 +0800 | [diff] [blame] | 197 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 198 | "snps,dwc2"; |
| 199 | reg = <0x10180000 0x40000>; |
| 200 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 201 | clocks = <&cru HCLK_OTG0>; |
| 202 | clock-names = "otg"; |
| 203 | dr_mode = "otg"; |
| 204 | g-np-tx-fifo-size = <16>; |
| 205 | g-rx-fifo-size = <275>; |
| 206 | g-tx-fifo-size = <256 128 128 64 64 32>; |
| 207 | g-use-dma; |
| 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
| 211 | usb_host: usb@101c0000 { |
Caesar Wang | 0082180 | 2016-01-14 09:08:41 +0800 | [diff] [blame] | 212 | compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 213 | "snps,dwc2"; |
| 214 | reg = <0x101c0000 0x40000>; |
| 215 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 216 | clocks = <&cru HCLK_OTG1>; |
| 217 | clock-names = "otg"; |
| 218 | dr_mode = "host"; |
| 219 | status = "disabled"; |
| 220 | }; |
| 221 | |
Xing Zheng | af671e7 | 2016-03-14 16:02:00 +0800 | [diff] [blame] | 222 | emac: ethernet@10200000 { |
| 223 | compatible = "rockchip,rk3036-emac", "snps,arc-emac"; |
| 224 | reg = <0x10200000 0x4000>; |
| 225 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| 226 | #address-cells = <1>; |
| 227 | #size-cells = <0>; |
| 228 | rockchip,grf = <&grf>; |
| 229 | clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; |
| 230 | clock-names = "hclk", "macref", "macclk"; |
| 231 | /* |
| 232 | * Fix the emac parent clock is DPLL instead of APLL. |
| 233 | * since that will cause some unstable things if the cpufreq |
| 234 | * is working. (e.g: the accurate 50MHz what mac_ref need) |
| 235 | */ |
| 236 | assigned-clocks = <&cru SCLK_MACPLL>; |
| 237 | assigned-clock-parents = <&cru PLL_DPLL>; |
| 238 | max-speed = <100>; |
| 239 | phy-mode = "rmii"; |
| 240 | status = "disabled"; |
| 241 | }; |
| 242 | |
Caesar Wang | 187d796 | 2015-12-17 22:21:49 +0800 | [diff] [blame] | 243 | sdmmc: dwmmc@10214000 { |
| 244 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| 245 | reg = <0x10214000 0x4000>; |
| 246 | clock-frequency = <37500000>; |
| 247 | clock-freq-min-max = <400000 37500000>; |
| 248 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; |
| 249 | clock-names = "biu", "ciu"; |
| 250 | fifo-depth = <0x100>; |
| 251 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | status = "disabled"; |
| 253 | }; |
| 254 | |
| 255 | sdio: dwmmc@10218000 { |
| 256 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| 257 | reg = <0x10218000 0x4000>; |
| 258 | clock-freq-min-max = <400000 37500000>; |
| 259 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, |
| 260 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; |
| 261 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; |
| 262 | fifo-depth = <0x100>; |
| 263 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 264 | status = "disabled"; |
| 265 | }; |
| 266 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 267 | emmc: dwmmc@1021c000 { |
Caesar Wang | 0082180 | 2016-01-14 09:08:41 +0800 | [diff] [blame] | 268 | compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 269 | reg = <0x1021c000 0x4000>; |
| 270 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 271 | bus-width = <8>; |
| 272 | cap-mmc-highspeed; |
| 273 | clock-frequency = <37500000>; |
| 274 | clock-freq-min-max = <400000 37500000>; |
| 275 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, |
| 276 | <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; |
| 277 | clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; |
| 278 | default-sample-phase = <158>; |
| 279 | disable-wp; |
| 280 | dmas = <&pdma 12>; |
| 281 | dma-names = "rx-tx"; |
| 282 | fifo-depth = <0x100>; |
| 283 | mmc-ddr-1_8v; |
| 284 | non-removable; |
| 285 | num-slots = <1>; |
| 286 | pinctrl-names = "default"; |
| 287 | pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; |
| 288 | status = "disabled"; |
| 289 | }; |
| 290 | |
| 291 | i2s: i2s@10220000 { |
| 292 | compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; |
| 293 | reg = <0x10220000 0x4000>; |
| 294 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| 295 | #address-cells = <1>; |
| 296 | #size-cells = <0>; |
Heiko Stuebner | 3860aa1c | 2016-01-09 03:18:51 +0100 | [diff] [blame] | 297 | clock-names = "i2s_clk", "i2s_hclk"; |
| 298 | clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 299 | dmas = <&pdma 0>, <&pdma 1>; |
| 300 | dma-names = "tx", "rx"; |
| 301 | pinctrl-names = "default"; |
| 302 | pinctrl-0 = <&i2s_bus>; |
| 303 | status = "disabled"; |
| 304 | }; |
| 305 | |
| 306 | cru: clock-controller@20000000 { |
| 307 | compatible = "rockchip,rk3036-cru"; |
| 308 | reg = <0x20000000 0x1000>; |
| 309 | rockchip,grf = <&grf>; |
| 310 | #clock-cells = <1>; |
| 311 | #reset-cells = <1>; |
| 312 | assigned-clocks = <&cru PLL_GPLL>; |
| 313 | assigned-clock-rates = <594000000>; |
| 314 | }; |
| 315 | |
| 316 | grf: syscon@20008000 { |
Andy Yan | b60ab70 | 2016-07-06 21:28:34 +0800 | [diff] [blame] | 317 | compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 318 | reg = <0x20008000 0x1000>; |
Andy Yan | b60ab70 | 2016-07-06 21:28:34 +0800 | [diff] [blame] | 319 | |
| 320 | reboot-mode { |
| 321 | compatible = "syscon-reboot-mode"; |
| 322 | offset = <0x1d8>; |
| 323 | mode-normal = <BOOT_NORMAL>; |
| 324 | mode-recovery = <BOOT_RECOVERY>; |
| 325 | mode-bootloader = <BOOT_FASTBOOT>; |
| 326 | mode-loader = <BOOT_BL_DOWNLOAD>; |
| 327 | }; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | acodec: acodec-ana@20030000 { |
| 331 | compatible = "rk3036-codec"; |
| 332 | reg = <0x20030000 0x4000>; |
| 333 | rockchip,grf = <&grf>; |
| 334 | clock-names = "acodec_pclk"; |
| 335 | clocks = <&cru PCLK_ACODEC>; |
| 336 | status = "disabled"; |
| 337 | }; |
| 338 | |
Caesar Wang | b7217cf | 2016-02-02 11:40:50 +0800 | [diff] [blame] | 339 | hdmi: hdmi@20034000 { |
| 340 | compatible = "rockchip,rk3036-inno-hdmi"; |
| 341 | reg = <0x20034000 0x4000>; |
| 342 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 343 | clocks = <&cru PCLK_HDMI>; |
| 344 | clock-names = "pclk"; |
| 345 | rockchip,grf = <&grf>; |
| 346 | pinctrl-names = "default"; |
| 347 | pinctrl-0 = <&hdmi_ctl>; |
| 348 | status = "disabled"; |
| 349 | |
| 350 | hdmi_in: port { |
| 351 | #address-cells = <1>; |
| 352 | #size-cells = <0>; |
| 353 | hdmi_in_vop: endpoint@0 { |
| 354 | reg = <0>; |
| 355 | remote-endpoint = <&vop_out_hdmi>; |
| 356 | }; |
| 357 | }; |
| 358 | }; |
| 359 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 360 | timer: timer@20044000 { |
| 361 | compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; |
| 362 | reg = <0x20044000 0x20>; |
| 363 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 364 | clocks = <&xin24m>, <&cru PCLK_TIMER>; |
| 365 | clock-names = "timer", "pclk"; |
| 366 | }; |
| 367 | |
| 368 | pwm0: pwm@20050000 { |
| 369 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; |
| 370 | reg = <0x20050000 0x10>; |
| 371 | #pwm-cells = <3>; |
| 372 | clocks = <&cru PCLK_PWM>; |
| 373 | clock-names = "pwm"; |
| 374 | pinctrl-names = "default"; |
| 375 | pinctrl-0 = <&pwm0_pin>; |
| 376 | status = "disabled"; |
| 377 | }; |
| 378 | |
| 379 | pwm1: pwm@20050010 { |
| 380 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; |
| 381 | reg = <0x20050010 0x10>; |
| 382 | #pwm-cells = <3>; |
| 383 | clocks = <&cru PCLK_PWM>; |
| 384 | clock-names = "pwm"; |
| 385 | pinctrl-names = "default"; |
| 386 | pinctrl-0 = <&pwm1_pin>; |
| 387 | status = "disabled"; |
| 388 | }; |
| 389 | |
| 390 | pwm2: pwm@20050020 { |
| 391 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; |
| 392 | reg = <0x20050020 0x10>; |
| 393 | #pwm-cells = <3>; |
| 394 | clocks = <&cru PCLK_PWM>; |
| 395 | clock-names = "pwm"; |
| 396 | pinctrl-names = "default"; |
| 397 | pinctrl-0 = <&pwm2_pin>; |
| 398 | status = "disabled"; |
| 399 | }; |
| 400 | |
| 401 | pwm3: pwm@20050030 { |
| 402 | compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; |
| 403 | reg = <0x20050030 0x10>; |
| 404 | #pwm-cells = <2>; |
| 405 | clocks = <&cru PCLK_PWM>; |
| 406 | clock-names = "pwm"; |
| 407 | pinctrl-names = "default"; |
| 408 | pinctrl-0 = <&pwm3_pin>; |
| 409 | status = "disabled"; |
| 410 | }; |
| 411 | |
| 412 | i2c1: i2c@20056000 { |
Caesar Wang | 0082180 | 2016-01-14 09:08:41 +0800 | [diff] [blame] | 413 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 414 | reg = <0x20056000 0x1000>; |
| 415 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 416 | #address-cells = <1>; |
| 417 | #size-cells = <0>; |
| 418 | clock-names = "i2c"; |
| 419 | clocks = <&cru PCLK_I2C1>; |
| 420 | pinctrl-names = "default"; |
| 421 | pinctrl-0 = <&i2c1_xfer>; |
| 422 | status = "disabled"; |
| 423 | }; |
| 424 | |
| 425 | i2c2: i2c@2005a000 { |
Caesar Wang | 0082180 | 2016-01-14 09:08:41 +0800 | [diff] [blame] | 426 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 427 | reg = <0x2005a000 0x1000>; |
| 428 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| 429 | #address-cells = <1>; |
| 430 | #size-cells = <0>; |
| 431 | clock-names = "i2c"; |
| 432 | clocks = <&cru PCLK_I2C2>; |
| 433 | pinctrl-names = "default"; |
| 434 | pinctrl-0 = <&i2c2_xfer>; |
| 435 | status = "disabled"; |
| 436 | }; |
| 437 | |
| 438 | uart0: serial@20060000 { |
| 439 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; |
| 440 | reg = <0x20060000 0x100>; |
| 441 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 442 | reg-shift = <2>; |
| 443 | reg-io-width = <4>; |
| 444 | clock-frequency = <24000000>; |
| 445 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; |
| 446 | clock-names = "baudclk", "apb_pclk"; |
| 447 | pinctrl-names = "default"; |
| 448 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; |
| 449 | status = "disabled"; |
| 450 | }; |
| 451 | |
| 452 | uart1: serial@20064000 { |
| 453 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; |
| 454 | reg = <0x20064000 0x100>; |
| 455 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 456 | reg-shift = <2>; |
| 457 | reg-io-width = <4>; |
| 458 | clock-frequency = <24000000>; |
| 459 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; |
| 460 | clock-names = "baudclk", "apb_pclk"; |
| 461 | pinctrl-names = "default"; |
| 462 | pinctrl-0 = <&uart1_xfer>; |
| 463 | status = "disabled"; |
| 464 | }; |
| 465 | |
| 466 | uart2: serial@20068000 { |
| 467 | compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; |
| 468 | reg = <0x20068000 0x100>; |
| 469 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 470 | reg-shift = <2>; |
| 471 | reg-io-width = <4>; |
| 472 | clock-frequency = <24000000>; |
| 473 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; |
| 474 | clock-names = "baudclk", "apb_pclk"; |
| 475 | pinctrl-names = "default"; |
| 476 | pinctrl-0 = <&uart2_xfer>; |
| 477 | status = "disabled"; |
| 478 | }; |
| 479 | |
| 480 | i2c0: i2c@20072000 { |
Caesar Wang | 0082180 | 2016-01-14 09:08:41 +0800 | [diff] [blame] | 481 | compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 482 | reg = <0x20072000 0x1000>; |
| 483 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| 484 | #address-cells = <1>; |
| 485 | #size-cells = <0>; |
| 486 | clock-names = "i2c"; |
| 487 | clocks = <&cru PCLK_I2C0>; |
| 488 | pinctrl-names = "default"; |
| 489 | pinctrl-0 = <&i2c0_xfer>; |
| 490 | status = "disabled"; |
| 491 | }; |
| 492 | |
Caesar Wang | f629fcf | 2016-02-02 11:40:53 +0800 | [diff] [blame] | 493 | spi: spi@20074000 { |
| 494 | compatible = "rockchip,rockchip-spi"; |
| 495 | reg = <0x20074000 0x1000>; |
| 496 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 497 | clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>; |
| 498 | clock-names = "apb-pclk","spi_pclk"; |
| 499 | dmas = <&pdma 8>, <&pdma 9>; |
| 500 | dma-names = "tx", "rx"; |
| 501 | pinctrl-names = "default"; |
| 502 | pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; |
| 503 | #address-cells = <1>; |
| 504 | #size-cells = <0>; |
| 505 | status = "disabled"; |
| 506 | }; |
| 507 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 508 | pinctrl: pinctrl { |
| 509 | compatible = "rockchip,rk3036-pinctrl"; |
| 510 | rockchip,grf = <&grf>; |
| 511 | #address-cells = <1>; |
| 512 | #size-cells = <1>; |
| 513 | ranges; |
| 514 | |
| 515 | gpio0: gpio0@2007c000 { |
| 516 | compatible = "rockchip,gpio-bank"; |
| 517 | reg = <0x2007c000 0x100>; |
| 518 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 519 | clocks = <&cru PCLK_GPIO0>; |
| 520 | |
| 521 | gpio-controller; |
| 522 | #gpio-cells = <2>; |
| 523 | |
| 524 | interrupt-controller; |
| 525 | #interrupt-cells = <2>; |
| 526 | }; |
| 527 | |
| 528 | gpio1: gpio1@20080000 { |
| 529 | compatible = "rockchip,gpio-bank"; |
| 530 | reg = <0x20080000 0x100>; |
| 531 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 532 | clocks = <&cru PCLK_GPIO1>; |
| 533 | |
| 534 | gpio-controller; |
| 535 | #gpio-cells = <2>; |
| 536 | |
| 537 | interrupt-controller; |
| 538 | #interrupt-cells = <2>; |
| 539 | }; |
| 540 | |
| 541 | gpio2: gpio2@20084000 { |
| 542 | compatible = "rockchip,gpio-bank"; |
| 543 | reg = <0x20084000 0x100>; |
| 544 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 545 | clocks = <&cru PCLK_GPIO2>; |
| 546 | |
| 547 | gpio-controller; |
| 548 | #gpio-cells = <2>; |
| 549 | |
| 550 | interrupt-controller; |
| 551 | #interrupt-cells = <2>; |
| 552 | }; |
| 553 | |
Xing Zheng | 68556dd | 2015-12-17 22:21:47 +0800 | [diff] [blame] | 554 | pcfg_pull_default: pcfg_pull_default { |
| 555 | bias-pull-pin-default; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 556 | }; |
| 557 | |
| 558 | pcfg_pull_none: pcfg-pull-none { |
| 559 | bias-disable; |
| 560 | }; |
| 561 | |
| 562 | pwm0 { |
| 563 | pwm0_pin: pwm0-pin { |
| 564 | rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; |
| 565 | }; |
| 566 | }; |
| 567 | |
| 568 | pwm1 { |
| 569 | pwm1_pin: pwm1-pin { |
| 570 | rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; |
| 571 | }; |
| 572 | }; |
| 573 | |
| 574 | pwm2 { |
| 575 | pwm2_pin: pwm2-pin { |
| 576 | rockchip,pins = <0 1 2 &pcfg_pull_none>; |
| 577 | }; |
| 578 | }; |
| 579 | |
| 580 | pwm3 { |
| 581 | pwm3_pin: pwm3-pin { |
| 582 | rockchip,pins = <0 27 1 &pcfg_pull_none>; |
| 583 | }; |
| 584 | }; |
| 585 | |
Caesar Wang | 187d796 | 2015-12-17 22:21:49 +0800 | [diff] [blame] | 586 | sdmmc { |
| 587 | sdmmc_clk: sdmmc-clk { |
| 588 | rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>; |
| 589 | }; |
| 590 | |
| 591 | sdmmc_cmd: sdmmc-cmd { |
| 592 | rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>; |
| 593 | }; |
| 594 | |
| 595 | sdmmc_cd: sdmcc-cd { |
| 596 | rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>; |
| 597 | }; |
| 598 | |
| 599 | sdmmc_bus1: sdmmc-bus1 { |
| 600 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>; |
| 601 | }; |
| 602 | |
| 603 | sdmmc_bus4: sdmmc-bus4 { |
| 604 | rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>, |
| 605 | <1 19 RK_FUNC_1 &pcfg_pull_default>, |
| 606 | <1 20 RK_FUNC_1 &pcfg_pull_default>, |
| 607 | <1 21 RK_FUNC_1 &pcfg_pull_default>; |
| 608 | }; |
| 609 | }; |
| 610 | |
| 611 | sdio { |
| 612 | sdio_bus1: sdio-bus1 { |
| 613 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>; |
| 614 | }; |
| 615 | |
| 616 | sdio_bus4: sdio-bus4 { |
| 617 | rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>, |
| 618 | <0 12 RK_FUNC_1 &pcfg_pull_default>, |
| 619 | <0 13 RK_FUNC_1 &pcfg_pull_default>, |
| 620 | <0 14 RK_FUNC_1 &pcfg_pull_default>; |
| 621 | }; |
| 622 | |
| 623 | sdio_cmd: sdio-cmd { |
| 624 | rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>; |
| 625 | }; |
| 626 | |
| 627 | sdio_clk: sdio-clk { |
| 628 | rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>; |
| 629 | }; |
| 630 | }; |
| 631 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 632 | emmc { |
| 633 | /* |
| 634 | * We run eMMC at max speed; bump up drive strength. |
| 635 | * We also have external pulls, so disable the internal ones. |
| 636 | */ |
| 637 | emmc_clk: emmc-clk { |
| 638 | rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; |
| 639 | }; |
| 640 | |
| 641 | emmc_cmd: emmc-cmd { |
Xing Zheng | 68556dd | 2015-12-17 22:21:47 +0800 | [diff] [blame] | 642 | rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 643 | }; |
| 644 | |
| 645 | emmc_bus8: emmc-bus8 { |
Xing Zheng | 68556dd | 2015-12-17 22:21:47 +0800 | [diff] [blame] | 646 | rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>, |
| 647 | <1 25 RK_FUNC_2 &pcfg_pull_default>, |
| 648 | <1 26 RK_FUNC_2 &pcfg_pull_default>, |
| 649 | <1 27 RK_FUNC_2 &pcfg_pull_default>, |
| 650 | <1 28 RK_FUNC_2 &pcfg_pull_default>, |
| 651 | <1 29 RK_FUNC_2 &pcfg_pull_default>, |
| 652 | <1 30 RK_FUNC_2 &pcfg_pull_default>, |
| 653 | <1 31 RK_FUNC_2 &pcfg_pull_default>; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 654 | }; |
| 655 | }; |
| 656 | |
Xing Zheng | af671e7 | 2016-03-14 16:02:00 +0800 | [diff] [blame] | 657 | emac { |
| 658 | emac_xfer: emac-xfer { |
| 659 | rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */ |
| 660 | <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */ |
| 661 | <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */ |
| 662 | <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */ |
| 663 | <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */ |
| 664 | <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */ |
| 665 | <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */ |
| 666 | <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */ |
| 667 | }; |
| 668 | |
| 669 | emac_mdio: emac-mdio { |
| 670 | rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */ |
| 671 | <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */ |
| 672 | }; |
| 673 | }; |
| 674 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 675 | i2c0 { |
| 676 | i2c0_xfer: i2c0-xfer { |
| 677 | rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, |
| 678 | <0 1 RK_FUNC_1 &pcfg_pull_none>; |
| 679 | }; |
| 680 | }; |
| 681 | |
| 682 | i2c1 { |
| 683 | i2c1_xfer: i2c1-xfer { |
| 684 | rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, |
| 685 | <0 3 RK_FUNC_1 &pcfg_pull_none>; |
| 686 | }; |
| 687 | }; |
| 688 | |
| 689 | i2c2 { |
| 690 | i2c2_xfer: i2c2-xfer { |
| 691 | rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, |
| 692 | <2 21 RK_FUNC_1 &pcfg_pull_none>; |
| 693 | }; |
| 694 | }; |
| 695 | |
| 696 | i2s { |
| 697 | i2s_bus: i2s-bus { |
Caesar Wang | f475533 | 2016-01-07 16:25:44 +0800 | [diff] [blame] | 698 | rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, |
| 699 | <1 1 RK_FUNC_1 &pcfg_pull_default>, |
| 700 | <1 2 RK_FUNC_1 &pcfg_pull_default>, |
| 701 | <1 3 RK_FUNC_1 &pcfg_pull_default>, |
| 702 | <1 4 RK_FUNC_1 &pcfg_pull_default>, |
| 703 | <1 5 RK_FUNC_1 &pcfg_pull_default>; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 704 | }; |
| 705 | }; |
| 706 | |
Caesar Wang | b7217cf | 2016-02-02 11:40:50 +0800 | [diff] [blame] | 707 | hdmi { |
| 708 | hdmi_ctl: hdmi-ctl { |
| 709 | rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, |
| 710 | <1 9 RK_FUNC_1 &pcfg_pull_none>, |
| 711 | <1 10 RK_FUNC_1 &pcfg_pull_none>, |
| 712 | <1 11 RK_FUNC_1 &pcfg_pull_none>; |
| 713 | }; |
| 714 | }; |
| 715 | |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 716 | uart0 { |
| 717 | uart0_xfer: uart0-xfer { |
Xing Zheng | 68556dd | 2015-12-17 22:21:47 +0800 | [diff] [blame] | 718 | rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 719 | <0 17 RK_FUNC_1 &pcfg_pull_none>; |
| 720 | }; |
| 721 | |
| 722 | uart0_cts: uart0-cts { |
Xing Zheng | 68556dd | 2015-12-17 22:21:47 +0800 | [diff] [blame] | 723 | rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 724 | }; |
| 725 | |
| 726 | uart0_rts: uart0-rts { |
| 727 | rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; |
| 728 | }; |
| 729 | }; |
| 730 | |
| 731 | uart1 { |
| 732 | uart1_xfer: uart1-xfer { |
Xing Zheng | 68556dd | 2015-12-17 22:21:47 +0800 | [diff] [blame] | 733 | rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>, |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 734 | <2 23 RK_FUNC_1 &pcfg_pull_none>; |
| 735 | }; |
| 736 | /* no rts / cts for uart1 */ |
| 737 | }; |
| 738 | |
| 739 | uart2 { |
| 740 | uart2_xfer: uart2-xfer { |
Xing Zheng | 68556dd | 2015-12-17 22:21:47 +0800 | [diff] [blame] | 741 | rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>, |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 742 | <1 19 RK_FUNC_2 &pcfg_pull_none>; |
| 743 | }; |
| 744 | /* no rts / cts for uart2 */ |
| 745 | }; |
Caesar Wang | f629fcf | 2016-02-02 11:40:53 +0800 | [diff] [blame] | 746 | |
Rob Herring | c88208f | 2018-09-13 13:12:36 -0500 | [diff] [blame] | 747 | spi-pins { |
Caesar Wang | f629fcf | 2016-02-02 11:40:53 +0800 | [diff] [blame] | 748 | spi_txd:spi-txd { |
| 749 | rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>; |
| 750 | }; |
| 751 | |
| 752 | spi_rxd:spi-rxd { |
| 753 | rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>; |
| 754 | }; |
| 755 | |
| 756 | spi_clk:spi-clk { |
| 757 | rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>; |
| 758 | }; |
| 759 | |
| 760 | spi_cs0:spi-cs0 { |
| 761 | rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>; |
| 762 | |
| 763 | }; |
| 764 | |
| 765 | spi_cs1:spi-cs1 { |
| 766 | rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>; |
| 767 | |
| 768 | }; |
| 769 | }; |
Xing Zheng | faea098 | 2015-11-05 15:39:52 +0800 | [diff] [blame] | 770 | }; |
| 771 | }; |