Thierry Reding | 2cc85bd | 2015-03-23 10:32:57 +0100 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
| 3 | #include <dt-bindings/input/input.h> |
| 4 | #include "tegra210-p2530.dtsi" |
| 5 | |
| 6 | / { |
| 7 | model = "NVIDIA Tegra210 P2571 reference design"; |
| 8 | compatible = "nvidia,p2571", "nvidia,tegra210"; |
| 9 | |
Thierry Reding | be70771 | 2016-04-11 15:35:06 +0200 | [diff] [blame] | 10 | pinmux: pinmux@700008d4 { |
Thierry Reding | 2cc85bd | 2015-03-23 10:32:57 +0100 | [diff] [blame] | 11 | pinctrl-names = "boot"; |
| 12 | pinctrl-0 = <&state_boot>; |
| 13 | |
| 14 | state_boot: pinmux { |
| 15 | pex_l0_rst_n_pa0 { |
| 16 | nvidia,pins = "pex_l0_rst_n_pa0"; |
| 17 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 18 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 19 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 20 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 21 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 22 | }; |
| 23 | pex_l0_clkreq_n_pa1 { |
| 24 | nvidia,pins = "pex_l0_clkreq_n_pa1"; |
| 25 | nvidia,function = "rsvd1"; |
| 26 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 27 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 28 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 29 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 30 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 31 | }; |
| 32 | pex_wake_n_pa2 { |
| 33 | nvidia,pins = "pex_wake_n_pa2"; |
| 34 | nvidia,function = "rsvd1"; |
| 35 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 36 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 37 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 38 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 39 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 40 | }; |
| 41 | pex_l1_rst_n_pa3 { |
| 42 | nvidia,pins = "pex_l1_rst_n_pa3"; |
| 43 | nvidia,function = "rsvd1"; |
| 44 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 45 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 46 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 47 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 48 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 49 | }; |
| 50 | pex_l1_clkreq_n_pa4 { |
| 51 | nvidia,pins = "pex_l1_clkreq_n_pa4"; |
| 52 | nvidia,function = "rsvd1"; |
| 53 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 54 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 55 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 56 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 57 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 58 | }; |
| 59 | sata_led_active_pa5 { |
| 60 | nvidia,pins = "sata_led_active_pa5"; |
| 61 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 62 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 63 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 64 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 65 | }; |
| 66 | pa6 { |
| 67 | nvidia,pins = "pa6"; |
| 68 | nvidia,function = "rsvd1"; |
| 69 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 70 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 71 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 72 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 73 | }; |
| 74 | dap1_fs_pb0 { |
| 75 | nvidia,pins = "dap1_fs_pb0"; |
| 76 | nvidia,function = "rsvd1"; |
| 77 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 78 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 79 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 80 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 81 | }; |
| 82 | dap1_din_pb1 { |
| 83 | nvidia,pins = "dap1_din_pb1"; |
| 84 | nvidia,function = "rsvd1"; |
| 85 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 86 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 87 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 88 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 89 | }; |
| 90 | dap1_dout_pb2 { |
| 91 | nvidia,pins = "dap1_dout_pb2"; |
| 92 | nvidia,function = "rsvd1"; |
| 93 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 94 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 95 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 96 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 97 | }; |
| 98 | dap1_sclk_pb3 { |
| 99 | nvidia,pins = "dap1_sclk_pb3"; |
| 100 | nvidia,function = "rsvd1"; |
| 101 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 102 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 103 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 104 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 105 | }; |
| 106 | spi2_mosi_pb4 { |
| 107 | nvidia,pins = "spi2_mosi_pb4"; |
| 108 | nvidia,function = "rsvd2"; |
| 109 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 110 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 111 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 112 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 113 | }; |
| 114 | spi2_miso_pb5 { |
| 115 | nvidia,pins = "spi2_miso_pb5"; |
| 116 | nvidia,function = "rsvd2"; |
| 117 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 118 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 119 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 120 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 121 | }; |
| 122 | spi2_sck_pb6 { |
| 123 | nvidia,pins = "spi2_sck_pb6"; |
| 124 | nvidia,function = "rsvd2"; |
| 125 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 126 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 127 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 128 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 129 | }; |
| 130 | spi2_cs0_pb7 { |
| 131 | nvidia,pins = "spi2_cs0_pb7"; |
| 132 | nvidia,function = "rsvd2"; |
| 133 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 134 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 135 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 136 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 137 | }; |
| 138 | spi1_mosi_pc0 { |
| 139 | nvidia,pins = "spi1_mosi_pc0"; |
| 140 | nvidia,function = "rsvd1"; |
| 141 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 142 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 143 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 144 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 145 | }; |
| 146 | spi1_miso_pc1 { |
| 147 | nvidia,pins = "spi1_miso_pc1"; |
| 148 | nvidia,function = "rsvd1"; |
| 149 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 150 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 151 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 152 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 153 | }; |
| 154 | spi1_sck_pc2 { |
| 155 | nvidia,pins = "spi1_sck_pc2"; |
| 156 | nvidia,function = "rsvd1"; |
| 157 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 158 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 159 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 160 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 161 | }; |
| 162 | spi1_cs0_pc3 { |
| 163 | nvidia,pins = "spi1_cs0_pc3"; |
| 164 | nvidia,function = "rsvd1"; |
| 165 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 166 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 167 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 168 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 169 | }; |
| 170 | spi1_cs1_pc4 { |
| 171 | nvidia,pins = "spi1_cs1_pc4"; |
| 172 | nvidia,function = "rsvd1"; |
| 173 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 174 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 175 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 176 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 177 | }; |
| 178 | spi4_sck_pc5 { |
| 179 | nvidia,pins = "spi4_sck_pc5"; |
| 180 | nvidia,function = "rsvd1"; |
| 181 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 182 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 184 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 185 | }; |
| 186 | spi4_cs0_pc6 { |
| 187 | nvidia,pins = "spi4_cs0_pc6"; |
| 188 | nvidia,function = "rsvd1"; |
| 189 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 190 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 191 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 192 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 193 | }; |
| 194 | spi4_mosi_pc7 { |
| 195 | nvidia,pins = "spi4_mosi_pc7"; |
| 196 | nvidia,function = "rsvd1"; |
| 197 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 198 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 199 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 200 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 201 | }; |
| 202 | spi4_miso_pd0 { |
| 203 | nvidia,pins = "spi4_miso_pd0"; |
| 204 | nvidia,function = "rsvd1"; |
| 205 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 206 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 207 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 208 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 209 | }; |
| 210 | uart3_tx_pd1 { |
| 211 | nvidia,pins = "uart3_tx_pd1"; |
| 212 | nvidia,function = "rsvd2"; |
| 213 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 214 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 215 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 216 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 217 | }; |
| 218 | uart3_rx_pd2 { |
| 219 | nvidia,pins = "uart3_rx_pd2"; |
| 220 | nvidia,function = "rsvd2"; |
| 221 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 222 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 223 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 224 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 225 | }; |
| 226 | uart3_rts_pd3 { |
| 227 | nvidia,pins = "uart3_rts_pd3"; |
| 228 | nvidia,function = "rsvd2"; |
| 229 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 230 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 231 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 232 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 233 | }; |
| 234 | uart3_cts_pd4 { |
| 235 | nvidia,pins = "uart3_cts_pd4"; |
| 236 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 238 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 239 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 240 | }; |
| 241 | dmic1_clk_pe0 { |
| 242 | nvidia,pins = "dmic1_clk_pe0"; |
| 243 | nvidia,function = "i2s3"; |
| 244 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 245 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 246 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 247 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 248 | }; |
| 249 | dmic1_dat_pe1 { |
| 250 | nvidia,pins = "dmic1_dat_pe1"; |
| 251 | nvidia,function = "i2s3"; |
| 252 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 254 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 255 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 256 | }; |
| 257 | dmic2_clk_pe2 { |
| 258 | nvidia,pins = "dmic2_clk_pe2"; |
| 259 | nvidia,function = "i2s3"; |
| 260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 262 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 263 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 264 | }; |
| 265 | dmic2_dat_pe3 { |
| 266 | nvidia,pins = "dmic2_dat_pe3"; |
| 267 | nvidia,function = "i2s3"; |
| 268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 270 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 271 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 272 | }; |
| 273 | dmic3_clk_pe4 { |
| 274 | nvidia,pins = "dmic3_clk_pe4"; |
| 275 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 276 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 277 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 278 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 279 | }; |
| 280 | dmic3_dat_pe5 { |
| 281 | nvidia,pins = "dmic3_dat_pe5"; |
| 282 | nvidia,function = "rsvd2"; |
| 283 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 284 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 285 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 286 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 287 | }; |
| 288 | pe6 { |
| 289 | nvidia,pins = "pe6"; |
| 290 | nvidia,function = "rsvd0"; |
| 291 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 292 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 293 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 294 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 295 | }; |
| 296 | pe7 { |
| 297 | nvidia,pins = "pe7"; |
| 298 | nvidia,function = "pwm3"; |
| 299 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 300 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 301 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 302 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 303 | }; |
| 304 | gen3_i2c_scl_pf0 { |
| 305 | nvidia,pins = "gen3_i2c_scl_pf0"; |
| 306 | nvidia,function = "i2c3"; |
| 307 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 308 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 309 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 310 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 311 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 312 | }; |
| 313 | gen3_i2c_sda_pf1 { |
| 314 | nvidia,pins = "gen3_i2c_sda_pf1"; |
| 315 | nvidia,function = "i2c3"; |
| 316 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 317 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 318 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 319 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 320 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 321 | }; |
| 322 | uart2_tx_pg0 { |
| 323 | nvidia,pins = "uart2_tx_pg0"; |
| 324 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 325 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 326 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 327 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 328 | }; |
| 329 | uart2_rx_pg1 { |
| 330 | nvidia,pins = "uart2_rx_pg1"; |
| 331 | nvidia,function = "uartb"; |
| 332 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 333 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 334 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 335 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 336 | }; |
| 337 | uart2_rts_pg2 { |
| 338 | nvidia,pins = "uart2_rts_pg2"; |
| 339 | nvidia,function = "rsvd2"; |
| 340 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 341 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 342 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 343 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 344 | }; |
| 345 | uart2_cts_pg3 { |
| 346 | nvidia,pins = "uart2_cts_pg3"; |
| 347 | nvidia,function = "rsvd2"; |
| 348 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 349 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 350 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 351 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 352 | }; |
| 353 | wifi_en_ph0 { |
| 354 | nvidia,pins = "wifi_en_ph0"; |
| 355 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 356 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 357 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 358 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 359 | }; |
| 360 | wifi_rst_ph1 { |
| 361 | nvidia,pins = "wifi_rst_ph1"; |
| 362 | nvidia,function = "rsvd0"; |
| 363 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 364 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 365 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 366 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 367 | }; |
| 368 | wifi_wake_ap_ph2 { |
| 369 | nvidia,pins = "wifi_wake_ap_ph2"; |
| 370 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 371 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 372 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 373 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 374 | }; |
| 375 | ap_wake_bt_ph3 { |
| 376 | nvidia,pins = "ap_wake_bt_ph3"; |
| 377 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 378 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 379 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 380 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 381 | }; |
| 382 | bt_rst_ph4 { |
| 383 | nvidia,pins = "bt_rst_ph4"; |
| 384 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 385 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 386 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 387 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 388 | }; |
| 389 | bt_wake_ap_ph5 { |
| 390 | nvidia,pins = "bt_wake_ap_ph5"; |
| 391 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 392 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 393 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 394 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 395 | }; |
| 396 | ph6 { |
| 397 | nvidia,pins = "ph6"; |
| 398 | nvidia,function = "rsvd0"; |
| 399 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 400 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 401 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 402 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 403 | }; |
| 404 | ap_wake_nfc_ph7 { |
| 405 | nvidia,pins = "ap_wake_nfc_ph7"; |
| 406 | nvidia,function = "rsvd0"; |
| 407 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 408 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 409 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 410 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 411 | }; |
| 412 | nfc_en_pi0 { |
| 413 | nvidia,pins = "nfc_en_pi0"; |
| 414 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 415 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 416 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 417 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 418 | }; |
| 419 | nfc_int_pi1 { |
| 420 | nvidia,pins = "nfc_int_pi1"; |
| 421 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 422 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 423 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 424 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 425 | }; |
| 426 | gps_en_pi2 { |
| 427 | nvidia,pins = "gps_en_pi2"; |
| 428 | nvidia,function = "rsvd0"; |
| 429 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 430 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 431 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 432 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 433 | }; |
| 434 | gps_rst_pi3 { |
| 435 | nvidia,pins = "gps_rst_pi3"; |
| 436 | nvidia,function = "rsvd0"; |
| 437 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 438 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 439 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 440 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 441 | }; |
| 442 | uart4_tx_pi4 { |
| 443 | nvidia,pins = "uart4_tx_pi4"; |
| 444 | nvidia,function = "uartd"; |
| 445 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 446 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 447 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 448 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 449 | }; |
| 450 | uart4_rx_pi5 { |
| 451 | nvidia,pins = "uart4_rx_pi5"; |
| 452 | nvidia,function = "uartd"; |
| 453 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 454 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 455 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 456 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 457 | }; |
| 458 | uart4_rts_pi6 { |
| 459 | nvidia,pins = "uart4_rts_pi6"; |
| 460 | nvidia,function = "uartd"; |
| 461 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 462 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 463 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 464 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 465 | }; |
| 466 | uart4_cts_pi7 { |
| 467 | nvidia,pins = "uart4_cts_pi7"; |
| 468 | nvidia,function = "uartd"; |
| 469 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 470 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 471 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 472 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 473 | }; |
| 474 | gen1_i2c_sda_pj0 { |
| 475 | nvidia,pins = "gen1_i2c_sda_pj0"; |
| 476 | nvidia,function = "i2c1"; |
| 477 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 478 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 479 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 480 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 481 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 482 | }; |
| 483 | gen1_i2c_scl_pj1 { |
| 484 | nvidia,pins = "gen1_i2c_scl_pj1"; |
| 485 | nvidia,function = "i2c1"; |
| 486 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 487 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 488 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 489 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 490 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 491 | }; |
| 492 | gen2_i2c_scl_pj2 { |
| 493 | nvidia,pins = "gen2_i2c_scl_pj2"; |
| 494 | nvidia,function = "i2c2"; |
| 495 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 496 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 497 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 498 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 499 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| 500 | }; |
| 501 | gen2_i2c_sda_pj3 { |
| 502 | nvidia,pins = "gen2_i2c_sda_pj3"; |
| 503 | nvidia,function = "i2c2"; |
| 504 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 505 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 506 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 507 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 508 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| 509 | }; |
| 510 | dap4_fs_pj4 { |
| 511 | nvidia,pins = "dap4_fs_pj4"; |
| 512 | nvidia,function = "rsvd1"; |
| 513 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 514 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 515 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 516 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 517 | }; |
| 518 | dap4_din_pj5 { |
| 519 | nvidia,pins = "dap4_din_pj5"; |
| 520 | nvidia,function = "rsvd1"; |
| 521 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 522 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 523 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 524 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 525 | }; |
| 526 | dap4_dout_pj6 { |
| 527 | nvidia,pins = "dap4_dout_pj6"; |
| 528 | nvidia,function = "rsvd1"; |
| 529 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 530 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 531 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 532 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 533 | }; |
| 534 | dap4_sclk_pj7 { |
| 535 | nvidia,pins = "dap4_sclk_pj7"; |
| 536 | nvidia,function = "rsvd1"; |
| 537 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 538 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 539 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 540 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 541 | }; |
| 542 | pk0 { |
| 543 | nvidia,pins = "pk0"; |
| 544 | nvidia,function = "rsvd2"; |
| 545 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 546 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 547 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 548 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 549 | }; |
| 550 | pk1 { |
| 551 | nvidia,pins = "pk1"; |
| 552 | nvidia,function = "rsvd2"; |
| 553 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 554 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 555 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 556 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 557 | }; |
| 558 | pk2 { |
| 559 | nvidia,pins = "pk2"; |
| 560 | nvidia,function = "rsvd2"; |
| 561 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 562 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 563 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 564 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 565 | }; |
| 566 | pk3 { |
| 567 | nvidia,pins = "pk3"; |
| 568 | nvidia,function = "rsvd2"; |
| 569 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 570 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 571 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 572 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 573 | }; |
| 574 | pk4 { |
| 575 | nvidia,pins = "pk4"; |
| 576 | nvidia,function = "rsvd1"; |
| 577 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 578 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 579 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 580 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 581 | }; |
| 582 | pk5 { |
| 583 | nvidia,pins = "pk5"; |
| 584 | nvidia,function = "rsvd1"; |
| 585 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 586 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 587 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 588 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 589 | }; |
| 590 | pk6 { |
| 591 | nvidia,pins = "pk6"; |
| 592 | nvidia,function = "rsvd1"; |
| 593 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 594 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 595 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 596 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 597 | }; |
| 598 | pk7 { |
| 599 | nvidia,pins = "pk7"; |
| 600 | nvidia,function = "rsvd1"; |
| 601 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 602 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 603 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 604 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 605 | }; |
| 606 | pl0 { |
| 607 | nvidia,pins = "pl0"; |
| 608 | nvidia,function = "rsvd0"; |
| 609 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 610 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 611 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 612 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 613 | }; |
| 614 | pl1 { |
| 615 | nvidia,pins = "pl1"; |
| 616 | nvidia,function = "rsvd1"; |
| 617 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 618 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 619 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 620 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 621 | }; |
| 622 | sdmmc1_clk_pm0 { |
| 623 | nvidia,pins = "sdmmc1_clk_pm0"; |
| 624 | nvidia,function = "sdmmc1"; |
| 625 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 626 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 627 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 628 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 629 | }; |
| 630 | sdmmc1_cmd_pm1 { |
| 631 | nvidia,pins = "sdmmc1_cmd_pm1"; |
| 632 | nvidia,function = "sdmmc1"; |
| 633 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 634 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 635 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 636 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 637 | }; |
| 638 | sdmmc1_dat3_pm2 { |
| 639 | nvidia,pins = "sdmmc1_dat3_pm2"; |
| 640 | nvidia,function = "sdmmc1"; |
| 641 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 642 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 644 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 645 | }; |
| 646 | sdmmc1_dat2_pm3 { |
| 647 | nvidia,pins = "sdmmc1_dat2_pm3"; |
| 648 | nvidia,function = "sdmmc1"; |
| 649 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 650 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 651 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 652 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 653 | }; |
| 654 | sdmmc1_dat1_pm4 { |
| 655 | nvidia,pins = "sdmmc1_dat1_pm4"; |
| 656 | nvidia,function = "sdmmc1"; |
| 657 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 658 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 659 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 660 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 661 | }; |
| 662 | sdmmc1_dat0_pm5 { |
| 663 | nvidia,pins = "sdmmc1_dat0_pm5"; |
| 664 | nvidia,function = "sdmmc1"; |
| 665 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 666 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 667 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 668 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 669 | }; |
| 670 | sdmmc3_clk_pp0 { |
| 671 | nvidia,pins = "sdmmc3_clk_pp0"; |
| 672 | nvidia,function = "sdmmc3"; |
| 673 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 674 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 675 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 676 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 677 | }; |
| 678 | sdmmc3_cmd_pp1 { |
| 679 | nvidia,pins = "sdmmc3_cmd_pp1"; |
| 680 | nvidia,function = "sdmmc3"; |
| 681 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 682 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 683 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 684 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 685 | }; |
| 686 | sdmmc3_dat3_pp2 { |
| 687 | nvidia,pins = "sdmmc3_dat3_pp2"; |
| 688 | nvidia,function = "sdmmc3"; |
| 689 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 690 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 691 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 692 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 693 | }; |
| 694 | sdmmc3_dat2_pp3 { |
| 695 | nvidia,pins = "sdmmc3_dat2_pp3"; |
| 696 | nvidia,function = "sdmmc3"; |
| 697 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 698 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 699 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 700 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 701 | }; |
| 702 | sdmmc3_dat1_pp4 { |
| 703 | nvidia,pins = "sdmmc3_dat1_pp4"; |
| 704 | nvidia,function = "sdmmc3"; |
| 705 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 706 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 707 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 708 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 709 | }; |
| 710 | sdmmc3_dat0_pp5 { |
| 711 | nvidia,pins = "sdmmc3_dat0_pp5"; |
| 712 | nvidia,function = "sdmmc3"; |
| 713 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 714 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 715 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 716 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 717 | }; |
| 718 | cam1_mclk_ps0 { |
| 719 | nvidia,pins = "cam1_mclk_ps0"; |
| 720 | nvidia,function = "rsvd1"; |
| 721 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 722 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 723 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 724 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 725 | }; |
| 726 | cam2_mclk_ps1 { |
| 727 | nvidia,pins = "cam2_mclk_ps1"; |
| 728 | nvidia,function = "rsvd1"; |
| 729 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 730 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 731 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 732 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 733 | }; |
| 734 | cam_i2c_scl_ps2 { |
| 735 | nvidia,pins = "cam_i2c_scl_ps2"; |
| 736 | nvidia,function = "i2cvi"; |
| 737 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 738 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 739 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 740 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 741 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 742 | }; |
| 743 | cam_i2c_sda_ps3 { |
| 744 | nvidia,pins = "cam_i2c_sda_ps3"; |
| 745 | nvidia,function = "i2cvi"; |
| 746 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 747 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 748 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 749 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 750 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 751 | }; |
| 752 | cam_rst_ps4 { |
| 753 | nvidia,pins = "cam_rst_ps4"; |
| 754 | nvidia,function = "rsvd1"; |
| 755 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 756 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 757 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 758 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 759 | }; |
| 760 | cam_af_en_ps5 { |
| 761 | nvidia,pins = "cam_af_en_ps5"; |
| 762 | nvidia,function = "rsvd2"; |
| 763 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 764 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 765 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 766 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 767 | }; |
| 768 | cam_flash_en_ps6 { |
| 769 | nvidia,pins = "cam_flash_en_ps6"; |
| 770 | nvidia,function = "rsvd2"; |
| 771 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 772 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 773 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 774 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 775 | }; |
| 776 | cam1_pwdn_ps7 { |
| 777 | nvidia,pins = "cam1_pwdn_ps7"; |
| 778 | nvidia,function = "rsvd1"; |
| 779 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 780 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 781 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 782 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 783 | }; |
| 784 | cam2_pwdn_pt0 { |
| 785 | nvidia,pins = "cam2_pwdn_pt0"; |
| 786 | nvidia,function = "rsvd1"; |
| 787 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 788 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 789 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 790 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 791 | }; |
| 792 | cam1_strobe_pt1 { |
| 793 | nvidia,pins = "cam1_strobe_pt1"; |
| 794 | nvidia,function = "rsvd1"; |
| 795 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 796 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 797 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 798 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 799 | }; |
| 800 | uart1_tx_pu0 { |
| 801 | nvidia,pins = "uart1_tx_pu0"; |
| 802 | nvidia,function = "uarta"; |
| 803 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 804 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 805 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 806 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 807 | }; |
| 808 | uart1_rx_pu1 { |
| 809 | nvidia,pins = "uart1_rx_pu1"; |
| 810 | nvidia,function = "uarta"; |
| 811 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 812 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 813 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 814 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 815 | }; |
| 816 | uart1_rts_pu2 { |
| 817 | nvidia,pins = "uart1_rts_pu2"; |
| 818 | nvidia,function = "uarta"; |
| 819 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 820 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 821 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 822 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 823 | }; |
| 824 | uart1_cts_pu3 { |
| 825 | nvidia,pins = "uart1_cts_pu3"; |
| 826 | nvidia,function = "uarta"; |
| 827 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 828 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 829 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 830 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 831 | }; |
| 832 | lcd_bl_pwm_pv0 { |
| 833 | nvidia,pins = "lcd_bl_pwm_pv0"; |
| 834 | nvidia,function = "pwm0"; |
| 835 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 836 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 837 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 838 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 839 | }; |
| 840 | lcd_bl_en_pv1 { |
| 841 | nvidia,pins = "lcd_bl_en_pv1"; |
| 842 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 843 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 844 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 845 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 846 | }; |
| 847 | lcd_rst_pv2 { |
| 848 | nvidia,pins = "lcd_rst_pv2"; |
| 849 | nvidia,function = "rsvd0"; |
| 850 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 851 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 852 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 853 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 854 | }; |
| 855 | lcd_gpio1_pv3 { |
| 856 | nvidia,pins = "lcd_gpio1_pv3"; |
| 857 | nvidia,function = "rsvd1"; |
| 858 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 859 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 860 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 861 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 862 | }; |
| 863 | lcd_gpio2_pv4 { |
| 864 | nvidia,pins = "lcd_gpio2_pv4"; |
| 865 | nvidia,function = "pwm1"; |
| 866 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 867 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 868 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 869 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 870 | }; |
| 871 | ap_ready_pv5 { |
| 872 | nvidia,pins = "ap_ready_pv5"; |
| 873 | nvidia,function = "rsvd0"; |
| 874 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 875 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 876 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 877 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 878 | }; |
| 879 | touch_rst_pv6 { |
| 880 | nvidia,pins = "touch_rst_pv6"; |
| 881 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 882 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 883 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 884 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 885 | }; |
| 886 | touch_clk_pv7 { |
| 887 | nvidia,pins = "touch_clk_pv7"; |
| 888 | nvidia,function = "rsvd1"; |
| 889 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 890 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 891 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 892 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 893 | }; |
| 894 | modem_wake_ap_px0 { |
| 895 | nvidia,pins = "modem_wake_ap_px0"; |
| 896 | nvidia,function = "rsvd0"; |
| 897 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 898 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 899 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 900 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 901 | }; |
| 902 | touch_int_px1 { |
| 903 | nvidia,pins = "touch_int_px1"; |
| 904 | nvidia,function = "rsvd0"; |
| 905 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 906 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 907 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 908 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 909 | }; |
| 910 | motion_int_px2 { |
| 911 | nvidia,pins = "motion_int_px2"; |
| 912 | nvidia,function = "rsvd0"; |
| 913 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 914 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 915 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 916 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 917 | }; |
| 918 | als_prox_int_px3 { |
| 919 | nvidia,pins = "als_prox_int_px3"; |
| 920 | nvidia,function = "rsvd0"; |
| 921 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 922 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 923 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 924 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 925 | }; |
| 926 | temp_alert_px4 { |
| 927 | nvidia,pins = "temp_alert_px4"; |
| 928 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 929 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 930 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 931 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 932 | }; |
| 933 | button_power_on_px5 { |
| 934 | nvidia,pins = "button_power_on_px5"; |
| 935 | nvidia,function = "rsvd0"; |
| 936 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 937 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 938 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 939 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 940 | }; |
| 941 | button_vol_up_px6 { |
| 942 | nvidia,pins = "button_vol_up_px6"; |
| 943 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 944 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 945 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 946 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 947 | }; |
| 948 | button_vol_down_px7 { |
| 949 | nvidia,pins = "button_vol_down_px7"; |
| 950 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 951 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 952 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 953 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 954 | }; |
| 955 | button_slide_sw_py0 { |
| 956 | nvidia,pins = "button_slide_sw_py0"; |
| 957 | nvidia,function = "rsvd0"; |
| 958 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 959 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 960 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 961 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 962 | }; |
| 963 | button_home_py1 { |
| 964 | nvidia,pins = "button_home_py1"; |
| 965 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 966 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 967 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 968 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 969 | }; |
| 970 | lcd_te_py2 { |
| 971 | nvidia,pins = "lcd_te_py2"; |
| 972 | nvidia,function = "rsvd1"; |
| 973 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 974 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 975 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 976 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 977 | }; |
| 978 | pwr_i2c_scl_py3 { |
| 979 | nvidia,pins = "pwr_i2c_scl_py3"; |
| 980 | nvidia,function = "i2cpmu"; |
| 981 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 982 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 983 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 984 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 985 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 986 | }; |
| 987 | pwr_i2c_sda_py4 { |
| 988 | nvidia,pins = "pwr_i2c_sda_py4"; |
| 989 | nvidia,function = "i2cpmu"; |
| 990 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 991 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 992 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 993 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 994 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 995 | }; |
| 996 | clk_32k_out_py5 { |
| 997 | nvidia,pins = "clk_32k_out_py5"; |
| 998 | nvidia,function = "soc"; |
| 999 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1000 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1001 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1002 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1003 | }; |
| 1004 | pz0 { |
| 1005 | nvidia,pins = "pz0"; |
| 1006 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1007 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1008 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1009 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1010 | }; |
| 1011 | pz1 { |
| 1012 | nvidia,pins = "pz1"; |
| 1013 | nvidia,function = "sdmmc1"; |
| 1014 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1015 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1016 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1017 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1018 | }; |
| 1019 | pz2 { |
| 1020 | nvidia,pins = "pz2"; |
| 1021 | nvidia,function = "rsvd2"; |
| 1022 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1023 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1024 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1025 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1026 | }; |
| 1027 | pz3 { |
| 1028 | nvidia,pins = "pz3"; |
| 1029 | nvidia,function = "rsvd1"; |
| 1030 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1031 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1032 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1033 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1034 | }; |
| 1035 | pz4 { |
| 1036 | nvidia,pins = "pz4"; |
| 1037 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1038 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1039 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1040 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1041 | }; |
| 1042 | pz5 { |
| 1043 | nvidia,pins = "pz5"; |
| 1044 | nvidia,function = "soc"; |
| 1045 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1046 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1047 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1048 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1049 | }; |
| 1050 | dap2_fs_paa0 { |
| 1051 | nvidia,pins = "dap2_fs_paa0"; |
| 1052 | nvidia,function = "i2s2"; |
| 1053 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1054 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1055 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1056 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1057 | }; |
| 1058 | dap2_sclk_paa1 { |
| 1059 | nvidia,pins = "dap2_sclk_paa1"; |
| 1060 | nvidia,function = "i2s2"; |
| 1061 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1062 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1063 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1064 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1065 | }; |
| 1066 | dap2_din_paa2 { |
| 1067 | nvidia,pins = "dap2_din_paa2"; |
| 1068 | nvidia,function = "i2s2"; |
| 1069 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1070 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1071 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1072 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1073 | }; |
| 1074 | dap2_dout_paa3 { |
| 1075 | nvidia,pins = "dap2_dout_paa3"; |
| 1076 | nvidia,function = "i2s2"; |
| 1077 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1078 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1079 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1080 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1081 | }; |
| 1082 | aud_mclk_pbb0 { |
| 1083 | nvidia,pins = "aud_mclk_pbb0"; |
| 1084 | nvidia,function = "aud"; |
| 1085 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1086 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1087 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1088 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1089 | }; |
| 1090 | dvfs_pwm_pbb1 { |
| 1091 | nvidia,pins = "dvfs_pwm_pbb1"; |
| 1092 | nvidia,function = "cldvfs"; |
| 1093 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1094 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1095 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1096 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1097 | }; |
| 1098 | dvfs_clk_pbb2 { |
| 1099 | nvidia,pins = "dvfs_clk_pbb2"; |
| 1100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1102 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1103 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1104 | }; |
| 1105 | gpio_x1_aud_pbb3 { |
| 1106 | nvidia,pins = "gpio_x1_aud_pbb3"; |
| 1107 | nvidia,function = "rsvd0"; |
| 1108 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1109 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1110 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1111 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1112 | }; |
| 1113 | gpio_x3_aud_pbb4 { |
| 1114 | nvidia,pins = "gpio_x3_aud_pbb4"; |
| 1115 | nvidia,function = "rsvd0"; |
| 1116 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1117 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1118 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1119 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1120 | }; |
| 1121 | hdmi_cec_pcc0 { |
| 1122 | nvidia,pins = "hdmi_cec_pcc0"; |
| 1123 | nvidia,function = "cec"; |
| 1124 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1125 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1126 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1127 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1128 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| 1129 | }; |
| 1130 | hdmi_int_dp_hpd_pcc1 { |
| 1131 | nvidia,pins = "hdmi_int_dp_hpd_pcc1"; |
| 1132 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1133 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1134 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1135 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1136 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 1137 | }; |
| 1138 | spdif_out_pcc2 { |
| 1139 | nvidia,pins = "spdif_out_pcc2"; |
| 1140 | nvidia,function = "rsvd1"; |
| 1141 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1142 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1143 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1144 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1145 | }; |
| 1146 | spdif_in_pcc3 { |
| 1147 | nvidia,pins = "spdif_in_pcc3"; |
| 1148 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1149 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1150 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1151 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1152 | }; |
| 1153 | usb_vbus_en0_pcc4 { |
| 1154 | nvidia,pins = "usb_vbus_en0_pcc4"; |
| 1155 | nvidia,function = "usb"; |
| 1156 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1157 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1158 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1159 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1160 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| 1161 | }; |
| 1162 | usb_vbus_en1_pcc5 { |
| 1163 | nvidia,pins = "usb_vbus_en1_pcc5"; |
| 1164 | nvidia,function = "usb"; |
| 1165 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1166 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1167 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1168 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1169 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| 1170 | }; |
| 1171 | dp_hpd0_pcc6 { |
| 1172 | nvidia,pins = "dp_hpd0_pcc6"; |
| 1173 | nvidia,function = "rsvd1"; |
| 1174 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1175 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1176 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1177 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1178 | }; |
| 1179 | pcc7 { |
| 1180 | nvidia,pins = "pcc7"; |
| 1181 | nvidia,function = "rsvd0"; |
| 1182 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1183 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1184 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1185 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1186 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| 1187 | }; |
| 1188 | spi2_cs1_pdd0 { |
| 1189 | nvidia,pins = "spi2_cs1_pdd0"; |
| 1190 | nvidia,function = "rsvd1"; |
| 1191 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1192 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1193 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1194 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1195 | }; |
| 1196 | qspi_sck_pee0 { |
| 1197 | nvidia,pins = "qspi_sck_pee0"; |
| 1198 | nvidia,function = "rsvd1"; |
| 1199 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1200 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1202 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1203 | }; |
| 1204 | qspi_cs_n_pee1 { |
| 1205 | nvidia,pins = "qspi_cs_n_pee1"; |
| 1206 | nvidia,function = "rsvd1"; |
| 1207 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1208 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1209 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1210 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1211 | }; |
| 1212 | qspi_io0_pee2 { |
| 1213 | nvidia,pins = "qspi_io0_pee2"; |
| 1214 | nvidia,function = "rsvd1"; |
| 1215 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1216 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1217 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1218 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1219 | }; |
| 1220 | qspi_io1_pee3 { |
| 1221 | nvidia,pins = "qspi_io1_pee3"; |
| 1222 | nvidia,function = "rsvd1"; |
| 1223 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1224 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1225 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1226 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1227 | }; |
| 1228 | qspi_io2_pee4 { |
| 1229 | nvidia,pins = "qspi_io2_pee4"; |
| 1230 | nvidia,function = "rsvd1"; |
| 1231 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1232 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1233 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1234 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1235 | }; |
| 1236 | qspi_io3_pee5 { |
| 1237 | nvidia,pins = "qspi_io3_pee5"; |
| 1238 | nvidia,function = "rsvd1"; |
| 1239 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1240 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 1241 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1242 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1243 | }; |
| 1244 | core_pwr_req { |
| 1245 | nvidia,pins = "core_pwr_req"; |
| 1246 | nvidia,function = "core"; |
| 1247 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1248 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1249 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1250 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1251 | }; |
| 1252 | cpu_pwr_req { |
| 1253 | nvidia,pins = "cpu_pwr_req"; |
| 1254 | nvidia,function = "cpu"; |
| 1255 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1257 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1258 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1259 | }; |
| 1260 | pwr_int_n { |
| 1261 | nvidia,pins = "pwr_int_n"; |
| 1262 | nvidia,function = "pmi"; |
| 1263 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1264 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1265 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1266 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1267 | }; |
| 1268 | clk_32k_in { |
| 1269 | nvidia,pins = "clk_32k_in"; |
| 1270 | nvidia,function = "clk"; |
| 1271 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1272 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1273 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1274 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1275 | }; |
| 1276 | jtag_rtck { |
| 1277 | nvidia,pins = "jtag_rtck"; |
| 1278 | nvidia,function = "jtag"; |
| 1279 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1280 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1281 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1282 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1283 | }; |
| 1284 | clk_req { |
| 1285 | nvidia,pins = "clk_req"; |
| 1286 | nvidia,function = "sys"; |
| 1287 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1288 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1289 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1290 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1291 | }; |
| 1292 | shutdown { |
| 1293 | nvidia,pins = "shutdown"; |
| 1294 | nvidia,function = "shutdown"; |
| 1295 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1296 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1297 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1298 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1299 | }; |
| 1300 | }; |
| 1301 | }; |
| 1302 | }; |