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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
AKASHI Takahirofd92d4a2014-04-30 10:51:32 +010023#include <linux/compat.h>
Ard Biesheuvel60c0d452015-03-06 15:49:24 +010024#include <linux/efi.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000025#include <linux/export.h>
26#include <linux/sched.h>
27#include <linux/kernel.h>
28#include <linux/mm.h>
29#include <linux/stddef.h>
30#include <linux/unistd.h>
31#include <linux/user.h>
32#include <linux/delay.h>
33#include <linux/reboot.h>
34#include <linux/interrupt.h>
35#include <linux/kallsyms.h>
36#include <linux/init.h>
37#include <linux/cpu.h>
38#include <linux/elfcore.h>
39#include <linux/pm.h>
40#include <linux/tick.h>
41#include <linux/utsname.h>
42#include <linux/uaccess.h>
43#include <linux/random.h>
44#include <linux/hw_breakpoint.h>
45#include <linux/personality.h>
46#include <linux/notifier.h>
Jisheng Zhang096b3222015-09-16 22:23:21 +080047#include <trace/events/power.h>
Mark Rutland5b7e8f72016-11-03 20:23:13 +000048#include <linux/percpu.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000049
James Morse57f49592016-02-05 14:58:48 +000050#include <asm/alternative.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000051#include <asm/compat.h>
52#include <asm/cacheflush.h>
James Morsed0854412016-10-18 11:27:48 +010053#include <asm/exec.h>
Will Deaconec45d1c2013-01-17 12:31:45 +000054#include <asm/fpsimd.h>
55#include <asm/mmu_context.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000056#include <asm/processor.h>
57#include <asm/stacktrace.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000058
Laura Abbottc0c264a2014-06-25 23:55:03 +010059#ifdef CONFIG_CC_STACKPROTECTOR
60#include <linux/stackprotector.h>
61unsigned long __stack_chk_guard __read_mostly;
62EXPORT_SYMBOL(__stack_chk_guard);
63#endif
64
Catalin Marinasb3901d52012-03-05 11:49:28 +000065/*
66 * Function pointers to optional machine specific functions
67 */
68void (*pm_power_off)(void);
69EXPORT_SYMBOL_GPL(pm_power_off);
70
Catalin Marinasb0946fc2013-07-23 11:05:10 +010071void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +000072
Catalin Marinasb3901d52012-03-05 11:49:28 +000073/*
74 * This is our default idle handler.
75 */
Thomas Gleixner00872982013-03-21 22:49:39 +010076void arch_cpu_idle(void)
Catalin Marinasb3901d52012-03-05 11:49:28 +000077{
78 /*
79 * This should do all the clock switching and wait for interrupt
80 * tricks
81 */
Jisheng Zhang096b3222015-09-16 22:23:21 +080082 trace_cpu_idle_rcuidle(1, smp_processor_id());
Nicolas Pitre69905662014-02-17 10:59:30 -050083 cpu_do_idle();
84 local_irq_enable();
Jisheng Zhang096b3222015-09-16 22:23:21 +080085 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
Catalin Marinasb3901d52012-03-05 11:49:28 +000086}
87
Mark Rutland9327e2c2013-10-24 20:30:18 +010088#ifdef CONFIG_HOTPLUG_CPU
89void arch_cpu_idle_dead(void)
90{
91 cpu_die();
92}
93#endif
94
Arun KS90f51a02014-05-07 02:41:22 +010095/*
96 * Called by kexec, immediately prior to machine_kexec().
97 *
98 * This must completely disable all secondary CPUs; simply causing those CPUs
99 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
100 * kexec'd kernel to use any and all RAM as it sees fit, without having to
101 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
102 * functionality embodied in disable_nonboot_cpus() to achieve this.
103 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000104void machine_shutdown(void)
105{
Arun KS90f51a02014-05-07 02:41:22 +0100106 disable_nonboot_cpus();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000107}
108
Arun KS90f51a02014-05-07 02:41:22 +0100109/*
110 * Halting simply requires that the secondary CPUs stop performing any
111 * activity (executing tasks, handling interrupts). smp_send_stop()
112 * achieves this.
113 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000114void machine_halt(void)
115{
Arun KSb9acc492014-05-07 02:41:23 +0100116 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100117 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000118 while (1);
119}
120
Arun KS90f51a02014-05-07 02:41:22 +0100121/*
122 * Power-off simply requires that the secondary CPUs stop performing any
123 * activity (executing tasks, handling interrupts). smp_send_stop()
124 * achieves this. When the system power is turned off, it will take all CPUs
125 * with it.
126 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000127void machine_power_off(void)
128{
Arun KSb9acc492014-05-07 02:41:23 +0100129 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100130 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000131 if (pm_power_off)
132 pm_power_off();
133}
134
Arun KS90f51a02014-05-07 02:41:22 +0100135/*
136 * Restart requires that the secondary CPUs stop performing any activity
Mark Rutland68234df2015-04-20 10:24:35 +0100137 * while the primary CPU resets the system. Systems with multiple CPUs must
Arun KS90f51a02014-05-07 02:41:22 +0100138 * provide a HW restart implementation, to ensure that all CPUs reset at once.
139 * This is required so that any code running after reset on the primary CPU
140 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
141 * executing pre-reset code, and using RAM that the primary CPU's code wishes
142 * to use. Implementing such co-ordination would be essentially impossible.
143 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000144void machine_restart(char *cmd)
145{
Catalin Marinasb3901d52012-03-05 11:49:28 +0000146 /* Disable interrupts first */
147 local_irq_disable();
Arun KSb9acc492014-05-07 02:41:23 +0100148 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000149
Ard Biesheuvel60c0d452015-03-06 15:49:24 +0100150 /*
151 * UpdateCapsule() depends on the system being reset via
152 * ResetSystem().
153 */
154 if (efi_enabled(EFI_RUNTIME_SERVICES))
155 efi_reboot(reboot_mode, NULL);
156
Catalin Marinasb3901d52012-03-05 11:49:28 +0000157 /* Now call the architecture specific reboot code. */
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000158 if (arm_pm_restart)
Marc Zyngierff701302013-07-11 12:13:00 +0100159 arm_pm_restart(reboot_mode, cmd);
Guenter Roeck1c7ffc32014-09-26 00:03:16 +0000160 else
161 do_kernel_restart(cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000162
163 /*
164 * Whoops - the architecture was unable to reboot.
165 */
166 printk("Reboot failed -- System halted\n");
167 while (1);
168}
169
Greg Hackmannc69559c2014-09-09 17:36:05 -0700170/*
171 * dump a block of kernel memory from around the given address
172 */
173static void show_data(unsigned long addr, int nbytes, const char *name)
174{
175 int i, j;
176 int nlines;
177 u32 *p;
178
179 /*
180 * don't attempt to dump non-kernel addresses or
181 * values that are probably just small negative numbers
182 */
183 if (addr < PAGE_OFFSET || addr > -256UL)
184 return;
185
186 printk("\n%s: %#lx:\n", name, addr);
187
188 /*
189 * round address down to a 32 bit boundary
190 * and always dump a multiple of 32 bytes
191 */
192 p = (u32 *)(addr & ~(sizeof(u32) - 1));
193 nbytes += (addr & (sizeof(u32) - 1));
194 nlines = (nbytes + 31) / 32;
195
196
197 for (i = 0; i < nlines; i++) {
198 /*
199 * just display low 16 bits of address to keep
200 * each line of the dump < 80 characters
201 */
202 printk("%04lx ", (unsigned long)p & 0xffff);
203 for (j = 0; j < 8; j++) {
204 u32 data;
205 if (probe_kernel_address(p, data)) {
Ji Zhang13b40d32018-01-26 15:04:26 +0800206 pr_cont(" ********");
Greg Hackmannc69559c2014-09-09 17:36:05 -0700207 } else {
Ji Zhang13b40d32018-01-26 15:04:26 +0800208 pr_cont(" %08x", data);
Greg Hackmannc69559c2014-09-09 17:36:05 -0700209 }
210 ++p;
211 }
Ji Zhang13b40d32018-01-26 15:04:26 +0800212 pr_cont("\n");
Greg Hackmannc69559c2014-09-09 17:36:05 -0700213 }
214}
215
216static void show_extra_register_data(struct pt_regs *regs, int nbytes)
217{
218 mm_segment_t fs;
219 unsigned int i;
220
221 fs = get_fs();
222 set_fs(KERNEL_DS);
223 show_data(regs->pc - nbytes, nbytes * 2, "PC");
224 show_data(regs->regs[30] - nbytes, nbytes * 2, "LR");
225 show_data(regs->sp - nbytes, nbytes * 2, "SP");
226 for (i = 0; i < 30; i++) {
227 char name[4];
228 snprintf(name, sizeof(name), "X%u", i);
229 show_data(regs->regs[i] - nbytes, nbytes * 2, name);
230 }
231 set_fs(fs);
232}
233
Catalin Marinasb3901d52012-03-05 11:49:28 +0000234void __show_regs(struct pt_regs *regs)
235{
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100236 int i, top_reg;
237 u64 lr, sp;
238
239 if (compat_user_mode(regs)) {
240 lr = regs->compat_lr;
241 sp = regs->compat_sp;
242 top_reg = 12;
243 } else {
244 lr = regs->regs[30];
245 sp = regs->sp;
246 top_reg = 29;
247 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000248
Tejun Heoa43cb952013-04-30 15:27:17 -0700249 show_regs_print_info(KERN_DEFAULT);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000250 print_symbol("PC is at %s\n", instruction_pointer(regs));
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100251 print_symbol("LR is at %s\n", lr);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000252 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100253 regs->pc, lr, regs->pstate);
254 printk("sp : %016llx\n", sp);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100255
256 i = top_reg;
257
258 while (i >= 0) {
Catalin Marinasb3901d52012-03-05 11:49:28 +0000259 printk("x%-2d: %016llx ", i, regs->regs[i]);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100260 i--;
261
262 if (i % 2 == 0) {
263 pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
264 i--;
265 }
266
267 pr_cont("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000268 }
Greg Hackmannc69559c2014-09-09 17:36:05 -0700269 if (!user_mode(regs))
270 show_extra_register_data(regs, 128);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000271 printk("\n");
272}
273
274void show_regs(struct pt_regs * regs)
275{
276 printk("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000277 __show_regs(regs);
278}
279
Will Deaconeb35bdd2014-09-11 14:38:16 +0100280static void tls_thread_flush(void)
281{
Mark Rutlandadf75892016-09-08 13:55:38 +0100282 write_sysreg(0, tpidr_el0);
Will Deaconeb35bdd2014-09-11 14:38:16 +0100283
284 if (is_compat_task()) {
285 current->thread.tp_value = 0;
286
287 /*
288 * We need to ensure ordering between the shadow state and the
289 * hardware state, so that we don't corrupt the hardware state
290 * with a stale shadow state during context switch.
291 */
292 barrier();
Mark Rutlandadf75892016-09-08 13:55:38 +0100293 write_sysreg(0, tpidrro_el0);
Will Deaconeb35bdd2014-09-11 14:38:16 +0100294 }
295}
296
Catalin Marinasb3901d52012-03-05 11:49:28 +0000297void flush_thread(void)
298{
299 fpsimd_flush_thread();
Will Deaconeb35bdd2014-09-11 14:38:16 +0100300 tls_thread_flush();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000301 flush_ptrace_hw_breakpoint(current);
302}
303
304void release_thread(struct task_struct *dead_task)
305{
306}
307
308int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
309{
Janet Liu6eb6c802015-06-11 12:04:32 +0800310 if (current->mm)
311 fpsimd_preserve_current_state();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000312 *dst = *src;
313 return 0;
314}
315
316asmlinkage void ret_from_fork(void) asm("ret_from_fork");
317
318int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400319 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000320{
321 struct pt_regs *childregs = task_pt_regs(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000322
Catalin Marinasb3901d52012-03-05 11:49:28 +0000323 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000324
Dave Martina3922412017-12-05 14:56:42 +0000325 /*
326 * In case p was allocated the same task_struct pointer as some
327 * other recently-exited task, make sure p is disassociated from
328 * any cpu that may have run that now-exited task recently.
329 * Otherwise we could erroneously skip reloading the FPSIMD
330 * registers for p.
331 */
332 fpsimd_flush_task_state(p);
333
Al Viro9ac08002012-10-21 15:56:52 -0400334 if (likely(!(p->flags & PF_KTHREAD))) {
335 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100336 childregs->regs[0] = 0;
Will Deacond00a3812015-05-27 15:39:40 +0100337
338 /*
339 * Read the current TLS pointer from tpidr_el0 as it may be
340 * out-of-sync with the saved value.
341 */
Mark Rutlandadf75892016-09-08 13:55:38 +0100342 *task_user_tls(p) = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100343
344 if (stack_start) {
345 if (is_compat_thread(task_thread_info(p)))
Al Viroe0fd18c2012-10-18 00:55:54 -0400346 childregs->compat_sp = stack_start;
Will Deacond00a3812015-05-27 15:39:40 +0100347 else
Al Viroe0fd18c2012-10-18 00:55:54 -0400348 childregs->sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100349 }
Will Deacond00a3812015-05-27 15:39:40 +0100350
Catalin Marinasc34501d2012-10-05 12:31:20 +0100351 /*
352 * If a TLS pointer was passed to clone (4th argument), use it
353 * for the new thread.
354 */
355 if (clone_flags & CLONE_SETTLS)
Will Deacond00a3812015-05-27 15:39:40 +0100356 p->thread.tp_value = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100357 } else {
358 memset(childregs, 0, sizeof(struct pt_regs));
359 childregs->pstate = PSR_MODE_EL1h;
James Morse57f49592016-02-05 14:58:48 +0000360 if (IS_ENABLED(CONFIG_ARM64_UAO) &&
Suzuki K Poulosefe64d7d2016-11-08 13:56:20 +0000361 cpus_have_const_cap(ARM64_HAS_UAO))
James Morse57f49592016-02-05 14:58:48 +0000362 childregs->pstate |= PSR_UAO_BIT;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100363 p->thread.cpu_context.x19 = stack_start;
364 p->thread.cpu_context.x20 = stk_sz;
365 }
366 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
367 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000368
369 ptrace_hw_copy_thread(p);
370
371 return 0;
372}
373
374static void tls_thread_switch(struct task_struct *next)
375{
Will Deaconda1016a2017-11-14 14:33:28 +0000376 unsigned long tpidr;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000377
Mark Rutlandadf75892016-09-08 13:55:38 +0100378 tpidr = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100379 *task_user_tls(current) = tpidr;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000380
Will Deaconda1016a2017-11-14 14:33:28 +0000381 if (is_compat_thread(task_thread_info(next)))
382 write_sysreg(next->thread.tp_value, tpidrro_el0);
383 else if (!arm64_kernel_unmapped_at_el0())
384 write_sysreg(0, tpidrro_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000385
Will Deaconda1016a2017-11-14 14:33:28 +0000386 write_sysreg(*task_user_tls(next), tpidr_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000387}
388
James Morse57f49592016-02-05 14:58:48 +0000389/* Restore the UAO state depending on next's addr_limit */
James Morsed0854412016-10-18 11:27:48 +0100390void uao_thread_switch(struct task_struct *next)
James Morse57f49592016-02-05 14:58:48 +0000391{
Catalin Marinase9506312016-02-18 15:50:04 +0000392 if (IS_ENABLED(CONFIG_ARM64_UAO)) {
393 if (task_thread_info(next)->addr_limit == KERNEL_DS)
394 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
395 else
396 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
397 }
James Morse57f49592016-02-05 14:58:48 +0000398}
399
Catalin Marinasb3901d52012-03-05 11:49:28 +0000400/*
Mark Rutland5b7e8f72016-11-03 20:23:13 +0000401 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
402 * shadow copy so that we can restore this upon entry from userspace.
403 *
404 * This is *only* for exception entry from EL0, and is not valid until we
405 * __switch_to() a user task.
406 */
407DEFINE_PER_CPU(struct task_struct *, __entry_task);
408
409static void entry_task_switch(struct task_struct *next)
410{
411 __this_cpu_write(__entry_task, next);
412}
413
414/*
Catalin Marinasb3901d52012-03-05 11:49:28 +0000415 * Thread switching.
416 */
417struct task_struct *__switch_to(struct task_struct *prev,
418 struct task_struct *next)
419{
420 struct task_struct *last;
421
422 fpsimd_thread_switch(next);
423 tls_thread_switch(next);
424 hw_breakpoint_thread_switch(next);
Christopher Covington33257322013-04-03 19:01:01 +0100425 contextidr_thread_switch(next);
Mark Rutland5b7e8f72016-11-03 20:23:13 +0000426 entry_task_switch(next);
James Morse57f49592016-02-05 14:58:48 +0000427 uao_thread_switch(next);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000428
Catalin Marinas5108c672013-04-24 14:47:02 +0100429 /*
430 * Complete any pending TLB or cache maintenance on this CPU in case
431 * the thread migrates to a different CPU.
432 */
Will Deacon98f76852014-05-02 16:24:10 +0100433 dsb(ish);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000434
435 /* the actual thread switch */
436 last = cpu_switch_to(prev, next);
437
438 return last;
439}
440
Catalin Marinasb3901d52012-03-05 11:49:28 +0000441unsigned long get_wchan(struct task_struct *p)
442{
443 struct stackframe frame;
Mark Rutland0c7aad62016-11-03 20:23:08 +0000444 unsigned long stack_page, ret = 0;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000445 int count = 0;
446 if (!p || p == current || p->state == TASK_RUNNING)
447 return 0;
448
Mark Rutland0c7aad62016-11-03 20:23:08 +0000449 stack_page = (unsigned long)try_get_task_stack(p);
450 if (!stack_page)
451 return 0;
452
Catalin Marinasb3901d52012-03-05 11:49:28 +0000453 frame.fp = thread_saved_fp(p);
454 frame.sp = thread_saved_sp(p);
455 frame.pc = thread_saved_pc(p);
AKASHI Takahiro20380bb2015-12-15 17:33:41 +0900456#ifdef CONFIG_FUNCTION_GRAPH_TRACER
457 frame.graph = p->curr_ret_stack;
458#endif
Catalin Marinasb3901d52012-03-05 11:49:28 +0000459 do {
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000460 if (frame.sp < stack_page ||
461 frame.sp >= stack_page + THREAD_SIZE ||
AKASHI Takahirofe13f952015-12-15 17:33:40 +0900462 unwind_frame(p, &frame))
Mark Rutland0c7aad62016-11-03 20:23:08 +0000463 goto out;
464 if (!in_sched_functions(frame.pc)) {
465 ret = frame.pc;
466 goto out;
467 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000468 } while (count ++ < 16);
Mark Rutland0c7aad62016-11-03 20:23:08 +0000469
470out:
471 put_task_stack(p);
472 return ret;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000473}
474
475unsigned long arch_align_stack(unsigned long sp)
476{
477 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
478 sp -= get_random_int() & ~PAGE_MASK;
479 return sp & ~0xf;
480}
481
Catalin Marinasb3901d52012-03-05 11:49:28 +0000482unsigned long arch_randomize_brk(struct mm_struct *mm)
483{
Kees Cook61462c82016-05-10 10:55:49 -0700484 if (is_compat_task())
Jason Cooperfa5114c2016-10-11 13:54:02 -0700485 return randomize_page(mm->brk, 0x02000000);
Kees Cook61462c82016-05-10 10:55:49 -0700486 else
Jason Cooperfa5114c2016-10-11 13:54:02 -0700487 return randomize_page(mm->brk, 0x40000000);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000488}