Yuan-Hsin Chen | 0fe6f1d | 2011-01-18 14:49:28 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Fusb300 UDC (USB gadget) |
| 3 | * |
| 4 | * Copyright (C) 2010 Faraday Technology Corp. |
| 5 | * |
| 6 | * Author : Yuan-hsin Chen <yhchen@faraday-tech.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | * |
| 21 | */ |
| 22 | #include <linux/dma-mapping.h> |
| 23 | #include <linux/err.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/io.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/usb/ch9.h> |
| 28 | #include <linux/usb/gadget.h> |
| 29 | |
| 30 | #include "fusb300_udc.h" |
| 31 | |
| 32 | MODULE_DESCRIPTION("FUSB300 USB gadget driver"); |
| 33 | MODULE_LICENSE("GPL"); |
| 34 | MODULE_AUTHOR("Yuan Hsin Chen <yhchen@faraday-tech.com>"); |
| 35 | MODULE_ALIAS("platform:fusb300_udc"); |
| 36 | |
| 37 | #define DRIVER_VERSION "20 October 2010" |
| 38 | |
| 39 | static const char udc_name[] = "fusb300_udc"; |
| 40 | static const char * const fusb300_ep_name[] = { |
Dan Carpenter | 6b2e30c | 2011-02-07 20:01:36 +0300 | [diff] [blame] | 41 | "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9", |
| 42 | "ep10", "ep11", "ep12", "ep13", "ep14", "ep15" |
Yuan-Hsin Chen | 0fe6f1d | 2011-01-18 14:49:28 +0800 | [diff] [blame] | 43 | }; |
| 44 | |
| 45 | static void done(struct fusb300_ep *ep, struct fusb300_request *req, |
| 46 | int status); |
| 47 | |
| 48 | static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset, |
| 49 | u32 value) |
| 50 | { |
| 51 | u32 reg = ioread32(fusb300->reg + offset); |
| 52 | |
| 53 | reg |= value; |
| 54 | iowrite32(reg, fusb300->reg + offset); |
| 55 | } |
| 56 | |
| 57 | static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset, |
| 58 | u32 value) |
| 59 | { |
| 60 | u32 reg = ioread32(fusb300->reg + offset); |
| 61 | |
| 62 | reg &= ~value; |
| 63 | iowrite32(reg, fusb300->reg + offset); |
| 64 | } |
| 65 | |
| 66 | |
| 67 | static void fusb300_ep_setting(struct fusb300_ep *ep, |
| 68 | struct fusb300_ep_info info) |
| 69 | { |
| 70 | ep->epnum = info.epnum; |
| 71 | ep->type = info.type; |
| 72 | } |
| 73 | |
| 74 | static int fusb300_ep_release(struct fusb300_ep *ep) |
| 75 | { |
| 76 | if (!ep->epnum) |
| 77 | return 0; |
| 78 | ep->epnum = 0; |
| 79 | ep->stall = 0; |
| 80 | ep->wedged = 0; |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static void fusb300_set_fifo_entry(struct fusb300 *fusb300, |
| 85 | u32 ep) |
| 86 | { |
| 87 | u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); |
| 88 | |
| 89 | val &= ~FUSB300_EPSET1_FIFOENTRY_MSK; |
| 90 | val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM); |
| 91 | iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); |
| 92 | } |
| 93 | |
| 94 | static void fusb300_set_start_entry(struct fusb300 *fusb300, |
| 95 | u8 ep) |
| 96 | { |
| 97 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); |
| 98 | u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM; |
| 99 | |
| 100 | reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ; |
| 101 | reg |= FUSB300_EPSET1_START_ENTRY(start_entry); |
| 102 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); |
| 103 | if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) { |
| 104 | fusb300->fifo_entry_num = 0; |
| 105 | fusb300->addrofs = 0; |
| 106 | pr_err("fifo entry is over the maximum number!\n"); |
| 107 | } else |
| 108 | fusb300->fifo_entry_num++; |
| 109 | } |
| 110 | |
| 111 | /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */ |
| 112 | static void fusb300_set_epaddrofs(struct fusb300 *fusb300, |
| 113 | struct fusb300_ep_info info) |
| 114 | { |
| 115 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); |
| 116 | |
| 117 | reg &= ~FUSB300_EPSET2_ADDROFS_MSK; |
| 118 | reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs); |
| 119 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); |
| 120 | fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM; |
| 121 | } |
| 122 | |
| 123 | static void ep_fifo_setting(struct fusb300 *fusb300, |
| 124 | struct fusb300_ep_info info) |
| 125 | { |
| 126 | fusb300_set_fifo_entry(fusb300, info.epnum); |
| 127 | fusb300_set_start_entry(fusb300, info.epnum); |
| 128 | fusb300_set_epaddrofs(fusb300, info); |
| 129 | } |
| 130 | |
| 131 | static void fusb300_set_eptype(struct fusb300 *fusb300, |
| 132 | struct fusb300_ep_info info) |
| 133 | { |
| 134 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 135 | |
| 136 | reg &= ~FUSB300_EPSET1_TYPE_MSK; |
| 137 | reg |= FUSB300_EPSET1_TYPE(info.type); |
| 138 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 139 | } |
| 140 | |
| 141 | static void fusb300_set_epdir(struct fusb300 *fusb300, |
| 142 | struct fusb300_ep_info info) |
| 143 | { |
| 144 | u32 reg; |
| 145 | |
| 146 | if (!info.dir_in) |
| 147 | return; |
| 148 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 149 | reg &= ~FUSB300_EPSET1_DIR_MSK; |
| 150 | reg |= FUSB300_EPSET1_DIRIN; |
| 151 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 152 | } |
| 153 | |
| 154 | static void fusb300_set_ep_active(struct fusb300 *fusb300, |
| 155 | u8 ep) |
| 156 | { |
| 157 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); |
| 158 | |
| 159 | reg |= FUSB300_EPSET1_ACTEN; |
| 160 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); |
| 161 | } |
| 162 | |
| 163 | static void fusb300_set_epmps(struct fusb300 *fusb300, |
| 164 | struct fusb300_ep_info info) |
| 165 | { |
| 166 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); |
| 167 | |
| 168 | reg &= ~FUSB300_EPSET2_MPS_MSK; |
| 169 | reg |= FUSB300_EPSET2_MPS(info.maxpacket); |
| 170 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); |
| 171 | } |
| 172 | |
| 173 | static void fusb300_set_interval(struct fusb300 *fusb300, |
| 174 | struct fusb300_ep_info info) |
| 175 | { |
| 176 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 177 | |
| 178 | reg &= ~FUSB300_EPSET1_INTERVAL(0x7); |
| 179 | reg |= FUSB300_EPSET1_INTERVAL(info.interval); |
| 180 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 181 | } |
| 182 | |
| 183 | static void fusb300_set_bwnum(struct fusb300 *fusb300, |
| 184 | struct fusb300_ep_info info) |
| 185 | { |
| 186 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 187 | |
| 188 | reg &= ~FUSB300_EPSET1_BWNUM(0x3); |
| 189 | reg |= FUSB300_EPSET1_BWNUM(info.bw_num); |
| 190 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); |
| 191 | } |
| 192 | |
| 193 | static void set_ep_reg(struct fusb300 *fusb300, |
| 194 | struct fusb300_ep_info info) |
| 195 | { |
| 196 | fusb300_set_eptype(fusb300, info); |
| 197 | fusb300_set_epdir(fusb300, info); |
| 198 | fusb300_set_epmps(fusb300, info); |
| 199 | |
| 200 | if (info.interval) |
| 201 | fusb300_set_interval(fusb300, info); |
| 202 | |
| 203 | if (info.bw_num) |
| 204 | fusb300_set_bwnum(fusb300, info); |
| 205 | |
| 206 | fusb300_set_ep_active(fusb300, info.epnum); |
| 207 | } |
| 208 | |
| 209 | static int config_ep(struct fusb300_ep *ep, |
| 210 | const struct usb_endpoint_descriptor *desc) |
| 211 | { |
| 212 | struct fusb300 *fusb300 = ep->fusb300; |
| 213 | struct fusb300_ep_info info; |
| 214 | |
| 215 | ep->desc = desc; |
| 216 | |
| 217 | info.interval = 0; |
| 218 | info.addrofs = 0; |
| 219 | info.bw_num = 0; |
| 220 | |
| 221 | info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
| 222 | info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; |
| 223 | info.maxpacket = le16_to_cpu(desc->wMaxPacketSize); |
| 224 | info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; |
| 225 | |
| 226 | if ((info.type == USB_ENDPOINT_XFER_INT) || |
| 227 | (info.type == USB_ENDPOINT_XFER_ISOC)) { |
| 228 | info.interval = desc->bInterval; |
| 229 | if (info.type == USB_ENDPOINT_XFER_ISOC) |
| 230 | info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11); |
| 231 | } |
| 232 | |
| 233 | ep_fifo_setting(fusb300, info); |
| 234 | |
| 235 | set_ep_reg(fusb300, info); |
| 236 | |
| 237 | fusb300_ep_setting(ep, info); |
| 238 | |
| 239 | fusb300->ep[info.epnum] = ep; |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static int fusb300_enable(struct usb_ep *_ep, |
| 245 | const struct usb_endpoint_descriptor *desc) |
| 246 | { |
| 247 | struct fusb300_ep *ep; |
| 248 | |
| 249 | ep = container_of(_ep, struct fusb300_ep, ep); |
| 250 | |
| 251 | if (ep->fusb300->reenum) { |
| 252 | ep->fusb300->fifo_entry_num = 0; |
| 253 | ep->fusb300->addrofs = 0; |
| 254 | ep->fusb300->reenum = 0; |
| 255 | } |
| 256 | |
| 257 | return config_ep(ep, desc); |
| 258 | } |
| 259 | |
| 260 | static int fusb300_disable(struct usb_ep *_ep) |
| 261 | { |
| 262 | struct fusb300_ep *ep; |
| 263 | struct fusb300_request *req; |
| 264 | unsigned long flags; |
| 265 | |
| 266 | ep = container_of(_ep, struct fusb300_ep, ep); |
| 267 | |
| 268 | BUG_ON(!ep); |
| 269 | |
| 270 | while (!list_empty(&ep->queue)) { |
| 271 | req = list_entry(ep->queue.next, struct fusb300_request, queue); |
| 272 | spin_lock_irqsave(&ep->fusb300->lock, flags); |
| 273 | done(ep, req, -ECONNRESET); |
| 274 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); |
| 275 | } |
| 276 | |
| 277 | return fusb300_ep_release(ep); |
| 278 | } |
| 279 | |
| 280 | static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep, |
| 281 | gfp_t gfp_flags) |
| 282 | { |
| 283 | struct fusb300_request *req; |
| 284 | |
| 285 | req = kzalloc(sizeof(struct fusb300_request), gfp_flags); |
| 286 | if (!req) |
| 287 | return NULL; |
| 288 | INIT_LIST_HEAD(&req->queue); |
| 289 | |
| 290 | return &req->req; |
| 291 | } |
| 292 | |
| 293 | static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req) |
| 294 | { |
| 295 | struct fusb300_request *req; |
| 296 | |
| 297 | req = container_of(_req, struct fusb300_request, req); |
| 298 | kfree(req); |
| 299 | } |
| 300 | |
| 301 | static int enable_fifo_int(struct fusb300_ep *ep) |
| 302 | { |
| 303 | struct fusb300 *fusb300 = ep->fusb300; |
| 304 | |
| 305 | if (ep->epnum) { |
| 306 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0, |
| 307 | FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum)); |
| 308 | } else { |
| 309 | pr_err("can't enable_fifo_int ep0\n"); |
| 310 | return -EINVAL; |
| 311 | } |
| 312 | |
| 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | static int disable_fifo_int(struct fusb300_ep *ep) |
| 317 | { |
| 318 | struct fusb300 *fusb300 = ep->fusb300; |
| 319 | |
| 320 | if (ep->epnum) { |
| 321 | fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0, |
| 322 | FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum)); |
| 323 | } else { |
| 324 | pr_err("can't disable_fifo_int ep0\n"); |
| 325 | return -EINVAL; |
| 326 | } |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length) |
| 332 | { |
| 333 | u32 reg; |
| 334 | |
| 335 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); |
| 336 | reg &= ~FUSB300_CSR_LEN_MSK; |
| 337 | reg |= FUSB300_CSR_LEN(length); |
| 338 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR); |
| 339 | } |
| 340 | |
| 341 | /* write data to cx fifo */ |
| 342 | static void fusb300_wrcxf(struct fusb300_ep *ep, |
| 343 | struct fusb300_request *req) |
| 344 | { |
| 345 | int i = 0; |
| 346 | u8 *tmp; |
| 347 | u32 data; |
| 348 | struct fusb300 *fusb300 = ep->fusb300; |
| 349 | u32 length = req->req.length - req->req.actual; |
| 350 | |
| 351 | tmp = req->req.buf + req->req.actual; |
| 352 | |
| 353 | if (length > SS_CTL_MAX_PACKET_SIZE) { |
| 354 | fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE); |
| 355 | for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) { |
| 356 | data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 | |
| 357 | *(tmp + 3) << 24; |
| 358 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 359 | tmp += 4; |
| 360 | } |
| 361 | req->req.actual += SS_CTL_MAX_PACKET_SIZE; |
| 362 | } else { /* length is less than max packet size */ |
| 363 | fusb300_set_cxlen(fusb300, length); |
| 364 | for (i = length >> 2; i > 0; i--) { |
| 365 | data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 | |
| 366 | *(tmp + 3) << 24; |
| 367 | printk(KERN_DEBUG " 0x%x\n", data); |
| 368 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 369 | tmp = tmp + 4; |
| 370 | } |
| 371 | switch (length % 4) { |
| 372 | case 1: |
| 373 | data = *tmp; |
| 374 | printk(KERN_DEBUG " 0x%x\n", data); |
| 375 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 376 | break; |
| 377 | case 2: |
| 378 | data = *tmp | *(tmp + 1) << 8; |
| 379 | printk(KERN_DEBUG " 0x%x\n", data); |
| 380 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 381 | break; |
| 382 | case 3: |
| 383 | data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16; |
| 384 | printk(KERN_DEBUG " 0x%x\n", data); |
| 385 | iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 386 | break; |
| 387 | default: |
| 388 | break; |
| 389 | } |
| 390 | req->req.actual += length; |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep) |
| 395 | { |
| 396 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep), |
| 397 | FUSB300_EPSET0_STL); |
| 398 | } |
| 399 | |
| 400 | static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep) |
| 401 | { |
| 402 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); |
| 403 | |
| 404 | if (reg & FUSB300_EPSET0_STL) { |
| 405 | printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep); |
| 406 | reg &= ~FUSB300_EPSET0_STL; |
| 407 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); |
| 408 | } |
| 409 | } |
| 410 | |
| 411 | static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req) |
| 412 | { |
| 413 | if (ep->fusb300->ep0_dir) { /* if IN */ |
| 414 | if (req->req.length) { |
| 415 | fusb300_wrcxf(ep, req); |
| 416 | } else |
| 417 | printk(KERN_DEBUG "%s : req->req.length = 0x%x\n", |
| 418 | __func__, req->req.length); |
| 419 | if ((req->req.length == req->req.actual) || |
| 420 | (req->req.actual < ep->ep.maxpacket)) |
| 421 | done(ep, req, 0); |
| 422 | } else { /* OUT */ |
| 423 | if (!req->req.length) |
| 424 | done(ep, req, 0); |
| 425 | else |
| 426 | fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1, |
| 427 | FUSB300_IGER1_CX_OUT_INT); |
| 428 | } |
| 429 | } |
| 430 | |
| 431 | static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req, |
| 432 | gfp_t gfp_flags) |
| 433 | { |
| 434 | struct fusb300_ep *ep; |
| 435 | struct fusb300_request *req; |
| 436 | unsigned long flags; |
| 437 | int request = 0; |
| 438 | |
| 439 | ep = container_of(_ep, struct fusb300_ep, ep); |
| 440 | req = container_of(_req, struct fusb300_request, req); |
| 441 | |
| 442 | if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN) |
| 443 | return -ESHUTDOWN; |
| 444 | |
| 445 | spin_lock_irqsave(&ep->fusb300->lock, flags); |
| 446 | |
| 447 | if (list_empty(&ep->queue)) |
| 448 | request = 1; |
| 449 | |
| 450 | list_add_tail(&req->queue, &ep->queue); |
| 451 | |
| 452 | req->req.actual = 0; |
| 453 | req->req.status = -EINPROGRESS; |
| 454 | |
| 455 | if (ep->desc == NULL) /* ep0 */ |
| 456 | ep0_queue(ep, req); |
| 457 | else if (request && !ep->stall) |
| 458 | enable_fifo_int(ep); |
| 459 | |
| 460 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
| 466 | { |
| 467 | struct fusb300_ep *ep; |
| 468 | struct fusb300_request *req; |
| 469 | unsigned long flags; |
| 470 | |
| 471 | ep = container_of(_ep, struct fusb300_ep, ep); |
| 472 | req = container_of(_req, struct fusb300_request, req); |
| 473 | |
| 474 | spin_lock_irqsave(&ep->fusb300->lock, flags); |
| 475 | if (!list_empty(&ep->queue)) |
| 476 | done(ep, req, -ECONNRESET); |
| 477 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); |
| 478 | |
| 479 | return 0; |
| 480 | } |
| 481 | |
| 482 | static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge) |
| 483 | { |
| 484 | struct fusb300_ep *ep; |
| 485 | struct fusb300 *fusb300; |
| 486 | unsigned long flags; |
| 487 | int ret = 0; |
| 488 | |
| 489 | ep = container_of(_ep, struct fusb300_ep, ep); |
| 490 | |
| 491 | fusb300 = ep->fusb300; |
| 492 | |
| 493 | spin_lock_irqsave(&ep->fusb300->lock, flags); |
| 494 | |
| 495 | if (!list_empty(&ep->queue)) { |
| 496 | ret = -EAGAIN; |
| 497 | goto out; |
| 498 | } |
| 499 | |
| 500 | if (value) { |
| 501 | fusb300_set_epnstall(fusb300, ep->epnum); |
| 502 | ep->stall = 1; |
| 503 | if (wedge) |
| 504 | ep->wedged = 1; |
| 505 | } else { |
| 506 | fusb300_clear_epnstall(fusb300, ep->epnum); |
| 507 | ep->stall = 0; |
| 508 | ep->wedged = 0; |
| 509 | } |
| 510 | |
| 511 | out: |
| 512 | spin_unlock_irqrestore(&ep->fusb300->lock, flags); |
| 513 | return ret; |
| 514 | } |
| 515 | |
| 516 | static int fusb300_set_halt(struct usb_ep *_ep, int value) |
| 517 | { |
| 518 | return fusb300_set_halt_and_wedge(_ep, value, 0); |
| 519 | } |
| 520 | |
| 521 | static int fusb300_set_wedge(struct usb_ep *_ep) |
| 522 | { |
| 523 | return fusb300_set_halt_and_wedge(_ep, 1, 1); |
| 524 | } |
| 525 | |
| 526 | static void fusb300_fifo_flush(struct usb_ep *_ep) |
| 527 | { |
| 528 | } |
| 529 | |
| 530 | static struct usb_ep_ops fusb300_ep_ops = { |
| 531 | .enable = fusb300_enable, |
| 532 | .disable = fusb300_disable, |
| 533 | |
| 534 | .alloc_request = fusb300_alloc_request, |
| 535 | .free_request = fusb300_free_request, |
| 536 | |
| 537 | .queue = fusb300_queue, |
| 538 | .dequeue = fusb300_dequeue, |
| 539 | |
| 540 | .set_halt = fusb300_set_halt, |
| 541 | .fifo_flush = fusb300_fifo_flush, |
| 542 | .set_wedge = fusb300_set_wedge, |
| 543 | }; |
| 544 | |
| 545 | /*****************************************************************************/ |
| 546 | static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset, |
| 547 | u32 value) |
| 548 | { |
| 549 | iowrite32(value, fusb300->reg + offset); |
| 550 | } |
| 551 | |
| 552 | static void fusb300_reset(void) |
| 553 | { |
| 554 | } |
| 555 | |
| 556 | static void fusb300_set_cxstall(struct fusb300 *fusb300) |
| 557 | { |
| 558 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR, |
| 559 | FUSB300_CSR_STL); |
| 560 | } |
| 561 | |
| 562 | static void fusb300_set_cxdone(struct fusb300 *fusb300) |
| 563 | { |
| 564 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR, |
| 565 | FUSB300_CSR_DONE); |
| 566 | } |
| 567 | |
| 568 | /* read data from cx fifo */ |
| 569 | void fusb300_rdcxf(struct fusb300 *fusb300, |
| 570 | u8 *buffer, u32 length) |
| 571 | { |
| 572 | int i = 0; |
| 573 | u8 *tmp; |
| 574 | u32 data; |
| 575 | |
| 576 | tmp = buffer; |
| 577 | |
| 578 | for (i = (length >> 2); i > 0; i--) { |
| 579 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 580 | printk(KERN_DEBUG " 0x%x\n", data); |
| 581 | *tmp = data & 0xFF; |
| 582 | *(tmp + 1) = (data >> 8) & 0xFF; |
| 583 | *(tmp + 2) = (data >> 16) & 0xFF; |
| 584 | *(tmp + 3) = (data >> 24) & 0xFF; |
| 585 | tmp = tmp + 4; |
| 586 | } |
| 587 | |
| 588 | switch (length % 4) { |
| 589 | case 1: |
| 590 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 591 | printk(KERN_DEBUG " 0x%x\n", data); |
| 592 | *tmp = data & 0xFF; |
| 593 | break; |
| 594 | case 2: |
| 595 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 596 | printk(KERN_DEBUG " 0x%x\n", data); |
| 597 | *tmp = data & 0xFF; |
| 598 | *(tmp + 1) = (data >> 8) & 0xFF; |
| 599 | break; |
| 600 | case 3: |
| 601 | data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); |
| 602 | printk(KERN_DEBUG " 0x%x\n", data); |
| 603 | *tmp = data & 0xFF; |
| 604 | *(tmp + 1) = (data >> 8) & 0xFF; |
| 605 | *(tmp + 2) = (data >> 16) & 0xFF; |
| 606 | break; |
| 607 | default: |
| 608 | break; |
| 609 | } |
| 610 | } |
| 611 | |
| 612 | #if 0 |
| 613 | static void fusb300_dbg_fifo(struct fusb300_ep *ep, |
| 614 | u8 entry, u16 length) |
| 615 | { |
| 616 | u32 reg; |
| 617 | u32 i = 0; |
| 618 | u32 j = 0; |
| 619 | |
| 620 | reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM); |
| 621 | reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) | |
| 622 | FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG); |
| 623 | reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) | |
| 624 | FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG); |
| 625 | iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM); |
| 626 | |
| 627 | for (i = 0; i < (length >> 2); i++) { |
| 628 | if (i * 4 == 1024) |
| 629 | break; |
| 630 | reg = ioread32(ep->fusb300->reg + |
| 631 | FUSB300_OFFSET_BUFDBG_START + i * 4); |
| 632 | printk(KERN_DEBUG" 0x%-8x", reg); |
| 633 | j++; |
| 634 | if ((j % 4) == 0) |
| 635 | printk(KERN_DEBUG "\n"); |
| 636 | } |
| 637 | |
| 638 | if (length % 4) { |
| 639 | reg = ioread32(ep->fusb300->reg + |
| 640 | FUSB300_OFFSET_BUFDBG_START + i * 4); |
| 641 | printk(KERN_DEBUG " 0x%x\n", reg); |
| 642 | } |
| 643 | |
| 644 | if ((j % 4) != 0) |
| 645 | printk(KERN_DEBUG "\n"); |
| 646 | |
| 647 | fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM, |
| 648 | FUSB300_GTM_TST_FIFO_DEG); |
| 649 | } |
| 650 | |
| 651 | static void fusb300_cmp_dbg_fifo(struct fusb300_ep *ep, |
| 652 | u8 entry, u16 length, u8 *golden) |
| 653 | { |
| 654 | u32 reg; |
| 655 | u32 i = 0; |
| 656 | u32 golden_value; |
| 657 | u8 *tmp; |
| 658 | |
| 659 | tmp = golden; |
| 660 | |
| 661 | printk(KERN_DEBUG "fusb300_cmp_dbg_fifo (entry %d) : start\n", entry); |
| 662 | |
| 663 | reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_GTM); |
| 664 | reg &= ~(FUSB300_GTM_TST_EP_ENTRY(0xF) | |
| 665 | FUSB300_GTM_TST_EP_NUM(0xF) | FUSB300_GTM_TST_FIFO_DEG); |
| 666 | reg |= (FUSB300_GTM_TST_EP_ENTRY(entry) | |
| 667 | FUSB300_GTM_TST_EP_NUM(ep->epnum) | FUSB300_GTM_TST_FIFO_DEG); |
| 668 | iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_GTM); |
| 669 | |
| 670 | for (i = 0; i < (length >> 2); i++) { |
| 671 | if (i * 4 == 1024) |
| 672 | break; |
| 673 | golden_value = *tmp | *(tmp + 1) << 8 | |
| 674 | *(tmp + 2) << 16 | *(tmp + 3) << 24; |
| 675 | |
| 676 | reg = ioread32(ep->fusb300->reg + |
| 677 | FUSB300_OFFSET_BUFDBG_START + i*4); |
| 678 | |
| 679 | if (reg != golden_value) { |
| 680 | printk(KERN_DEBUG "0x%x : ", (u32)(ep->fusb300->reg + |
| 681 | FUSB300_OFFSET_BUFDBG_START + i*4)); |
| 682 | printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n", |
| 683 | golden_value, reg); |
| 684 | } |
| 685 | tmp += 4; |
| 686 | } |
| 687 | |
| 688 | switch (length % 4) { |
| 689 | case 1: |
| 690 | golden_value = *tmp; |
| 691 | case 2: |
| 692 | golden_value = *tmp | *(tmp + 1) << 8; |
| 693 | case 3: |
| 694 | golden_value = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16; |
| 695 | default: |
| 696 | break; |
| 697 | |
| 698 | reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_BUFDBG_START + i*4); |
| 699 | if (reg != golden_value) { |
| 700 | printk(KERN_DEBUG "0x%x:", (u32)(ep->fusb300->reg + |
| 701 | FUSB300_OFFSET_BUFDBG_START + i*4)); |
| 702 | printk(KERN_DEBUG " golden = 0x%x, reg = 0x%x\n", |
| 703 | golden_value, reg); |
| 704 | } |
| 705 | } |
| 706 | |
| 707 | printk(KERN_DEBUG "fusb300_cmp_dbg_fifo : end\n"); |
| 708 | fusb300_disable_bit(ep->fusb300, FUSB300_OFFSET_GTM, |
| 709 | FUSB300_GTM_TST_FIFO_DEG); |
| 710 | } |
| 711 | #endif |
| 712 | |
| 713 | static void fusb300_rdfifo(struct fusb300_ep *ep, |
| 714 | struct fusb300_request *req, |
| 715 | u32 length) |
| 716 | { |
| 717 | int i = 0; |
| 718 | u8 *tmp; |
| 719 | u32 data, reg; |
| 720 | struct fusb300 *fusb300 = ep->fusb300; |
| 721 | |
| 722 | tmp = req->req.buf + req->req.actual; |
| 723 | req->req.actual += length; |
| 724 | |
| 725 | if (req->req.actual > req->req.length) |
| 726 | printk(KERN_DEBUG "req->req.actual > req->req.length\n"); |
| 727 | |
| 728 | for (i = (length >> 2); i > 0; i--) { |
| 729 | data = ioread32(fusb300->reg + |
| 730 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 731 | *tmp = data & 0xFF; |
| 732 | *(tmp + 1) = (data >> 8) & 0xFF; |
| 733 | *(tmp + 2) = (data >> 16) & 0xFF; |
| 734 | *(tmp + 3) = (data >> 24) & 0xFF; |
| 735 | tmp = tmp + 4; |
| 736 | } |
| 737 | |
| 738 | switch (length % 4) { |
| 739 | case 1: |
| 740 | data = ioread32(fusb300->reg + |
| 741 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 742 | *tmp = data & 0xFF; |
| 743 | break; |
| 744 | case 2: |
| 745 | data = ioread32(fusb300->reg + |
| 746 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 747 | *tmp = data & 0xFF; |
| 748 | *(tmp + 1) = (data >> 8) & 0xFF; |
| 749 | break; |
| 750 | case 3: |
| 751 | data = ioread32(fusb300->reg + |
| 752 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 753 | *tmp = data & 0xFF; |
| 754 | *(tmp + 1) = (data >> 8) & 0xFF; |
| 755 | *(tmp + 2) = (data >> 16) & 0xFF; |
| 756 | break; |
| 757 | default: |
| 758 | break; |
| 759 | } |
| 760 | |
| 761 | do { |
| 762 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); |
| 763 | reg &= FUSB300_IGR1_SYNF0_EMPTY_INT; |
| 764 | if (i) |
| 765 | printk(KERN_INFO "sync fifo is not empty!\n"); |
| 766 | i++; |
| 767 | } while (!reg); |
| 768 | } |
| 769 | |
| 770 | /* write data to fifo */ |
| 771 | static void fusb300_wrfifo(struct fusb300_ep *ep, |
| 772 | struct fusb300_request *req) |
| 773 | { |
| 774 | int i = 0; |
| 775 | u8 *tmp; |
| 776 | u32 data, reg; |
| 777 | struct fusb300 *fusb300 = ep->fusb300; |
| 778 | |
| 779 | tmp = req->req.buf; |
| 780 | req->req.actual = req->req.length; |
| 781 | |
| 782 | for (i = (req->req.length >> 2); i > 0; i--) { |
| 783 | data = *tmp | *(tmp + 1) << 8 | |
| 784 | *(tmp + 2) << 16 | *(tmp + 3) << 24; |
| 785 | |
| 786 | iowrite32(data, fusb300->reg + |
| 787 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 788 | tmp += 4; |
| 789 | } |
| 790 | |
| 791 | switch (req->req.length % 4) { |
| 792 | case 1: |
| 793 | data = *tmp; |
| 794 | iowrite32(data, fusb300->reg + |
| 795 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 796 | break; |
| 797 | case 2: |
| 798 | data = *tmp | *(tmp + 1) << 8; |
| 799 | iowrite32(data, fusb300->reg + |
| 800 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 801 | break; |
| 802 | case 3: |
| 803 | data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16; |
| 804 | iowrite32(data, fusb300->reg + |
| 805 | FUSB300_OFFSET_EPPORT(ep->epnum)); |
| 806 | break; |
| 807 | default: |
| 808 | break; |
| 809 | } |
| 810 | |
| 811 | do { |
| 812 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); |
| 813 | reg &= FUSB300_IGR1_SYNF0_EMPTY_INT; |
| 814 | if (i) |
| 815 | printk(KERN_INFO"sync fifo is not empty!\n"); |
| 816 | i++; |
| 817 | } while (!reg); |
| 818 | } |
| 819 | |
| 820 | static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep) |
| 821 | { |
| 822 | u8 value; |
| 823 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); |
| 824 | |
| 825 | value = reg & FUSB300_EPSET0_STL; |
| 826 | |
| 827 | return value; |
| 828 | } |
| 829 | |
| 830 | static u8 fusb300_get_cxstall(struct fusb300 *fusb300) |
| 831 | { |
| 832 | u8 value; |
| 833 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); |
| 834 | |
| 835 | value = (reg & FUSB300_CSR_STL) >> 1; |
| 836 | |
| 837 | return value; |
| 838 | } |
| 839 | |
| 840 | static void request_error(struct fusb300 *fusb300) |
| 841 | { |
| 842 | fusb300_set_cxstall(fusb300); |
| 843 | printk(KERN_DEBUG "request error!!\n"); |
| 844 | } |
| 845 | |
| 846 | static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) |
| 847 | __releases(fusb300->lock) |
| 848 | __acquires(fusb300->lock) |
| 849 | { |
| 850 | u8 ep; |
| 851 | u16 status = 0; |
| 852 | u16 w_index = ctrl->wIndex; |
| 853 | |
| 854 | switch (ctrl->bRequestType & USB_RECIP_MASK) { |
| 855 | case USB_RECIP_DEVICE: |
| 856 | status = 1 << USB_DEVICE_SELF_POWERED; |
| 857 | break; |
| 858 | case USB_RECIP_INTERFACE: |
| 859 | status = 0; |
| 860 | break; |
| 861 | case USB_RECIP_ENDPOINT: |
| 862 | ep = w_index & USB_ENDPOINT_NUMBER_MASK; |
| 863 | if (ep) { |
| 864 | if (fusb300_get_epnstall(fusb300, ep)) |
| 865 | status = 1 << USB_ENDPOINT_HALT; |
| 866 | } else { |
| 867 | if (fusb300_get_cxstall(fusb300)) |
| 868 | status = 0; |
| 869 | } |
| 870 | break; |
| 871 | |
| 872 | default: |
| 873 | request_error(fusb300); |
| 874 | return; /* exit */ |
| 875 | } |
| 876 | |
| 877 | fusb300->ep0_data = cpu_to_le16(status); |
| 878 | fusb300->ep0_req->buf = &fusb300->ep0_data; |
| 879 | fusb300->ep0_req->length = 2; |
| 880 | |
| 881 | spin_unlock(&fusb300->lock); |
| 882 | fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL); |
| 883 | spin_lock(&fusb300->lock); |
| 884 | } |
| 885 | |
| 886 | static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) |
| 887 | { |
| 888 | u8 ep; |
| 889 | |
| 890 | switch (ctrl->bRequestType & USB_RECIP_MASK) { |
| 891 | case USB_RECIP_DEVICE: |
| 892 | fusb300_set_cxdone(fusb300); |
| 893 | break; |
| 894 | case USB_RECIP_INTERFACE: |
| 895 | fusb300_set_cxdone(fusb300); |
| 896 | break; |
| 897 | case USB_RECIP_ENDPOINT: { |
| 898 | u16 w_index = le16_to_cpu(ctrl->wIndex); |
| 899 | |
| 900 | ep = w_index & USB_ENDPOINT_NUMBER_MASK; |
| 901 | if (ep) |
| 902 | fusb300_set_epnstall(fusb300, ep); |
| 903 | else |
| 904 | fusb300_set_cxstall(fusb300); |
| 905 | fusb300_set_cxdone(fusb300); |
| 906 | } |
| 907 | break; |
| 908 | default: |
| 909 | request_error(fusb300); |
| 910 | break; |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep) |
| 915 | { |
| 916 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep), |
| 917 | FUSB300_EPSET0_CLRSEQNUM); |
| 918 | } |
| 919 | |
| 920 | static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) |
| 921 | { |
| 922 | struct fusb300_ep *ep = |
| 923 | fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK]; |
| 924 | |
| 925 | switch (ctrl->bRequestType & USB_RECIP_MASK) { |
| 926 | case USB_RECIP_DEVICE: |
| 927 | fusb300_set_cxdone(fusb300); |
| 928 | break; |
| 929 | case USB_RECIP_INTERFACE: |
| 930 | fusb300_set_cxdone(fusb300); |
| 931 | break; |
| 932 | case USB_RECIP_ENDPOINT: |
| 933 | if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) { |
| 934 | if (ep->wedged) { |
| 935 | fusb300_set_cxdone(fusb300); |
| 936 | break; |
| 937 | } |
| 938 | if (ep->stall) { |
| 939 | ep->stall = 0; |
| 940 | fusb300_clear_seqnum(fusb300, ep->epnum); |
| 941 | fusb300_clear_epnstall(fusb300, ep->epnum); |
| 942 | if (!list_empty(&ep->queue)) |
| 943 | enable_fifo_int(ep); |
| 944 | } |
| 945 | } |
| 946 | fusb300_set_cxdone(fusb300); |
| 947 | break; |
| 948 | default: |
| 949 | request_error(fusb300); |
| 950 | break; |
| 951 | } |
| 952 | } |
| 953 | |
| 954 | static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr) |
| 955 | { |
| 956 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR); |
| 957 | |
| 958 | reg &= ~FUSB300_DAR_DRVADDR_MSK; |
| 959 | reg |= FUSB300_DAR_DRVADDR(addr); |
| 960 | |
| 961 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR); |
| 962 | } |
| 963 | |
| 964 | static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) |
| 965 | { |
| 966 | if (ctrl->wValue >= 0x0100) |
| 967 | request_error(fusb300); |
| 968 | else { |
| 969 | fusb300_set_dev_addr(fusb300, ctrl->wValue); |
| 970 | fusb300_set_cxdone(fusb300); |
| 971 | } |
| 972 | } |
| 973 | |
| 974 | #define UVC_COPY_DESCRIPTORS(mem, src) \ |
| 975 | do { \ |
| 976 | const struct usb_descriptor_header * const *__src; \ |
| 977 | for (__src = src; *__src; ++__src) { \ |
| 978 | memcpy(mem, *__src, (*__src)->bLength); \ |
| 979 | mem += (*__src)->bLength; \ |
| 980 | } \ |
| 981 | } while (0) |
| 982 | |
| 983 | static void fusb300_ep0_complete(struct usb_ep *ep, |
| 984 | struct usb_request *req) |
| 985 | { |
| 986 | } |
| 987 | |
| 988 | static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl) |
| 989 | { |
| 990 | u8 *p = (u8 *)ctrl; |
| 991 | u8 ret = 0; |
| 992 | u8 i = 0; |
| 993 | |
| 994 | fusb300_rdcxf(fusb300, p, 8); |
| 995 | fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN; |
| 996 | fusb300->ep0_length = ctrl->wLength; |
| 997 | |
| 998 | /* check request */ |
| 999 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { |
| 1000 | switch (ctrl->bRequest) { |
| 1001 | case USB_REQ_GET_STATUS: |
| 1002 | get_status(fusb300, ctrl); |
| 1003 | break; |
| 1004 | case USB_REQ_CLEAR_FEATURE: |
| 1005 | clear_feature(fusb300, ctrl); |
| 1006 | break; |
| 1007 | case USB_REQ_SET_FEATURE: |
| 1008 | set_feature(fusb300, ctrl); |
| 1009 | break; |
| 1010 | case USB_REQ_SET_ADDRESS: |
| 1011 | set_address(fusb300, ctrl); |
| 1012 | break; |
| 1013 | case USB_REQ_SET_CONFIGURATION: |
| 1014 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR, |
| 1015 | FUSB300_DAR_SETCONFG); |
| 1016 | /* clear sequence number */ |
| 1017 | for (i = 1; i <= FUSB300_MAX_NUM_EP; i++) |
| 1018 | fusb300_clear_seqnum(fusb300, i); |
| 1019 | fusb300->reenum = 1; |
| 1020 | ret = 1; |
| 1021 | break; |
| 1022 | default: |
| 1023 | ret = 1; |
| 1024 | break; |
| 1025 | } |
| 1026 | } else |
| 1027 | ret = 1; |
| 1028 | |
| 1029 | return ret; |
| 1030 | } |
| 1031 | |
| 1032 | static void fusb300_set_ep_bycnt(struct fusb300_ep *ep, u32 bycnt) |
| 1033 | { |
| 1034 | struct fusb300 *fusb300 = ep->fusb300; |
| 1035 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum)); |
| 1036 | |
| 1037 | reg &= ~FUSB300_FFR_BYCNT; |
| 1038 | reg |= bycnt & FUSB300_FFR_BYCNT; |
| 1039 | |
| 1040 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum)); |
| 1041 | } |
| 1042 | |
| 1043 | static void done(struct fusb300_ep *ep, struct fusb300_request *req, |
| 1044 | int status) |
| 1045 | { |
| 1046 | list_del_init(&req->queue); |
| 1047 | |
| 1048 | /* don't modify queue heads during completion callback */ |
| 1049 | if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN) |
| 1050 | req->req.status = -ESHUTDOWN; |
| 1051 | else |
| 1052 | req->req.status = status; |
| 1053 | |
| 1054 | spin_unlock(&ep->fusb300->lock); |
| 1055 | req->req.complete(&ep->ep, &req->req); |
| 1056 | spin_lock(&ep->fusb300->lock); |
| 1057 | |
| 1058 | if (ep->epnum) { |
| 1059 | disable_fifo_int(ep); |
| 1060 | if (!list_empty(&ep->queue)) |
| 1061 | enable_fifo_int(ep); |
| 1062 | } else |
| 1063 | fusb300_set_cxdone(ep->fusb300); |
| 1064 | } |
| 1065 | |
| 1066 | void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, |
| 1067 | struct fusb300_request *req) |
| 1068 | { |
| 1069 | u32 value; |
| 1070 | u32 reg; |
| 1071 | |
| 1072 | /* wait SW owner */ |
| 1073 | do { |
| 1074 | reg = ioread32(ep->fusb300->reg + |
| 1075 | FUSB300_OFFSET_EPPRD_W0(ep->epnum)); |
| 1076 | reg &= FUSB300_EPPRD0_H; |
| 1077 | } while (reg); |
| 1078 | |
| 1079 | iowrite32((u32) req->req.buf, ep->fusb300->reg + |
| 1080 | FUSB300_OFFSET_EPPRD_W1(ep->epnum)); |
| 1081 | |
| 1082 | value = FUSB300_EPPRD0_BTC(req->req.length) | FUSB300_EPPRD0_H | |
| 1083 | FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I; |
| 1084 | iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum)); |
| 1085 | |
| 1086 | iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum)); |
| 1087 | |
| 1088 | fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY, |
| 1089 | FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum)); |
| 1090 | } |
| 1091 | |
| 1092 | static void fusb300_wait_idma_finished(struct fusb300_ep *ep) |
| 1093 | { |
| 1094 | u32 reg; |
| 1095 | |
| 1096 | do { |
| 1097 | reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1); |
| 1098 | if ((reg & FUSB300_IGR1_VBUS_CHG_INT) || |
| 1099 | (reg & FUSB300_IGR1_WARM_RST_INT) || |
| 1100 | (reg & FUSB300_IGR1_HOT_RST_INT) || |
| 1101 | (reg & FUSB300_IGR1_USBRST_INT) |
| 1102 | ) |
| 1103 | goto IDMA_RESET; |
| 1104 | reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0); |
| 1105 | reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum); |
| 1106 | } while (!reg); |
| 1107 | |
| 1108 | fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0, |
| 1109 | FUSB300_IGR0_EPn_PRD_INT(ep->epnum)); |
| 1110 | IDMA_RESET: |
| 1111 | fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGER0, |
| 1112 | FUSB300_IGER0_EEPn_PRD_INT(ep->epnum)); |
| 1113 | } |
| 1114 | |
| 1115 | static void fusb300_set_idma(struct fusb300_ep *ep, |
| 1116 | struct fusb300_request *req) |
| 1117 | { |
| 1118 | dma_addr_t d; |
| 1119 | u8 *tmp = NULL; |
| 1120 | |
| 1121 | d = dma_map_single(NULL, req->req.buf, req->req.length, DMA_TO_DEVICE); |
| 1122 | |
| 1123 | if (dma_mapping_error(NULL, d)) { |
| 1124 | kfree(req->req.buf); |
| 1125 | printk(KERN_DEBUG "dma_mapping_error\n"); |
| 1126 | } |
| 1127 | |
| 1128 | dma_sync_single_for_device(NULL, d, req->req.length, DMA_TO_DEVICE); |
| 1129 | |
| 1130 | fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0, |
| 1131 | FUSB300_IGER0_EEPn_PRD_INT(ep->epnum)); |
| 1132 | |
| 1133 | tmp = req->req.buf; |
| 1134 | req->req.buf = (u8 *)d; |
| 1135 | |
| 1136 | fusb300_fill_idma_prdtbl(ep, req); |
| 1137 | /* check idma is done */ |
| 1138 | fusb300_wait_idma_finished(ep); |
| 1139 | |
| 1140 | req->req.buf = tmp; |
| 1141 | |
| 1142 | if (d) |
| 1143 | dma_unmap_single(NULL, d, req->req.length, DMA_TO_DEVICE); |
| 1144 | } |
| 1145 | |
| 1146 | static void in_ep_fifo_handler(struct fusb300_ep *ep) |
| 1147 | { |
| 1148 | struct fusb300_request *req = list_entry(ep->queue.next, |
| 1149 | struct fusb300_request, queue); |
| 1150 | |
| 1151 | if (req->req.length) { |
| 1152 | #if 0 |
| 1153 | fusb300_set_ep_bycnt(ep, req->req.length); |
| 1154 | fusb300_wrfifo(ep, req); |
| 1155 | #else |
| 1156 | fusb300_set_idma(ep, req); |
| 1157 | #endif |
| 1158 | } |
| 1159 | done(ep, req, 0); |
| 1160 | } |
| 1161 | |
| 1162 | static void out_ep_fifo_handler(struct fusb300_ep *ep) |
| 1163 | { |
| 1164 | struct fusb300 *fusb300 = ep->fusb300; |
| 1165 | struct fusb300_request *req = list_entry(ep->queue.next, |
| 1166 | struct fusb300_request, queue); |
| 1167 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum)); |
| 1168 | u32 length = reg & FUSB300_FFR_BYCNT; |
| 1169 | |
| 1170 | fusb300_rdfifo(ep, req, length); |
| 1171 | |
| 1172 | /* finish out transfer */ |
| 1173 | if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket)) |
| 1174 | done(ep, req, 0); |
| 1175 | } |
| 1176 | |
| 1177 | static void check_device_mode(struct fusb300 *fusb300) |
| 1178 | { |
| 1179 | u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR); |
| 1180 | |
| 1181 | switch (reg & FUSB300_GCR_DEVEN_MSK) { |
| 1182 | case FUSB300_GCR_DEVEN_SS: |
| 1183 | fusb300->gadget.speed = USB_SPEED_SUPER; |
| 1184 | break; |
| 1185 | case FUSB300_GCR_DEVEN_HS: |
| 1186 | fusb300->gadget.speed = USB_SPEED_HIGH; |
| 1187 | break; |
| 1188 | case FUSB300_GCR_DEVEN_FS: |
| 1189 | fusb300->gadget.speed = USB_SPEED_FULL; |
| 1190 | break; |
| 1191 | default: |
| 1192 | fusb300->gadget.speed = USB_SPEED_UNKNOWN; |
| 1193 | break; |
| 1194 | } |
| 1195 | printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK)); |
| 1196 | } |
| 1197 | |
| 1198 | |
| 1199 | static void fusb300_ep0out(struct fusb300 *fusb300) |
| 1200 | { |
| 1201 | struct fusb300_ep *ep = fusb300->ep[0]; |
| 1202 | u32 reg; |
| 1203 | |
| 1204 | if (!list_empty(&ep->queue)) { |
| 1205 | struct fusb300_request *req; |
| 1206 | |
| 1207 | req = list_first_entry(&ep->queue, |
| 1208 | struct fusb300_request, queue); |
| 1209 | if (req->req.length) |
| 1210 | fusb300_rdcxf(ep->fusb300, req->req.buf, |
| 1211 | req->req.length); |
| 1212 | done(ep, req, 0); |
| 1213 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); |
| 1214 | reg &= ~FUSB300_IGER1_CX_OUT_INT; |
| 1215 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1); |
| 1216 | } else |
| 1217 | pr_err("%s : empty queue\n", __func__); |
| 1218 | } |
| 1219 | |
| 1220 | static void fusb300_ep0in(struct fusb300 *fusb300) |
| 1221 | { |
| 1222 | struct fusb300_request *req; |
| 1223 | struct fusb300_ep *ep = fusb300->ep[0]; |
| 1224 | |
| 1225 | if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) { |
| 1226 | req = list_entry(ep->queue.next, |
| 1227 | struct fusb300_request, queue); |
| 1228 | if (req->req.length) |
| 1229 | fusb300_wrcxf(ep, req); |
| 1230 | if ((req->req.length - req->req.actual) < ep->ep.maxpacket) |
| 1231 | done(ep, req, 0); |
| 1232 | } else |
| 1233 | fusb300_set_cxdone(fusb300); |
| 1234 | } |
| 1235 | |
| 1236 | static void fusb300_grp2_handler(void) |
| 1237 | { |
| 1238 | } |
| 1239 | |
| 1240 | static void fusb300_grp3_handler(void) |
| 1241 | { |
| 1242 | } |
| 1243 | |
| 1244 | static void fusb300_grp4_handler(void) |
| 1245 | { |
| 1246 | } |
| 1247 | |
| 1248 | static void fusb300_grp5_handler(void) |
| 1249 | { |
| 1250 | } |
| 1251 | |
| 1252 | static irqreturn_t fusb300_irq(int irq, void *_fusb300) |
| 1253 | { |
| 1254 | struct fusb300 *fusb300 = _fusb300; |
| 1255 | u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); |
| 1256 | u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); |
| 1257 | u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0); |
| 1258 | u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0); |
| 1259 | struct usb_ctrlrequest ctrl; |
| 1260 | u8 in; |
| 1261 | u32 reg; |
| 1262 | int i; |
| 1263 | |
| 1264 | spin_lock(&fusb300->lock); |
| 1265 | |
| 1266 | int_grp1 &= int_grp1_en; |
| 1267 | int_grp0 &= int_grp0_en; |
| 1268 | |
| 1269 | if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) { |
| 1270 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1271 | FUSB300_IGR1_WARM_RST_INT); |
| 1272 | printk(KERN_INFO"fusb300_warmreset\n"); |
| 1273 | fusb300_reset(); |
| 1274 | } |
| 1275 | |
| 1276 | if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) { |
| 1277 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1278 | FUSB300_IGR1_HOT_RST_INT); |
| 1279 | printk(KERN_INFO"fusb300_hotreset\n"); |
| 1280 | fusb300_reset(); |
| 1281 | } |
| 1282 | |
| 1283 | if (int_grp1 & FUSB300_IGR1_USBRST_INT) { |
| 1284 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1285 | FUSB300_IGR1_USBRST_INT); |
| 1286 | fusb300_reset(); |
| 1287 | } |
| 1288 | /* COMABT_INT has a highest priority */ |
| 1289 | |
| 1290 | if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) { |
| 1291 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1292 | FUSB300_IGR1_CX_COMABT_INT); |
| 1293 | printk(KERN_INFO"fusb300_ep0abt\n"); |
| 1294 | } |
| 1295 | |
| 1296 | if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) { |
| 1297 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1298 | FUSB300_IGR1_VBUS_CHG_INT); |
| 1299 | printk(KERN_INFO"fusb300_vbus_change\n"); |
| 1300 | } |
| 1301 | |
| 1302 | if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) { |
| 1303 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1304 | FUSB300_IGR1_U3_EXIT_FAIL_INT); |
| 1305 | } |
| 1306 | |
| 1307 | if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) { |
| 1308 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1309 | FUSB300_IGR1_U2_EXIT_FAIL_INT); |
| 1310 | } |
| 1311 | |
| 1312 | if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) { |
| 1313 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1314 | FUSB300_IGR1_U1_EXIT_FAIL_INT); |
| 1315 | } |
| 1316 | |
| 1317 | if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) { |
| 1318 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1319 | FUSB300_IGR1_U2_ENTRY_FAIL_INT); |
| 1320 | } |
| 1321 | |
| 1322 | if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) { |
| 1323 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1324 | FUSB300_IGR1_U1_ENTRY_FAIL_INT); |
| 1325 | } |
| 1326 | |
| 1327 | if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) { |
| 1328 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1329 | FUSB300_IGR1_U3_EXIT_INT); |
| 1330 | printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n"); |
| 1331 | } |
| 1332 | |
| 1333 | if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) { |
| 1334 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1335 | FUSB300_IGR1_U2_EXIT_INT); |
| 1336 | printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n"); |
| 1337 | } |
| 1338 | |
| 1339 | if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) { |
| 1340 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1341 | FUSB300_IGR1_U1_EXIT_INT); |
| 1342 | printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n"); |
| 1343 | } |
| 1344 | |
| 1345 | if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) { |
| 1346 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1347 | FUSB300_IGR1_U3_ENTRY_INT); |
| 1348 | printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n"); |
| 1349 | fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1, |
| 1350 | FUSB300_SSCR1_GO_U3_DONE); |
| 1351 | } |
| 1352 | |
| 1353 | if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) { |
| 1354 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1355 | FUSB300_IGR1_U2_ENTRY_INT); |
| 1356 | printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n"); |
| 1357 | } |
| 1358 | |
| 1359 | if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) { |
| 1360 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1361 | FUSB300_IGR1_U1_ENTRY_INT); |
| 1362 | printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n"); |
| 1363 | } |
| 1364 | |
| 1365 | if (int_grp1 & FUSB300_IGR1_RESM_INT) { |
| 1366 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1367 | FUSB300_IGR1_RESM_INT); |
| 1368 | printk(KERN_INFO "fusb300_resume\n"); |
| 1369 | } |
| 1370 | |
| 1371 | if (int_grp1 & FUSB300_IGR1_SUSP_INT) { |
| 1372 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1373 | FUSB300_IGR1_SUSP_INT); |
| 1374 | printk(KERN_INFO "fusb300_suspend\n"); |
| 1375 | } |
| 1376 | |
| 1377 | if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) { |
| 1378 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1379 | FUSB300_IGR1_HS_LPM_INT); |
| 1380 | printk(KERN_INFO "fusb300_HS_LPM_INT\n"); |
| 1381 | } |
| 1382 | |
| 1383 | if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) { |
| 1384 | fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1, |
| 1385 | FUSB300_IGR1_DEV_MODE_CHG_INT); |
| 1386 | check_device_mode(fusb300); |
| 1387 | } |
| 1388 | |
| 1389 | if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) { |
| 1390 | fusb300_set_cxstall(fusb300); |
| 1391 | printk(KERN_INFO "fusb300_ep0fail\n"); |
| 1392 | } |
| 1393 | |
| 1394 | if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) { |
| 1395 | printk(KERN_INFO "fusb300_ep0setup\n"); |
| 1396 | if (setup_packet(fusb300, &ctrl)) { |
| 1397 | spin_unlock(&fusb300->lock); |
| 1398 | if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0) |
| 1399 | fusb300_set_cxstall(fusb300); |
| 1400 | spin_lock(&fusb300->lock); |
| 1401 | } |
| 1402 | } |
| 1403 | |
| 1404 | if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT) |
| 1405 | printk(KERN_INFO "fusb300_cmdend\n"); |
| 1406 | |
| 1407 | |
| 1408 | if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) { |
| 1409 | printk(KERN_INFO "fusb300_cxout\n"); |
| 1410 | fusb300_ep0out(fusb300); |
| 1411 | } |
| 1412 | |
| 1413 | if (int_grp1 & FUSB300_IGR1_CX_IN_INT) { |
| 1414 | printk(KERN_INFO "fusb300_cxin\n"); |
| 1415 | fusb300_ep0in(fusb300); |
| 1416 | } |
| 1417 | |
| 1418 | if (int_grp1 & FUSB300_IGR1_INTGRP5) |
| 1419 | fusb300_grp5_handler(); |
| 1420 | |
| 1421 | if (int_grp1 & FUSB300_IGR1_INTGRP4) |
| 1422 | fusb300_grp4_handler(); |
| 1423 | |
| 1424 | if (int_grp1 & FUSB300_IGR1_INTGRP3) |
| 1425 | fusb300_grp3_handler(); |
| 1426 | |
| 1427 | if (int_grp1 & FUSB300_IGR1_INTGRP2) |
| 1428 | fusb300_grp2_handler(); |
| 1429 | |
| 1430 | if (int_grp0) { |
| 1431 | for (i = 1; i < FUSB300_MAX_NUM_EP; i++) { |
| 1432 | if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) { |
| 1433 | reg = ioread32(fusb300->reg + |
| 1434 | FUSB300_OFFSET_EPSET1(i)); |
| 1435 | in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0; |
| 1436 | if (in) |
| 1437 | in_ep_fifo_handler(fusb300->ep[i]); |
| 1438 | else |
| 1439 | out_ep_fifo_handler(fusb300->ep[i]); |
| 1440 | } |
| 1441 | } |
| 1442 | } |
| 1443 | |
| 1444 | spin_unlock(&fusb300->lock); |
| 1445 | |
| 1446 | return IRQ_HANDLED; |
| 1447 | } |
| 1448 | |
| 1449 | static void fusb300_set_u2_timeout(struct fusb300 *fusb300, |
| 1450 | u32 time) |
| 1451 | { |
| 1452 | u32 reg; |
| 1453 | |
| 1454 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); |
| 1455 | reg &= ~0xff; |
| 1456 | reg |= FUSB300_SSCR2_U2TIMEOUT(time); |
| 1457 | |
| 1458 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); |
| 1459 | } |
| 1460 | |
| 1461 | static void fusb300_set_u1_timeout(struct fusb300 *fusb300, |
| 1462 | u32 time) |
| 1463 | { |
| 1464 | u32 reg; |
| 1465 | |
| 1466 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); |
| 1467 | reg &= ~(0xff << 8); |
| 1468 | reg |= FUSB300_SSCR2_U1TIMEOUT(time); |
| 1469 | |
| 1470 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); |
| 1471 | } |
| 1472 | |
| 1473 | static void init_controller(struct fusb300 *fusb300) |
| 1474 | { |
| 1475 | u32 reg; |
| 1476 | u32 mask = 0; |
| 1477 | u32 val = 0; |
| 1478 | |
| 1479 | /* split on */ |
| 1480 | mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON; |
| 1481 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR); |
| 1482 | reg &= ~mask; |
| 1483 | reg |= val; |
| 1484 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR); |
| 1485 | |
| 1486 | /* enable high-speed LPM */ |
| 1487 | mask = val = FUSB300_HSCR_HS_LPM_PERMIT; |
| 1488 | reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR); |
| 1489 | reg &= ~mask; |
| 1490 | reg |= val; |
| 1491 | iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR); |
| 1492 | |
| 1493 | /*set u1 u2 timmer*/ |
| 1494 | fusb300_set_u2_timeout(fusb300, 0xff); |
| 1495 | fusb300_set_u1_timeout(fusb300, 0xff); |
| 1496 | |
| 1497 | /* enable all grp1 interrupt */ |
| 1498 | iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1); |
| 1499 | } |
| 1500 | /*------------------------------------------------------------------------*/ |
| 1501 | static struct fusb300 *the_controller; |
| 1502 | |
| 1503 | int usb_gadget_probe_driver(struct usb_gadget_driver *driver, |
| 1504 | int (*bind)(struct usb_gadget *)) |
| 1505 | { |
| 1506 | struct fusb300 *fusb300 = the_controller; |
| 1507 | int retval; |
| 1508 | |
| 1509 | if (!driver |
| 1510 | || driver->speed < USB_SPEED_FULL |
| 1511 | || !bind |
| 1512 | || !driver->setup) |
| 1513 | return -EINVAL; |
| 1514 | |
| 1515 | if (!fusb300) |
| 1516 | return -ENODEV; |
| 1517 | |
| 1518 | if (fusb300->driver) |
| 1519 | return -EBUSY; |
| 1520 | |
| 1521 | /* hook up the driver */ |
| 1522 | driver->driver.bus = NULL; |
| 1523 | fusb300->driver = driver; |
| 1524 | fusb300->gadget.dev.driver = &driver->driver; |
| 1525 | |
| 1526 | retval = device_add(&fusb300->gadget.dev); |
| 1527 | if (retval) { |
| 1528 | pr_err("device_add error (%d)\n", retval); |
| 1529 | goto error; |
| 1530 | } |
| 1531 | |
| 1532 | retval = bind(&fusb300->gadget); |
| 1533 | if (retval) { |
| 1534 | pr_err("bind to driver error (%d)\n", retval); |
| 1535 | device_del(&fusb300->gadget.dev); |
| 1536 | goto error; |
| 1537 | } |
| 1538 | |
| 1539 | return 0; |
| 1540 | |
| 1541 | error: |
| 1542 | fusb300->driver = NULL; |
| 1543 | fusb300->gadget.dev.driver = NULL; |
| 1544 | |
| 1545 | return retval; |
| 1546 | } |
| 1547 | EXPORT_SYMBOL(usb_gadget_probe_driver); |
| 1548 | |
| 1549 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
| 1550 | { |
| 1551 | struct fusb300 *fusb300 = the_controller; |
| 1552 | |
| 1553 | if (driver != fusb300->driver || !driver->unbind) |
| 1554 | return -EINVAL; |
| 1555 | |
| 1556 | driver->unbind(&fusb300->gadget); |
| 1557 | fusb300->gadget.dev.driver = NULL; |
| 1558 | |
| 1559 | init_controller(fusb300); |
| 1560 | device_del(&fusb300->gadget.dev); |
| 1561 | fusb300->driver = NULL; |
| 1562 | |
| 1563 | return 0; |
| 1564 | } |
| 1565 | EXPORT_SYMBOL(usb_gadget_unregister_driver); |
| 1566 | /*--------------------------------------------------------------------------*/ |
| 1567 | |
| 1568 | static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active) |
| 1569 | { |
| 1570 | return 0; |
| 1571 | } |
| 1572 | |
| 1573 | static struct usb_gadget_ops fusb300_gadget_ops = { |
| 1574 | .pullup = fusb300_udc_pullup, |
| 1575 | }; |
| 1576 | |
| 1577 | static int __exit fusb300_remove(struct platform_device *pdev) |
| 1578 | { |
| 1579 | struct fusb300 *fusb300 = dev_get_drvdata(&pdev->dev); |
| 1580 | |
| 1581 | iounmap(fusb300->reg); |
| 1582 | free_irq(platform_get_irq(pdev, 0), fusb300); |
| 1583 | |
| 1584 | fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req); |
| 1585 | kfree(fusb300); |
| 1586 | |
| 1587 | return 0; |
| 1588 | } |
| 1589 | |
| 1590 | static int __init fusb300_probe(struct platform_device *pdev) |
| 1591 | { |
| 1592 | struct resource *res, *ires, *ires1; |
| 1593 | void __iomem *reg = NULL; |
| 1594 | struct fusb300 *fusb300 = NULL; |
| 1595 | struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP]; |
| 1596 | int ret = 0; |
| 1597 | int i; |
| 1598 | |
| 1599 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1600 | if (!res) { |
| 1601 | ret = -ENODEV; |
| 1602 | pr_err("platform_get_resource error.\n"); |
| 1603 | goto clean_up; |
| 1604 | } |
| 1605 | |
| 1606 | ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 1607 | if (!ires) { |
| 1608 | ret = -ENODEV; |
| 1609 | dev_err(&pdev->dev, |
| 1610 | "platform_get_resource IORESOURCE_IRQ error.\n"); |
| 1611 | goto clean_up; |
| 1612 | } |
| 1613 | |
| 1614 | ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
| 1615 | if (!ires1) { |
| 1616 | ret = -ENODEV; |
| 1617 | dev_err(&pdev->dev, |
| 1618 | "platform_get_resource IORESOURCE_IRQ 1 error.\n"); |
| 1619 | goto clean_up; |
| 1620 | } |
| 1621 | |
| 1622 | reg = ioremap(res->start, resource_size(res)); |
| 1623 | if (reg == NULL) { |
| 1624 | ret = -ENOMEM; |
| 1625 | pr_err("ioremap error.\n"); |
| 1626 | goto clean_up; |
| 1627 | } |
| 1628 | |
| 1629 | /* initialize udc */ |
| 1630 | fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL); |
| 1631 | if (fusb300 == NULL) { |
| 1632 | pr_err("kzalloc error\n"); |
| 1633 | goto clean_up; |
| 1634 | } |
| 1635 | |
| 1636 | for (i = 0; i < FUSB300_MAX_NUM_EP; i++) { |
| 1637 | _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL); |
| 1638 | if (_ep[i] == NULL) { |
| 1639 | pr_err("_ep kzalloc error\n"); |
| 1640 | goto clean_up; |
| 1641 | } |
| 1642 | fusb300->ep[i] = _ep[i]; |
| 1643 | } |
| 1644 | |
| 1645 | spin_lock_init(&fusb300->lock); |
| 1646 | |
| 1647 | dev_set_drvdata(&pdev->dev, fusb300); |
| 1648 | |
| 1649 | fusb300->gadget.ops = &fusb300_gadget_ops; |
| 1650 | |
| 1651 | device_initialize(&fusb300->gadget.dev); |
| 1652 | |
| 1653 | dev_set_name(&fusb300->gadget.dev, "gadget"); |
| 1654 | |
| 1655 | fusb300->gadget.is_dualspeed = 1; |
| 1656 | fusb300->gadget.dev.parent = &pdev->dev; |
| 1657 | fusb300->gadget.dev.dma_mask = pdev->dev.dma_mask; |
| 1658 | fusb300->gadget.dev.release = pdev->dev.release; |
| 1659 | fusb300->gadget.name = udc_name; |
| 1660 | fusb300->reg = reg; |
| 1661 | |
| 1662 | ret = request_irq(ires->start, fusb300_irq, IRQF_DISABLED | IRQF_SHARED, |
| 1663 | udc_name, fusb300); |
| 1664 | if (ret < 0) { |
| 1665 | pr_err("request_irq error (%d)\n", ret); |
| 1666 | goto clean_up; |
| 1667 | } |
| 1668 | |
| 1669 | ret = request_irq(ires1->start, fusb300_irq, |
| 1670 | IRQF_DISABLED | IRQF_SHARED, udc_name, fusb300); |
| 1671 | if (ret < 0) { |
| 1672 | pr_err("request_irq1 error (%d)\n", ret); |
| 1673 | goto clean_up; |
| 1674 | } |
| 1675 | |
| 1676 | INIT_LIST_HEAD(&fusb300->gadget.ep_list); |
| 1677 | |
| 1678 | for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) { |
| 1679 | struct fusb300_ep *ep = fusb300->ep[i]; |
| 1680 | |
| 1681 | if (i != 0) { |
| 1682 | INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list); |
| 1683 | list_add_tail(&fusb300->ep[i]->ep.ep_list, |
| 1684 | &fusb300->gadget.ep_list); |
| 1685 | } |
| 1686 | ep->fusb300 = fusb300; |
| 1687 | INIT_LIST_HEAD(&ep->queue); |
| 1688 | ep->ep.name = fusb300_ep_name[i]; |
| 1689 | ep->ep.ops = &fusb300_ep_ops; |
| 1690 | ep->ep.maxpacket = HS_BULK_MAX_PACKET_SIZE; |
| 1691 | } |
| 1692 | fusb300->ep[0]->ep.maxpacket = HS_CTL_MAX_PACKET_SIZE; |
| 1693 | fusb300->ep[0]->epnum = 0; |
| 1694 | fusb300->gadget.ep0 = &fusb300->ep[0]->ep; |
| 1695 | INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list); |
| 1696 | |
| 1697 | the_controller = fusb300; |
| 1698 | |
| 1699 | fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep, |
| 1700 | GFP_KERNEL); |
| 1701 | if (fusb300->ep0_req == NULL) |
| 1702 | goto clean_up3; |
| 1703 | |
| 1704 | init_controller(fusb300); |
| 1705 | dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION); |
| 1706 | |
| 1707 | return 0; |
| 1708 | |
| 1709 | clean_up3: |
| 1710 | free_irq(ires->start, fusb300); |
| 1711 | |
| 1712 | clean_up: |
| 1713 | if (fusb300) { |
| 1714 | if (fusb300->ep0_req) |
| 1715 | fusb300_free_request(&fusb300->ep[0]->ep, |
| 1716 | fusb300->ep0_req); |
| 1717 | kfree(fusb300); |
| 1718 | } |
| 1719 | if (reg) |
| 1720 | iounmap(reg); |
| 1721 | |
| 1722 | return ret; |
| 1723 | } |
| 1724 | |
| 1725 | static struct platform_driver fusb300_driver = { |
| 1726 | .remove = __exit_p(fusb300_remove), |
| 1727 | .driver = { |
| 1728 | .name = (char *) udc_name, |
| 1729 | .owner = THIS_MODULE, |
| 1730 | }, |
| 1731 | }; |
| 1732 | |
| 1733 | static int __init fusb300_udc_init(void) |
| 1734 | { |
| 1735 | return platform_driver_probe(&fusb300_driver, fusb300_probe); |
| 1736 | } |
| 1737 | |
| 1738 | module_init(fusb300_udc_init); |
| 1739 | |
| 1740 | static void __exit fusb300_udc_cleanup(void) |
| 1741 | { |
| 1742 | platform_driver_unregister(&fusb300_driver); |
| 1743 | } |
| 1744 | module_exit(fusb300_udc_cleanup); |