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gerrit-public.fairphone.software / kernel / msm-4.9 / 140a23e0dfec6ddf09d3426b288e2653251f666d / . / arch / arm / boot / dts / qcom / sdxpoorwills-coresight.dtsi
blob: eb5c21031e9a73032394c333f197f3f12ac94a9f [file] [log] [blame]
Mao Jinlong9c7f4182018-01-11 20:48:58 +0800[diff] [blame]1/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
14 csr: csr@6001000 {
15 compatible = "qcom,coresight-csr";
16 reg = <0x6001000 0x1000>;
17 reg-names = "csr-base";
18
19 coresight-name = "coresight-csr";
muluhe54427642018-02-06 20:14:40 +0800[diff] [blame]20 qcom,usb-bam-support;
21 qcom,hwctrl-set-support;
22 qcom,set-byte-cntr-support;
23
24 qcom,blk-size = <1>;
25 };
26
27 swao_csr: csr@6b0e000 {
28 compatible = "qcom,coresight-csr";
29 reg = <0x6b0e000 0x1000>;
30 reg-names = "csr-base";
31
32 clocks = <&clock_aop QDSS_CLK>;
33 clock-names = "apb_pclk";
34
35 coresight-name = "coresight-swao-csr";
36 qcom,timestamp-support;
Mao Jinlong9c7f4182018-01-11 20:48:58 +0800[diff] [blame]37
38 qcom,blk-size = <1>;
39 };
40
41 tmc_etr: tmc@6048000 {
42 compatible = "arm,primecell";
43 arm,primecell-periphid = <0x0003b961>;
44
45 reg = <0x6048000 0x1000>,
46 <0x6064000 0x15000>;
47 reg-names = "tmc-base", "bam-base";
48
49 arm,buffer-size = <0x400000>;
50 arm,sg-enable;
51
52 coresight-name = "coresight-tmc-etr";
53 coresight-ctis = <&cti0 &cti8>;
muluhe54427642018-02-06 20:14:40 +0800[diff] [blame]54 coresight-csr = <&csr>;
Mao Jinlong9c7f4182018-01-11 20:48:58 +0800[diff] [blame]55
56 clocks = <&clock_aop QDSS_CLK>;
57 clock-names = "apb_pclk";
58
59 interrupts = <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>;
60 interrupt-names = "byte-cntr-irq";
61
62 port {
63 tmc_etr_in_replicator: endpoint {
64 slave-mode;
65 remote-endpoint = <&replicator_out_tmc_etr>;
66 };
67 };
68 };
69
70 replicator_qdss: replicator@6046000 {
71 compatible = "arm,primecell";
72 arm,primecell-periphid = <0x0003b909>;
73
74 reg = <0x6046000 0x1000>;
75 reg-names = "replicator-base";
76
77 coresight-name = "coresight-replicator";
78
79 clocks = <&clock_aop QDSS_CLK>;
80 clock-names = "apb_pclk";
81
82 ports {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 port@0 {
87 reg = <0>;
88 replicator_out_tmc_etr: endpoint {
89 remote-endpoint=
90 <&tmc_etr_in_replicator>;
91 };
92 };
93
94 port@1 {
95 reg = <0>;
96 replicator_in_tmc_etf: endpoint {
97 slave-mode;
98 remote-endpoint=
99 <&tmc_etf_out_replicator>;
100 };
101 };
102 };
103 };
104
105 tmc_etf: tmc@6047000 {
106 compatible = "arm,primecell";
107 arm,primecell-periphid = <0x0003b961>;
108
109 reg = <0x6047000 0x1000>;
110 reg-names = "tmc-base";
111
112 coresight-name = "coresight-tmc-etf";
113 coresight-ctis = <&cti0 &cti8>;
muluhe54427642018-02-06 20:14:40 +0800[diff] [blame]114 coresight-csr = <&csr>;
Mao Jinlong9c7f4182018-01-11 20:48:58 +0800[diff] [blame]115 arm,default-sink;
116
117 clocks = <&clock_aop QDSS_CLK>;
118 clock-names = "apb_pclk";
119
120 ports {
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 port@0 {
125 reg = <0>;
126 tmc_etf_out_replicator: endpoint {
127 remote-endpoint =
128 <&replicator_in_tmc_etf>;
129 };
130 };
131
132 port@1 {
133 reg = <0>;
134 tmc_etf_in_funnel_merg: endpoint {
135 slave-mode;
136 remote-endpoint =
137 <&funnel_merg_out_tmc_etf>;
138 };
139 };
140 };
141 };
142
143 funnel_merg: funnel@6045000 {
144 compatible = "arm,primecell";
145 arm,primecell-periphid = <0x0003b908>;
146
147 reg = <0x6045000 0x1000>;
148 reg-names = "funnel-base";
149
150 coresight-name = "coresight-funnel-merg";
151
152 clocks = <&clock_aop QDSS_CLK>;
153 clock-names = "apb_pclk";
154
155 ports {
156 #address-cells = <1>;
157 #size-cells = <0>;
158
159 port@0 {
160 reg = <0>;
161 funnel_merg_out_tmc_etf: endpoint {
162 remote-endpoint =
163 <&tmc_etf_in_funnel_merg>;
164 };
165 };
166
167 port@1 {
168 reg = <0>;
169 funnel_merg_in_funnel_in0: endpoint {
170 slave-mode;
171 remote-endpoint =
172 <&funnel_in0_out_funnel_merg>;
173 };
174 };
175
176 port@2 {
177 reg = <1>;
178 funnel_merg_in_funnel_in1: endpoint {
179 slave-mode;
180 remote-endpoint =
181 <&funnel_in1_out_funnel_merg>;
182 };
183 };
184 };
185 };
186
187 funnel_in0: funnel@6041000 {
188 compatible = "arm,primecell";
189 arm,primecell-periphid = <0x0003b908>;
190
191 reg = <0x6041000 0x1000>;
192 reg-names = "funnel-base";
193
194 coresight-name = "coresight-funnel-in0";
195
196 clocks = <&clock_aop QDSS_CLK>;
197 clock-names = "apb_pclk";
198
199 ports {
200 #address-cells = <1>;
201 #size-cells = <0>;
202
203 port@0 {
204 reg = <0>;
205 funnel_in0_out_funnel_merg: endpoint {
206 remote-endpoint =
207 <&funnel_merg_in_funnel_in0>;
208 };
209 };
210
211 port@1 {
212 reg = <6>;
213 funnel_in0_in_funnel_qatb: endpoint {
214 slave-mode;
215 remote-endpoint =
216 <&funnel_qatb_out_funnel_in0>;
217 };
218 };
219
220 port@2 {
221 reg = <7>;
222 funnel_in0_in_stm: endpoint {
223 slave-mode;
224 remote-endpoint = <&stm_out_funnel_in0>;
225 };
226 };
227 };
228 };
229
230 stm: stm@6002000 {
231 compatible = "arm,primecell";
232 arm,primecell-periphid = <0x0003b962>;
233
234 reg = <0x6002000 0x1000>,
235 <0x16280000 0x180000>;
236 reg-names = "stm-base", "stm-stimulus-base";
237
238 coresight-name = "coresight-stm";
239
240 clocks = <&clock_aop QDSS_CLK>;
241 clock-names = "apb_pclk";
242
243 port {
244 stm_out_funnel_in0: endpoint {
245 remote-endpoint = <&funnel_in0_in_stm>;
246 };
247 };
248
249 };
250
251 funnel_qatb: funnel@6005000 {
252 compatible = "arm,primecell";
253 arm,primecell-periphid = <0x0003b908>;
254
255 reg = <0x6005000 0x1000>;
256 reg-names = "funnel-base";
257
258 coresight-name = "coresight-funnel-qatb";
259
260 clocks = <&clock_aop QDSS_CLK>;
261 clock-names = "apb_pclk";
262
263 ports {
264 #address-cells = <1>;
265 #size-cells = <0>;
266
267 port@0 {
268 reg = <0>;
269 funnel_qatb_out_funnel_in0: endpoint {
270 remote-endpoint =
271 <&funnel_in0_in_funnel_qatb>;
272 };
273 };
274
275 port@1 {
276 reg = <0>;
277 funnel_qatb_in_tpda: endpoint {
278 slave-mode;
279 remote-endpoint =
280 <&tpda_out_funnel_qatb>;
281 };
282 };
283 };
284 };
285
286 tpda: tpda@6004000 {
287 compatible = "arm,primecell";
288 arm,primecell-periphid = <0x0003b969>;
289 reg = <0x6004000 0x1000>;
290 reg-names = "tpda-base";
291
292 coresight-name = "coresight-tpda";
293
294 qcom,tpda-atid = <65>;
295 qcom,bc-elem-size = <10 32>,
296 <13 32>;
297 qcom,tc-elem-size = <13 32>;
298 qcom,dsb-elem-size = <0 32>,
299 <2 32>,
300 <3 32>,
301 <5 32>,
302 <6 32>,
303 <10 32>,
304 <11 32>,
305 <13 32>;
306 qcom,cmb-elem-size = <3 64>,
307 <7 64>,
308 <9 64>,
309 <13 64>;
310
311 clocks = <&clock_aop QDSS_CLK>;
312 clock-names = "apb_pclk";
313
314 ports {
315 #address-cells = <1>;
316 #size-cells = <0>;
317 port@0 {
318 reg = <0>;
319 tpda_out_funnel_qatb: endpoint {
320 remote-endpoint =
321 <&funnel_qatb_in_tpda>;
322 };
323
324 };
325
326 port@1 {
327 reg = <0>;
328 tpda_in_funnel_ddr_0: endpoint {
329 slave-mode;
330 remote-endpoint =
331 <&funnel_ddr_0_out_tpda>;
332 };
333 };
334
335 port@2 {
336 reg = <1>;
337 tpda_in_tpdm_vsense: endpoint {
338 slave-mode;
339 remote-endpoint =
340 <&tpdm_vsense_out_tpda>;
341 };
342 };
343
344 port@3 {
345 reg = <2>;
346 tpda_in_tpdm_dcc: endpoint {
347 slave-mode;
348 remote-endpoint =
349 <&tpdm_dcc_out_tpda>;
350 };
351 };
352
353 port@4 {
354 reg = <5>;
355 tpda_in_tpdm_center: endpoint {
356 slave-mode;
357 remote-endpoint =
358 <&tpdm_center_out_tpda>;
359 };
360 };
361 };
362 };
363
364 funnel_ddr_0: funnel@69e2000 {
365 compatible = "arm,primecell";
366 arm,primecell-periphid = <0x0003b908>;
367
368 reg = <0x69e2000 0x1000>;
369 reg-names = "funnel-base";
370
371 coresight-name = "coresight-funnel-ddr-0";
372
373 clocks = <&clock_aop QDSS_CLK>;
374 clock-names = "apb_pclk";
375
376 ports {
377 #address-cells = <1>;
378 #size-cells = <0>;
379
380 port@0 {
381 reg = <0>;
382 funnel_ddr_0_out_tpda: endpoint {
383 remote-endpoint =
384 <&tpda_in_funnel_ddr_0>;
385 };
386 };
387
388 port@1 {
389 reg = <0>;
390 funnel_ddr_0_in_tpdm_ddr: endpoint {
391 slave-mode;
392 remote-endpoint =
393 <&tpdm_ddr_out_funnel_ddr_0>;
394 };
395 };
396 };
397 };
398
399 tpdm_dcc: tpdm@6870280 {
400 compatible = "arm,primecell";
401 arm,primecell-periphid = <0x0003b968>;
402 reg = <0x6870280 0x1000>;
403 reg-names = "tpdm-base";
404
405 coresight-name = "coresight-tpdm-dcc";
406
407 clocks = <&clock_aop QDSS_CLK>;
408 clock-names = "apb_pclk";
409
410 port{
411 tpdm_dcc_out_tpda: endpoint {
412 remote-endpoint = <&tpda_in_tpdm_dcc>;
413 };
414 };
415 };
416
417 tpdm_vsense: tpdm@6840000 {
418 compatible = "arm,primecell";
419 arm,primecell-periphid = <0x0003b968>;
420 reg = <0x6840000 0x1000>;
421 reg-names = "tpdm-base";
422
423 coresight-name = "coresight-tpdm-vsense";
424
425 clocks = <&clock_aop QDSS_CLK>;
426 clock-names = "apb_pclk";
427
428 port{
429 tpdm_vsense_out_tpda: endpoint {
430 remote-endpoint = <&tpda_in_tpdm_vsense>;
431 };
432 };
433 };
434
435 tpdm_center: tpdm@6c28000 {
436 compatible = "arm,primecell";
437 arm,primecell-periphid = <0x0003b968>;
438 reg = <0x6c28000 0x1000>;
439 reg-names = "tpdm-base";
440
441 coresight-name = "coresight-tpdm-center";
442
443 clocks = <&clock_aop QDSS_CLK>;
444 clock-names = "apb_pclk";
445
446 port{
447 tpdm_center_out_tpda: endpoint {
448 remote-endpoint = <&tpda_in_tpdm_center>;
449 };
450 };
451 };
452
453 tpdm_ddr: tpdm@69e0000 {
454 compatible = "arm,primecell";
455 arm,primecell-periphid = <0x0003b968>;
456 reg = <0x69e0000 0x1000>;
457 reg-names = "tpdm-base";
458
459 coresight-name = "coresight-tpdm-ddr";
460
461 clocks = <&clock_aop QDSS_CLK>;
462 clock-names = "apb_pclk";
463
464 qcom,msr-fix-req;
465
466 port {
467 tpdm_ddr_out_funnel_ddr_0: endpoint {
468 remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
469 };
470 };
471 };
472
473 funnel_in1: funnel@6042000 {
474 compatible = "arm,primecell";
475 arm,primecell-periphid = <0x0003b908>;
476
477 reg = <0x6042000 0x1000>;
478 reg-names = "funnel-base";
479
480 coresight-name = "coresight-funnel-in1";
481
482 clocks = <&clock_aop QDSS_CLK>;
483 clock-names = "apb_pclk";
484
485 ports {
486 #address-cells = <1>;
487 #size-cells = <0>;
488
489 port@0 {
490 reg = <0>;
491 funnel_in1_out_funnel_merg: endpoint {
492 remote-endpoint =
493 <&funnel_merg_in_funnel_in1>;
494 };
495 };
496
497 port@1 {
498 reg = <2>;
499 funnel_in1_in_funnel_swao: endpoint {
500 slave-mode;
501 remote-endpoint =
502 <&funnel_swao_out_funnel_in1>;
503 };
504 };
505
506 port@2 {
507 reg = <3>;
508 funnel_in1_in_modem_etm0: endpoint {
509 slave-mode;
510 remote-endpoint =
511 <&modem_etm0_out_funnel_in1>;
512 };
513 };
514
515 port@3 {
516 reg = <7>;
517 funnel_in1_in_tpda_modem: endpoint {
518 slave-mode;
519 remote-endpoint =
520 <&tpda_modem_out_funnel_in1>;
521 };
522 };
523 };
524 };
525
526 modem_etm0 {
527 compatible = "qcom,coresight-remote-etm";
528
529 coresight-name = "coresight-modem-etm0";
530 qcom,inst-id = <2>;
531
532 port {
533 modem_etm0_out_funnel_in1: endpoint {
534 remote-endpoint =
535 <&funnel_in1_in_modem_etm0>;
536 };
537 };
538 };
539
540 funnel_swao:funnel@6b08000 {
541 compatible = "arm,primecell";
542 arm,primecell-periphid = <0x0003b908>;
543
544 reg = <0x6b08000 0x1000>;
545 reg-names = "funnel-base";
546
547 coresight-name = "coresight-funnel-swao";
548
549 clocks = <&clock_aop QDSS_CLK>;
550 clock-names = "apb_pclk";
551
552 ports {
553 #address-cells = <1>;
554 #size-cells = <0>;
555
556 port@0 {
557 reg = <0>;
558 funnel_swao_out_funnel_in1: endpoint {
559 remote-endpoint =
560 <&funnel_in1_in_funnel_swao>;
561 };
562 };
563
564 port@1 {
565 reg = <7>;
566 funnel_swao_in_tpda_swao: endpoint {
567 slave-mode;
568 remote-endpoint=
569 <&tpda_swao_out_funnel_swao>;
570 };
571 };
572 };
573 };
574
575 tpda_modem: tpda@6832000 {
576 compatible = "arm,primecell";
577 arm,primecell-periphid = <0x0003b969>;
578 reg = <0x6832000 0x1000>;
579 reg-names = "tpda-base";
580
581 coresight-name = "coresight-tpda-modem";
582
583 qcom,tpda-atid = <67>;
584 qcom,dsb-elem-size = <0 32>;
585 qcom,cmb-elem-size = <0 64>;
586
587 clocks = <&clock_aop QDSS_CLK>;
588 clock-names = "apb_pclk";
589
590 ports {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 port@0 {
594 reg = <0>;
595 tpda_modem_out_funnel_in1: endpoint {
596 remote-endpoint =
597 <&funnel_in1_in_tpda_modem>;
598 };
599 };
600
601 port@1 {
602 reg = <0>;
603 tpda_modem_in_tpdm_modem: endpoint {
604 slave-mode;
605 remote-endpoint =
606 <&tpdm_modem_out_tpda_modem>;
607 };
608 };
609 };
610 };
611
612 tpdm_modem: tpdm@6830000 {
613 compatible = "arm,primecell";
614 arm,primecell-periphid = <0x0003b968>;
615 reg = <0x6830000 0x1000>;
616 reg-names = "tpdm-base";
617
618 coresight-name = "coresight-tpdm-modem";
619
620 clocks = <&clock_aop QDSS_CLK>;
621 clock-names = "apb_pclk";
622
623 port {
624 tpdm_modem_out_tpda_modem: endpoint {
625 remote-endpoint = <&tpda_modem_in_tpdm_modem>;
626 };
627 };
628 };
629
630 tpda_swao: tpda@6b01000 {
631 compatible = "arm,primecell";
632 arm,primecell-periphid = <0x0003b969>;
633 reg = <0x6b01000 0x1000>;
634 reg-names = "tpda-base";
635
636 coresight-name = "coresight-tpda-swao";
637
638 qcom,tpda-atid = <71>;
639 qcom,dsb-elem-size = <1 32>;
640 qcom,cmb-elem-size = <0 64>;
641
642 clocks = <&clock_aop QDSS_CLK>;
643 clock-names = "apb_pclk";
644
645 ports {
646 #address-cells = <1>;
647 #size-cells = <0>;
648
649 port@0 {
650 reg = <0>;
651 tpda_swao_out_funnel_swao: endpoint {
652 remote-endpoint =
653 <&funnel_swao_in_tpda_swao>;
654 };
655
656 };
657
658 port@1 {
659 reg = <0>;
660 tpda_swao_in_tpdm_swao0: endpoint {
661 slave-mode;
662 remote-endpoint =
663 <&tpdm_swao0_out_tpda_swao>;
664 };
665 };
666
667 port@2 {
668 reg = <1>;
669 tpda_swao_in_tpdm_swao1: endpoint {
670 slave-mode;
671 remote-endpoint =
672 <&tpdm_swao1_out_tpda_swao>;
673 };
674
675 };
676 };
677 };
678
679 tpdm_swao0: tpdm@6b02000 {
680 compatible = "arm,primecell";
681 arm,primecell-periphid = <0x0003b968>;
682
683 reg = <0x6b02000 0x1000>;
684 reg-names = "tpdm-base";
685
686 coresight-name = "coresight-tpdm-swao-0";
687
688 clocks = <&clock_aop QDSS_CLK>;
689 clock-names = "apb_pclk";
690
691 port {
692 tpdm_swao0_out_tpda_swao: endpoint {
693 remote-endpoint = <&tpda_swao_in_tpdm_swao0>;
694 };
695 };
696 };
697
698 tpdm_swao1: tpdm@6b03000 {
699 compatible = "arm,primecell";
700 arm,primecell-periphid = <0x0003b968>;
701 reg = <0x6b03000 0x1000>;
702 reg-names = "tpdm-base";
703
704 coresight-name="coresight-tpdm-swao-1";
705
706 clocks = <&clock_aop QDSS_CLK>;
707 clock-names = "apb_pclk";
708
709 qcom,msr-fix-req;
710
711 port {
712 tpdm_swao1_out_tpda_swao: endpoint {
713 remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
714 };
715 };
716 };
717
718 ipcb_tgu: tgu@6b0c000 {
719 compatible = "arm,primecell";
720 arm,primecell-periphid = <0x0003b999>;
721 reg = <0x6b0c000 0x1000>;
722 reg-names = "tgu-base";
723 tgu-steps = <3>;
724 tgu-conditions = <4>;
725 tgu-regs = <4>;
726 tgu-timer-counters = <8>;
727
728 coresight-name = "coresight-tgu-ipcb";
729
730 clocks = <&clock_aop QDSS_CLK>;
731 clock-names = "apb_pclk";
732 };
733
734 cti0: cti@6010000 {
735 compatible = "arm,primecell";
736 arm,primecell-periphid = <0x0003b966>;
737 reg = <0x6010000 0x1000>;
738 reg-names = "cti-base";
739
740 coresight-name = "coresight-cti0";
741
742 clocks = <&clock_aop QDSS_CLK>;
743 clock-names = "apb_pclk";
744
745 };
746
747 cti1: cti@6011000 {
748 compatible = "arm,primecell";
749 arm,primecell-periphid = <0x0003b966>;
750 reg = <0x6011000 0x1000>;
751 reg-names = "cti-base";
752
753 coresight-name = "coresight-cti1";
754
755 clocks = <&clock_aop QDSS_CLK>;
756 clock-names = "apb_pclk";
757
758 };
759
760 cti2: cti@6012000 {
761 compatible = "arm,primecell";
762 arm,primecell-periphid = <0x0003b966>;
763 reg = <0x6012000 0x1000>;
764 reg-names = "cti-base";
765
766 coresight-name = "coresight-cti2";
767
768 clocks = <&clock_aop QDSS_CLK>;
769 clock-names = "apb_pclk";
770 };
771
772 cti3: cti@6013000 {
773 compatible = "arm,primecell";
774 arm,primecell-periphid = <0x0003b966>;
775 reg = <0x6013000 0x1000>;
776 reg-names = "cti-base";
777
778 coresight-name = "coresight-cti3";
779
780 clocks = <&clock_aop QDSS_CLK>;
781 clock-names = "apb_pclk";
782
783 };
784
785 cti4: cti@6014000 {
786 compatible = "arm,primecell";
787 arm,primecell-periphid = <0x0003b966>;
788 reg = <0x6014000 0x1000>;
789 reg-names = "cti-base";
790
791 coresight-name = "coresight-cti4";
792
793 clocks = <&clock_aop QDSS_CLK>;
794 clock-names = "apb_pclk";
795
796 };
797
798 cti5: cti@6015000 {
799 compatible = "arm,primecell";
800 arm,primecell-periphid = <0x0003b966>;
801 reg = <0x6015000 0x1000>;
802 reg-names = "cti-base";
803
804 coresight-name = "coresight-cti5";
805
806 clocks = <&clock_aop QDSS_CLK>;
807 clock-names = "apb_pclk";
808
809 };
810
811 cti6: cti@6016000 {
812 compatible = "arm,primecell";
813 arm,primecell-periphid = <0x0003b966>;
814 reg = <0x6016000 0x1000>;
815 reg-names = "cti-base";
816
817 coresight-name = "coresight-cti6";
818
819 clocks = <&clock_aop QDSS_CLK>;
820 clock-names = "apb_pclk";
821
822 };
823
824 cti7: cti@6017000 {
825 compatible = "arm,primecell";
826 arm,primecell-periphid = <0x0003b966>;
827 reg = <0x6017000 0x1000>;
828 reg-names = "cti-base";
829
830 coresight-name = "coresight-cti7";
831
832 clocks = <&clock_aop QDSS_CLK>;
833 clock-names = "apb_pclk";
834
835 };
836
837 cti8: cti@6018000 {
838 compatible = "arm,primecell";
839 arm,primecell-periphid = <0x0003b966>;
840 reg = <0x6018000 0x1000>;
841 reg-names = "cti-base";
842
843 coresight-name = "coresight-cti8";
844
845 clocks = <&clock_aop QDSS_CLK>;
846 clock-names = "apb_pclk";
847
848 };
849
850 cti9: cti@6019000 {
851 compatible = "arm,primecell";
852 arm,primecell-periphid = <0x0003b966>;
853 reg = <0x6019000 0x1000>;
854 reg-names = "cti-base";
855
856 coresight-name = "coresight-cti9";
857
858 clocks = <&clock_aop QDSS_CLK>;
859 clock-names = "apb_pclk";
860
861 };
862
863 cti10: cti@601a000 {
864 compatible = "arm,primecell";
865 arm,primecell-periphid = <0x0003b966>;
866 reg = <0x601a000 0x1000>;
867 reg-names = "cti-base";
868
869 coresight-name = "coresight-cti10";
870
871 clocks = <&clock_aop QDSS_CLK>;
872 clock-names = "apb_pclk";
873
874 };
875
876 cti11: cti@601b000 {
877 compatible = "arm,primecell";
878 arm,primecell-periphid = <0x0003b966>;
879 reg = <0x601b000 0x1000>;
880 reg-names = "cti-base";
881
882 coresight-name = "coresight-cti11";
883
884 clocks = <&clock_aop QDSS_CLK>;
885 clock-names = "apb_pclk";
886
887 };
888
889 cti12: cti@601c000 {
890 compatible = "arm,primecell";
891 arm,primecell-periphid = <0x0003b966>;
892 reg = <0x601c000 0x1000>;
893 reg-names = "cti-base";
894
895 coresight-name = "coresight-cti12";
896
897 clocks = <&clock_aop QDSS_CLK>;
898 clock-names = "apb_pclk";
899
900 };
901
902 cti13: cti@601d000 {
903 compatible = "arm,primecell";
904 arm,primecell-periphid = <0x0003b966>;
905 reg = <0x601d000 0x1000>;
906 reg-names = "cti-base";
907
908 coresight-name = "coresight-cti13";
909
910 clocks = <&clock_aop QDSS_CLK>;
911 clock-names = "apb_pclk";
912
913 };
914
915 cti14: cti@601e000 {
916 compatible = "arm,primecell";
917 arm,primecell-periphid = <0x0003b966>;
918 reg = <0x601e000 0x1000>;
919 reg-names = "cti-base";
920
921 coresight-name = "coresight-cti14";
922
923 clocks = <&clock_aop QDSS_CLK>;
924 clock-names = "apb_pclk";
925
926 };
927
928 cti15: cti@601f000 {
929 compatible = "arm,primecell";
930 arm,primecell-periphid = <0x0003b966>;
931 reg = <0x601f000 0x1000>;
932 reg-names = "cti-base";
933
934 coresight-name = "coresight-cti15";
935
936 clocks = <&clock_aop QDSS_CLK>;
937 clock-names = "apb_pclk";
938
939 };
940
941 cti_cpu0: cti@7003000 {
942 compatible = "arm,primecell";
943 arm,primecell-periphid = <0x0003b966>;
944 reg = <0x7003000 0x1000>;
945 reg-names = "cti-base";
946
947 coresight-name = "coresight-cti-cpu0";
948 cpu = <&CPU0>;
949
950 clocks = <&clock_aop QDSS_CLK>;
951 clock-names = "apb_pclk";
952
953 };
954
955 cti_modem_cpu0:cti@6837000 {
956 compatible = "arm,primecell";
957 arm,primecell-periphid = <0x0003b966>;
958 reg = <0x6837000 0x1000>;
959 reg-names = "cti-base";
960
961 coresight-name = "coresight-cti-modem-cpu0";
962
963 clocks = <&clock_aop QDSS_CLK>;
964 clock-names = "apb_pclk";
965 };
966
967 cti_modem_cpu1:cti@683b000 {
968 compatible = "arm,primecell";
969 arm,primecell-periphid = <0x0003b966>;
970 reg = <0x683b000 0x1000>;
971 reg-names = "cti-base";
972
973 coresight-name = "coresight-cti-modem-cpu1";
974
975 clocks = <&clock_aop QDSS_CLK>;
976 clock-names = "apb_pclk";
977 };
978
979 cti0_swao:cti@6b04000 {
980 compatible = "arm,primecell";
981 arm,primecell-periphid = <0x0003b966>;
982 reg = <0x6b04000 0x1000>;
983 reg-names = "cti-base";
984
985 coresight-name = "coresight-cti-swao_cti0";
986
987 clocks = <&clock_aop QDSS_CLK>;
988 clock-names = "apb_pclk";
989 };
990
991 cti1_swao:cti@6b05000 {
992 compatible = "arm,primecell";
993 arm,primecell-periphid = <0x0003b966>;
994 reg = <0x6b05000 0x1000>;
995 reg-names = "cti-base";
996
997 coresight-name = "coresight-cti-swao_cti1";
998
999 clocks = <&clock_aop QDSS_CLK>;
1000 clock-names = "apb_pclk";
1001 };
1002
1003 cti2_swao:cti@6b06000 {
1004 compatible = "arm,primecell";
1005 arm,primecell-periphid = <0x0003b966>;
1006 reg = <0x6b06000 0x1000>;
1007 reg-names = "cti-base";
1008
1009 coresight-name = "coresight-cti-swao_cti2";
1010
1011 clocks = <&clock_aop QDSS_CLK>;
1012 clock-names = "apb_pclk";
1013 };
1014
1015 cti3_swao:cti@6b07000 {
1016 compatible = "arm,primecell";
1017 arm,primecell-periphid = <0x0003b966>;
1018 reg = <0x6b07000 0x1000>;
1019 reg-names = "cti-base";
1020
1021 coresight-name = "coresight-cti-swao_cti3";
1022
1023 clocks = <&clock_aop QDSS_CLK>;
1024 clock-names = "apb_pclk";
1025 };
1026
1027 cti0_ddr0: cti@69e1000 {
1028 compatible = "arm,primecell";
1029 arm,primecell-periphid = <0x0003b966>;
1030 reg = <0x69e1000 0x1000>;
1031 reg-names = "cti-base";
1032
1033 coresight-name = "coresight-cti-ddr_dl_0_cti";
1034
1035 clocks = <&clock_aop QDSS_CLK>;
1036 clock-names = "apb_pclk";
1037 };
1038
1039 cti0_ddr1: cti@69e4000 {
1040 compatible = "arm,primecell";
1041 arm,primecell-periphid = <0x0003b966>;
1042 reg = <0x69e4000 0x1000>;
1043 reg-names = "cti-base";
1044
1045 coresight-name = "coresight-cti-ddr_dl_1_cti0";
1046
1047 clocks = <&clock_aop QDSS_CLK>;
1048 clock-names = "apb_pclk";
1049 };
1050
1051 cti1_ddr1: cti@69e5000 {
1052 compatible = "arm,primecell";
1053 arm,primecell-periphid = <0x0003b966>;
1054 reg = <0x69e5000 0x1000>;
1055 reg-names = "cti-base";
1056
1057 coresight-name = "coresight-cti-ddr_dl_1_cti1";
1058
1059 clocks = <&clock_aop QDSS_CLK>;
1060 clock-names = "apb_pclk";
1061 };
1062
1063 cti2_ddr1: cti@69e6000 {
1064 compatible = "arm,primecell";
1065 arm,primecell-periphid = <0x0003b966>;
1066 reg = <0x69e6000 0x1000>;
1067 reg-names = "cti-base";
1068
1069 coresight-name = "coresight-cti-ddr_dl_1_cti2";
1070
1071 clocks = <&clock_aop QDSS_CLK>;
1072 clock-names = "apb_pclk";
1073 };
1074
1075 hwevent: hwevent@0x014066f0 {
1076 compatible = "qcom,coresight-hwevent";
1077 reg = <0x14066f0 0x4>,
1078 <0x14166f0 0x4>,
1079 <0x1406038 0x4>,
1080 <0x1416038 0x4>;
1081 reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl",
1082 "ddr-ch23-ctrl";
1083
1084 coresight-name = "coresight-hwevent";
muluhe54427642018-02-06 20:14:40 +0800[diff] [blame]1085 coresight-csr = <&csr>;
Mao Jinlong9c7f4182018-01-11 20:48:58 +0800[diff] [blame]1086
1087 clocks = <&clock_aop QDSS_CLK>;
1088 clock-names = "apb_pclk";
1089 };
1090};