| Jingbiao Lu | cff0037 | 2018-02-01 15:18:17 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | / { |
| 15 | psci { |
| 16 | compatible = "arm,psci-1.0"; |
| 17 | method = "smc"; |
| 18 | }; |
| 19 | |
| 20 | cpus { |
| 21 | #address-cells = <1>; |
| 22 | #size-cells = <0>; |
| 23 | cpu-map { |
| 24 | cluster0 { |
| 25 | core0 { |
| 26 | cpu = <&CPU4>; |
| 27 | }; |
| 28 | core1 { |
| 29 | cpu = <&CPU5>; |
| 30 | }; |
| 31 | core2 { |
| 32 | cpu = <&CPU6>; |
| 33 | }; |
| 34 | core3 { |
| 35 | cpu = <&CPU7>; |
| 36 | }; |
| 37 | }; |
| 38 | |
| 39 | cluster1 { |
| 40 | core0 { |
| 41 | cpu = <&CPU0>; |
| 42 | }; |
| 43 | core1 { |
| 44 | cpu = <&CPU1>; |
| 45 | }; |
| 46 | core2 { |
| 47 | cpu = <&CPU2>; |
| 48 | }; |
| 49 | core3 { |
| 50 | cpu = <&CPU3>; |
| 51 | }; |
| 52 | }; |
| 53 | }; |
| 54 | |
| 55 | CPU0: cpu@100 { |
| 56 | device_type = "cpu"; |
| 57 | compatible = "arm,cortex-a53"; |
| 58 | reg = <0x100>; |
| 59 | enable-method = "psci"; |
| 60 | next-level-cache = <&L2_1>; |
| 61 | L2_1: l2-cache { |
| 62 | compatible = "arm,arch-cache"; |
| 63 | cache-level = <2>; |
| 64 | /* A53 L2 dump not supported */ |
| 65 | qcom,dump-size = <0x0>; |
| 66 | }; |
| 67 | L1_I_100: l1-icache { |
| 68 | compatible = "arm,arch-cache"; |
| 69 | qcom,dump-size = <0x8800>; |
| 70 | }; |
| 71 | L1_D_100: l1-dcache { |
| 72 | compatible = "arm,arch-cache"; |
| 73 | qcom,dump-size = <0x9000>; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | CPU1: cpu@101 { |
| 78 | device_type = "cpu"; |
| 79 | compatible = "arm,cortex-a53"; |
| 80 | reg = <0x101>; |
| 81 | enable-method = "psci"; |
| 82 | next-level-cache = <&L2_1>; |
| 83 | L1_I_101: l1-icache { |
| 84 | compatible = "arm,arch-cache"; |
| 85 | qcom,dump-size = <0x8800>; |
| 86 | }; |
| 87 | L1_D_101: l1-dcache { |
| 88 | compatible = "arm,arch-cache"; |
| 89 | qcom,dump-size = <0x9000>; |
| 90 | }; |
| 91 | }; |
| 92 | |
| 93 | CPU2: cpu@102 { |
| 94 | device_type = "cpu"; |
| 95 | compatible = "arm,cortex-a53"; |
| 96 | reg = <0x102>; |
| 97 | enable-method = "psci"; |
| 98 | next-level-cache = <&L2_1>; |
| 99 | L1_I_102: l1-icache { |
| 100 | compatible = "arm,arch-cache"; |
| 101 | qcom,dump-size = <0x8800>; |
| 102 | }; |
| 103 | L1_D_102: l1-dcache { |
| 104 | compatible = "arm,arch-cache"; |
| 105 | qcom,dump-size = <0x9000>; |
| 106 | }; |
| 107 | }; |
| 108 | |
| 109 | CPU3: cpu@103 { |
| 110 | device_type = "cpu"; |
| 111 | compatible = "arm,cortex-a53"; |
| 112 | reg = <0x103>; |
| 113 | enable-method = "psci"; |
| 114 | next-level-cache = <&L2_1>; |
| 115 | L1_I_103: l1-icache { |
| 116 | compatible = "arm,arch-cache"; |
| 117 | qcom,dump-size = <0x8800>; |
| 118 | }; |
| 119 | L1_D_103: l1-dcache { |
| 120 | compatible = "arm,arch-cache"; |
| 121 | qcom,dump-size = <0x9000>; |
| 122 | }; |
| 123 | }; |
| 124 | |
| 125 | CPU4: cpu@0 { |
| 126 | device_type = "cpu"; |
| 127 | compatible = "arm,cortex-a53"; |
| 128 | reg = <0x0>; |
| 129 | enable-method = "psci"; |
| 130 | next-level-cache = <&L2_0>; |
| 131 | L2_0: l2-cache { |
| 132 | compatible = "arm,arch-cache"; |
| 133 | cache-level = <2>; |
| 134 | qcom,dump-size = <0x0>; |
| 135 | }; |
| 136 | L1_I_0: l1-icache { |
| 137 | compatible = "arm,arch-cache"; |
| 138 | qcom,dump-size = <0x8800>; |
| 139 | }; |
| 140 | L1_D_0: l1-dcache { |
| 141 | compatible = "arm,arch-cache"; |
| 142 | qcom,dump-size = <0x9000>; |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | CPU5: cpu@1 { |
| 147 | device_type = "cpu"; |
| 148 | compatible = "arm,cortex-a53"; |
| 149 | reg = <0x1>; |
| 150 | enable-method = "psci"; |
| 151 | next-level-cache = <&L2_0>; |
| 152 | L1_I_1: l1-icache { |
| 153 | compatible = "arm,arch-cache"; |
| 154 | qcom,dump-size = <0x8800>; |
| 155 | }; |
| 156 | L1_D_1: l1-dcache { |
| 157 | compatible = "arm,arch-cache"; |
| 158 | qcom,dump-size = <0x9000>; |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | CPU6: cpu@2 { |
| 163 | device_type = "cpu"; |
| 164 | compatible = "arm,cortex-a53"; |
| 165 | reg = <0x2>; |
| 166 | enable-method = "psci"; |
| 167 | next-level-cache = <&L2_0>; |
| 168 | L1_I_2: l1-icache { |
| 169 | compatible = "arm,arch-cache"; |
| 170 | qcom,dump-size = <0x8800>; |
| 171 | }; |
| 172 | L1_D_2: l1-dcache { |
| 173 | compatible = "arm,arch-cache"; |
| 174 | qcom,dump-size = <0x9000>; |
| 175 | }; |
| 176 | }; |
| 177 | |
| 178 | CPU7: cpu@3 { |
| 179 | device_type = "cpu"; |
| 180 | compatible = "arm,cortex-a53"; |
| 181 | reg = <0x3>; |
| 182 | enable-method = "psci"; |
| 183 | next-level-cache = <&L2_0>; |
| 184 | L1_I_3: l1-icache { |
| 185 | compatible = "arm,arch-cache"; |
| 186 | qcom,dump-size = <0x8800>; |
| 187 | }; |
| 188 | L1_D_3: l1-dcache { |
| 189 | compatible = "arm,arch-cache"; |
| 190 | qcom,dump-size = <0x9000>; |
| 191 | }; |
| 192 | }; |
| 193 | }; |
| 194 | }; |