Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/iopoll.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/clk/msm-clock-generic.h> |
| 20 | |
| 21 | #include "mdss-pll.h" |
| 22 | #include "mdss-dsi-pll.h" |
| 23 | #include "mdss-dsi-pll-8996.h" |
| 24 | |
| 25 | #define DSI_PLL_POLL_MAX_READS 15 |
| 26 | #define DSI_PLL_POLL_TIMEOUT_US 1000 |
| 27 | #define MSM8996_DSI_PLL_REVISION_2 2 |
| 28 | |
| 29 | #define DSI_PHY_SPARE_VAL 0x6a |
| 30 | #define DSI_PLL_DEFAULT_POSTDIV 1 |
| 31 | |
| 32 | #define CEIL(x, y) (((x) + ((y)-1)) / (y)) |
| 33 | static void pll_db_commit_8996(struct mdss_pll_resources *pll, |
| 34 | struct dsi_pll_db *pdb); |
| 35 | |
| 36 | int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel) |
| 37 | { |
| 38 | return 0; |
| 39 | } |
| 40 | |
| 41 | int get_mdss_byte_mux_sel_8996(struct mux_clk *clk) |
| 42 | { |
| 43 | return 0; |
| 44 | } |
| 45 | |
| 46 | int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel) |
| 47 | { |
| 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk) |
| 52 | { |
| 53 | return 0; |
| 54 | } |
| 55 | |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 56 | int post_n1_div_set_div(struct div_clk *clk, int div) |
| 57 | { |
| 58 | struct mdss_pll_resources *pll = clk->priv; |
| 59 | struct dsi_pll_db *pdb; |
| 60 | struct dsi_pll_output *pout; |
| 61 | int rc; |
| 62 | u32 n1div = 0; |
| 63 | |
| 64 | rc = mdss_pll_resource_enable(pll, true); |
| 65 | if (rc) { |
| 66 | pr_err("Failed to enable mdss dsi pll resources\n"); |
| 67 | return rc; |
| 68 | } |
| 69 | |
| 70 | pdb = (struct dsi_pll_db *)pll->priv; |
| 71 | pout = &pdb->out; |
| 72 | |
| 73 | /* |
| 74 | * vco rate = bit_clk * postdiv * n1div |
| 75 | * vco range from 1300 to 2600 Mhz |
| 76 | * postdiv = 1 |
| 77 | * n1div = 1 to 15 |
| 78 | * n1div = roundup(1300Mhz / bit_clk) |
| 79 | * support bit_clk above 86.67Mhz |
| 80 | */ |
| 81 | |
| 82 | /* this is for vco/bit clock */ |
| 83 | pout->pll_postdiv = DSI_PLL_DEFAULT_POSTDIV; |
| 84 | pout->pll_n1div = div; |
| 85 | |
| 86 | n1div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); |
| 87 | n1div &= ~0xf; |
| 88 | n1div |= (div & 0xf); |
| 89 | MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG0, n1div); |
| 90 | /* ensure n1 divider is programed */ |
| 91 | wmb(); |
| 92 | pr_debug("ndx=%d div=%d postdiv=%x n1div=%x\n", |
| 93 | pll->index, div, pout->pll_postdiv, pout->pll_n1div); |
| 94 | |
| 95 | mdss_pll_resource_enable(pll, false); |
| 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | int post_n1_div_get_div(struct div_clk *clk) |
| 101 | { |
| 102 | u32 div; |
| 103 | int rc; |
| 104 | struct mdss_pll_resources *pll = clk->priv; |
| 105 | |
| 106 | if (is_gdsc_disabled(pll)) |
| 107 | return 0; |
| 108 | |
| 109 | rc = mdss_pll_resource_enable(pll, true); |
| 110 | if (rc) { |
| 111 | pr_err("Failed to enable mdss dsi pll resources\n"); |
| 112 | return rc; |
| 113 | } |
| 114 | |
| 115 | /* |
| 116 | * postdiv = 1/2/4/8 |
| 117 | * n1div = 1 - 15 |
| 118 | * fot the time being, assume postdiv = 1 |
| 119 | */ |
| 120 | |
| 121 | div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); |
| 122 | div &= 0xF; |
| 123 | pr_debug("n1 div = %d\n", div); |
| 124 | |
| 125 | mdss_pll_resource_enable(pll, false); |
| 126 | |
| 127 | return div; |
| 128 | } |
| 129 | |
| 130 | int n2_div_set_div(struct div_clk *clk, int div) |
| 131 | { |
| 132 | int rc; |
| 133 | u32 n2div; |
| 134 | struct mdss_pll_resources *pll = clk->priv; |
| 135 | struct dsi_pll_db *pdb; |
| 136 | struct dsi_pll_output *pout; |
| 137 | struct mdss_pll_resources *slave; |
| 138 | |
| 139 | rc = mdss_pll_resource_enable(pll, true); |
| 140 | if (rc) { |
| 141 | pr_err("Failed to enable mdss dsi pll resources\n"); |
| 142 | return rc; |
| 143 | } |
| 144 | |
| 145 | pdb = (struct dsi_pll_db *)pll->priv; |
| 146 | pout = &pdb->out; |
| 147 | |
| 148 | /* this is for pixel_clock */ |
| 149 | n2div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); |
| 150 | n2div &= ~0xf0; /* bits 4 to 7 */ |
| 151 | n2div |= (div << 4); |
| 152 | MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG0, n2div); |
| 153 | |
| 154 | /* commit slave if split display is enabled */ |
| 155 | slave = pll->slave; |
| 156 | if (slave) |
| 157 | MDSS_PLL_REG_W(slave->pll_base, DSIPHY_CMN_CLK_CFG0, n2div); |
| 158 | |
| 159 | pout->pll_n2div = div; |
| 160 | |
| 161 | /* set dsiclk_sel=1 so that n2div *= 2 */ |
| 162 | MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG1, 1); |
| 163 | pr_debug("ndx=%d div=%d n2div=%x\n", pll->index, div, n2div); |
| 164 | |
| 165 | mdss_pll_resource_enable(pll, false); |
| 166 | |
| 167 | return rc; |
| 168 | } |
| 169 | |
| 170 | int shadow_n2_div_set_div(struct div_clk *clk, int div) |
| 171 | { |
| 172 | struct mdss_pll_resources *pll = clk->priv; |
| 173 | struct dsi_pll_db *pdb; |
| 174 | struct dsi_pll_output *pout; |
| 175 | u32 data; |
| 176 | |
| 177 | pdb = pll->priv; |
| 178 | pout = &pdb->out; |
| 179 | |
| 180 | pout->pll_n2div = div; |
| 181 | |
| 182 | data = (pout->pll_n1div | (pout->pll_n2div << 4)); |
| 183 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 184 | DSI_DYNAMIC_REFRESH_PLL_CTRL19, |
| 185 | DSIPHY_CMN_CLK_CFG0, DSIPHY_CMN_CLK_CFG1, |
| 186 | data, 1); |
| 187 | return 0; |
| 188 | } |
| 189 | |
| 190 | int n2_div_get_div(struct div_clk *clk) |
| 191 | { |
| 192 | int rc; |
| 193 | u32 n2div; |
| 194 | struct mdss_pll_resources *pll = clk->priv; |
| 195 | |
| 196 | if (is_gdsc_disabled(pll)) |
| 197 | return 0; |
| 198 | |
| 199 | rc = mdss_pll_resource_enable(pll, true); |
| 200 | if (rc) { |
| 201 | pr_err("Failed to enable mdss dsi pll=%d resources\n", |
| 202 | pll->index); |
| 203 | return rc; |
| 204 | } |
| 205 | |
| 206 | n2div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0); |
| 207 | n2div >>= 4; |
| 208 | n2div &= 0x0f; |
| 209 | |
| 210 | mdss_pll_resource_enable(pll, false); |
| 211 | |
| 212 | pr_debug("ndx=%d div=%d\n", pll->index, n2div); |
| 213 | |
| 214 | return n2div; |
| 215 | } |
| 216 | |
| 217 | static bool pll_is_pll_locked_8996(struct mdss_pll_resources *pll) |
| 218 | { |
| 219 | u32 status; |
| 220 | bool pll_locked; |
| 221 | |
| 222 | /* poll for PLL ready status */ |
| 223 | if (readl_poll_timeout_atomic((pll->pll_base + |
| 224 | DSIPHY_PLL_RESET_SM_READY_STATUS), |
| 225 | status, |
| 226 | ((status & BIT(5)) > 0), |
| 227 | DSI_PLL_POLL_MAX_READS, |
| 228 | DSI_PLL_POLL_TIMEOUT_US)) { |
| 229 | pr_err("DSI PLL ndx=%d status=%x failed to Lock\n", |
| 230 | pll->index, status); |
| 231 | pll_locked = false; |
| 232 | } else if (readl_poll_timeout_atomic((pll->pll_base + |
| 233 | DSIPHY_PLL_RESET_SM_READY_STATUS), |
| 234 | status, |
| 235 | ((status & BIT(0)) > 0), |
| 236 | DSI_PLL_POLL_MAX_READS, |
| 237 | DSI_PLL_POLL_TIMEOUT_US)) { |
| 238 | pr_err("DSI PLL ndx=%d status=%x PLl not ready\n", |
| 239 | pll->index, status); |
| 240 | pll_locked = false; |
| 241 | } else { |
| 242 | pll_locked = true; |
| 243 | } |
| 244 | |
| 245 | return pll_locked; |
| 246 | } |
| 247 | |
| 248 | static void dsi_pll_start_8996(void __iomem *pll_base) |
| 249 | { |
| 250 | pr_debug("start PLL at base=%pk\n", pll_base); |
| 251 | |
| 252 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VREF_CFG1, 0x10); |
| 253 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 1); |
| 254 | wmb(); /* make sure register committed */ |
| 255 | } |
| 256 | |
| 257 | static void dsi_pll_stop_8996(void __iomem *pll_base) |
| 258 | { |
| 259 | pr_debug("stop PLL at base=%pk\n", pll_base); |
| 260 | |
| 261 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 0); |
| 262 | wmb(); /* make sure register committed */ |
| 263 | } |
| 264 | |
| 265 | static inline bool pll_use_precal(struct mdss_pll_resources *pll) |
| 266 | { |
| 267 | bool ret = true; |
| 268 | u32 spare = MDSS_PLL_REG_R(pll->pll_base, |
| 269 | DSIPHY_CMN_GLBL_DIGTOP_SPARE2); |
| 270 | |
| 271 | if (!pll->cache_pll_trim_codes[0] || /* kvco code */ |
| 272 | !pll->cache_pll_trim_codes[1] || /* vco tune */ |
| 273 | !pll->cache_pll_trim_codes_rate || |
| 274 | (pll->cache_pll_trim_codes_rate != pll->vco_current_rate) || |
| 275 | (spare != DSI_PHY_SPARE_VAL)) /* phy reset */ |
| 276 | ret = false; |
| 277 | |
| 278 | pr_debug("ndx:%d kvco:%d vco_tune:%d spare:0x%x rate:%llu old:%llu ret:%d\n", |
| 279 | pll->index, pll->cache_pll_trim_codes[0], |
| 280 | pll->cache_pll_trim_codes[1], spare, |
| 281 | pll->cache_pll_trim_codes_rate, |
| 282 | pll->vco_current_rate, ret); |
| 283 | |
| 284 | return ret; |
| 285 | } |
| 286 | |
| 287 | int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll) |
| 288 | { |
| 289 | int rc = 0; |
| 290 | struct dsi_pll_db *pdb; |
| 291 | struct mdss_pll_resources *slave; |
| 292 | |
| 293 | if (!pll) { |
| 294 | pr_err("Invalid PLL resources\n"); |
| 295 | return -EINVAL; |
| 296 | } |
| 297 | |
| 298 | pdb = (struct dsi_pll_db *)pll->priv; |
| 299 | if (!pdb) { |
| 300 | pr_err("No priv found\n"); |
| 301 | return -EINVAL; |
| 302 | } |
| 303 | |
| 304 | dsi_pll_start_8996(pll->pll_base); |
| 305 | |
| 306 | /* |
| 307 | * both DSIPHY_PLL_CLKBUFLR_EN and DSIPHY_CMN_GLBL_TEST_CTRL |
| 308 | * enabled at mdss_dsi_8996_phy_config() |
| 309 | */ |
| 310 | |
| 311 | if (!pll_is_pll_locked_8996(pll)) { |
| 312 | pr_err("DSI PLL ndx=%d lock failed, retry full sequence!\n", |
| 313 | pll->index); |
| 314 | slave = pll->slave; |
| 315 | |
| 316 | /* commit slave if split display is enabled */ |
| 317 | if (slave) |
| 318 | pll_db_commit_8996(slave, pdb); |
| 319 | |
| 320 | /* commit master itself */ |
| 321 | pll_db_commit_8996(pll, pdb); |
| 322 | |
| 323 | dsi_pll_start_8996(pll->pll_base); |
| 324 | if (!pll_is_pll_locked_8996(pll)) { |
| 325 | pr_err("DSI PLL ndx=%d lock failed!!!\n", |
| 326 | pll->index); |
| 327 | rc = -EINVAL; |
| 328 | goto init_lock_err; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | if (!pll_use_precal(pll)) { |
| 333 | /* cache vco settings */ |
| 334 | pll->cache_pll_trim_codes[0] = MDSS_PLL_REG_R(pll->pll_base, |
| 335 | DSIPHY_PLL_CORE_KVCO_CODE_STATUS); |
| 336 | pll->cache_pll_trim_codes[1] = MDSS_PLL_REG_R(pll->pll_base, |
| 337 | DSIPHY_PLL_CORE_VCO_TUNE_STATUS); |
| 338 | pll->cache_pll_trim_codes_rate = pll->vco_current_rate; |
| 339 | |
| 340 | /* write spare */ |
| 341 | MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_DIGTOP_SPARE2, |
| 342 | DSI_PHY_SPARE_VAL); |
| 343 | } |
| 344 | |
| 345 | pr_debug("DSI PLL ndx:%d Locked! kvco=0x%x vco_tune=0x%x rate=%llu\n", |
| 346 | pll->index, pll->cache_pll_trim_codes[0], |
| 347 | pll->cache_pll_trim_codes[1], |
| 348 | pll->cache_pll_trim_codes_rate); |
| 349 | |
| 350 | init_lock_err: |
| 351 | return rc; |
| 352 | } |
| 353 | |
| 354 | static int dsi_pll_enable(struct clk *c) |
| 355 | { |
| 356 | int i, rc = 0; |
| 357 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 358 | struct mdss_pll_resources *pll = vco->priv; |
| 359 | |
| 360 | /* Try all enable sequences until one succeeds */ |
| 361 | for (i = 0; i < vco->pll_en_seq_cnt; i++) { |
| 362 | rc = vco->pll_enable_seqs[i](pll); |
| 363 | pr_debug("DSI PLL %s after sequence #%d\n", |
| 364 | rc ? "unlocked" : "locked", i + 1); |
| 365 | if (!rc) |
| 366 | break; |
| 367 | } |
| 368 | |
| 369 | if (rc) |
| 370 | pr_err("ndx=%d DSI PLL failed to lock\n", pll->index); |
| 371 | else |
| 372 | pll->pll_on = true; |
| 373 | |
| 374 | return rc; |
| 375 | } |
| 376 | |
| 377 | static void dsi_pll_disable(struct clk *c) |
| 378 | { |
| 379 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 380 | struct mdss_pll_resources *pll = vco->priv; |
| 381 | struct mdss_pll_resources *slave; |
| 382 | |
| 383 | if (!pll->pll_on && |
| 384 | mdss_pll_resource_enable(pll, true)) { |
| 385 | pr_err("Failed to enable mdss dsi pll=%d\n", pll->index); |
| 386 | return; |
| 387 | } |
| 388 | |
| 389 | pll->handoff_resources = false; |
| 390 | slave = pll->slave; |
| 391 | |
| 392 | dsi_pll_stop_8996(pll->pll_base); |
| 393 | |
| 394 | mdss_pll_resource_enable(pll, false); |
| 395 | |
| 396 | pll->pll_on = false; |
| 397 | |
| 398 | pr_debug("DSI PLL ndx=%d Disabled\n", pll->index); |
| 399 | } |
| 400 | |
| 401 | static void mdss_dsi_pll_8996_input_init(struct mdss_pll_resources *pll, |
| 402 | struct dsi_pll_db *pdb) |
| 403 | { |
| 404 | pdb->in.fref = 19200000; /* 19.2 Mhz*/ |
| 405 | pdb->in.fdata = 0; /* bit clock rate */ |
| 406 | pdb->in.dsiclk_sel = 1; /* 1, reg: 0x0014 */ |
| 407 | pdb->in.ssc_en = pll->ssc_en; /* 1, reg: 0x0494, bit 0 */ |
| 408 | pdb->in.ldo_en = 0; /* 0, reg: 0x004c, bit 0 */ |
| 409 | |
| 410 | /* fixed input */ |
| 411 | pdb->in.refclk_dbler_en = 0; /* 0, reg: 0x04c0, bit 1 */ |
| 412 | pdb->in.vco_measure_time = 5; /* 5, unknown */ |
| 413 | pdb->in.kvco_measure_time = 5; /* 5, unknown */ |
| 414 | pdb->in.bandgap_timer = 4; /* 4, reg: 0x0430, bit 3 - 5 */ |
| 415 | pdb->in.pll_wakeup_timer = 5; /* 5, reg: 0x043c, bit 0 - 2 */ |
| 416 | pdb->in.plllock_cnt = 1; /* 1, reg: 0x0488, bit 1 - 2 */ |
| 417 | pdb->in.plllock_rng = 0; /* 0, reg: 0x0488, bit 3 - 4 */ |
| 418 | pdb->in.ssc_center = pll->ssc_center;/* 0, reg: 0x0494, bit 1 */ |
| 419 | pdb->in.ssc_adj_period = 37; /* 37, reg: 0x498, bit 0 - 9 */ |
| 420 | pdb->in.ssc_spread = pll->ssc_ppm / 1000; |
| 421 | pdb->in.ssc_freq = pll->ssc_freq; |
| 422 | |
| 423 | pdb->in.pll_ie_trim = 4; /* 4, reg: 0x0400 */ |
| 424 | pdb->in.pll_ip_trim = 4; /* 4, reg: 0x0404 */ |
| 425 | pdb->in.pll_cpcset_cur = 1; /* 1, reg: 0x04f0, bit 0 - 2 */ |
| 426 | pdb->in.pll_cpmset_cur = 1; /* 1, reg: 0x04f0, bit 3 - 5 */ |
| 427 | pdb->in.pll_icpmset = 4; /* 4, reg: 0x04fc, bit 3 - 5 */ |
| 428 | pdb->in.pll_icpcset = 4; /* 4, reg: 0x04fc, bit 0 - 2 */ |
| 429 | pdb->in.pll_icpmset_p = 0; /* 0, reg: 0x04f4, bit 0 - 2 */ |
| 430 | pdb->in.pll_icpmset_m = 0; /* 0, reg: 0x04f4, bit 3 - 5 */ |
| 431 | pdb->in.pll_icpcset_p = 0; /* 0, reg: 0x04f8, bit 0 - 2 */ |
| 432 | pdb->in.pll_icpcset_m = 0; /* 0, reg: 0x04f8, bit 3 - 5 */ |
| 433 | pdb->in.pll_lpf_res1 = 3; /* 3, reg: 0x0504, bit 0 - 3 */ |
| 434 | pdb->in.pll_lpf_cap1 = 11; /* 11, reg: 0x0500, bit 0 - 3 */ |
| 435 | pdb->in.pll_lpf_cap2 = 1; /* 1, reg: 0x0500, bit 4 - 7 */ |
| 436 | pdb->in.pll_iptat_trim = 7; |
| 437 | pdb->in.pll_c3ctrl = 2; /* 2 */ |
| 438 | pdb->in.pll_r3ctrl = 1; /* 1 */ |
| 439 | } |
| 440 | |
| 441 | static void pll_8996_ssc_calc(struct mdss_pll_resources *pll, |
| 442 | struct dsi_pll_db *pdb) |
| 443 | { |
| 444 | u32 period, ssc_period; |
| 445 | u32 ref, rem; |
| 446 | s64 step_size; |
| 447 | |
| 448 | pr_debug("%s: vco=%lld ref=%lld\n", __func__, |
| 449 | pll->vco_current_rate, pll->vco_ref_clk_rate); |
| 450 | |
| 451 | ssc_period = pdb->in.ssc_freq / 500; |
| 452 | period = (unsigned long)pll->vco_ref_clk_rate / 1000; |
| 453 | ssc_period = CEIL(period, ssc_period); |
| 454 | ssc_period -= 1; |
| 455 | pdb->out.ssc_period = ssc_period; |
| 456 | |
| 457 | pr_debug("%s: ssc, freq=%d spread=%d period=%d\n", __func__, |
| 458 | pdb->in.ssc_freq, pdb->in.ssc_spread, pdb->out.ssc_period); |
| 459 | |
| 460 | step_size = (u32)pll->vco_current_rate; |
| 461 | ref = pll->vco_ref_clk_rate; |
| 462 | ref /= 1000; |
| 463 | step_size = div_s64(step_size, ref); |
| 464 | step_size <<= 20; |
| 465 | step_size = div_s64(step_size, 1000); |
| 466 | step_size *= pdb->in.ssc_spread; |
| 467 | step_size = div_s64(step_size, 1000); |
| 468 | step_size *= (pdb->in.ssc_adj_period + 1); |
| 469 | |
| 470 | rem = 0; |
| 471 | step_size = div_s64_rem(step_size, ssc_period + 1, &rem); |
| 472 | if (rem) |
| 473 | step_size++; |
| 474 | |
| 475 | pr_debug("%s: step_size=%lld\n", __func__, step_size); |
| 476 | |
| 477 | step_size &= 0x0ffff; /* take lower 16 bits */ |
| 478 | |
| 479 | pdb->out.ssc_step_size = step_size; |
| 480 | } |
| 481 | |
| 482 | static void pll_8996_dec_frac_calc(struct mdss_pll_resources *pll, |
| 483 | struct dsi_pll_db *pdb) |
| 484 | { |
| 485 | struct dsi_pll_input *pin = &pdb->in; |
| 486 | struct dsi_pll_output *pout = &pdb->out; |
| 487 | s64 multiplier = BIT(20); |
| 488 | s64 dec_start_multiple, dec_start, pll_comp_val; |
| 489 | s32 duration, div_frac_start; |
| 490 | s64 vco_clk_rate = pll->vco_current_rate; |
| 491 | s64 fref = pll->vco_ref_clk_rate; |
| 492 | |
| 493 | pr_debug("vco_clk_rate=%lld ref_clk_rate=%lld\n", |
| 494 | vco_clk_rate, fref); |
| 495 | |
| 496 | dec_start_multiple = div_s64(vco_clk_rate * multiplier, fref); |
| 497 | div_s64_rem(dec_start_multiple, multiplier, &div_frac_start); |
| 498 | |
| 499 | dec_start = div_s64(dec_start_multiple, multiplier); |
| 500 | |
| 501 | pout->dec_start = (u32)dec_start; |
| 502 | pout->div_frac_start = div_frac_start; |
| 503 | |
| 504 | if (pin->plllock_cnt == 0) |
| 505 | duration = 1024; |
| 506 | else if (pin->plllock_cnt == 1) |
| 507 | duration = 256; |
| 508 | else if (pin->plllock_cnt == 2) |
| 509 | duration = 128; |
| 510 | else |
| 511 | duration = 32; |
| 512 | |
| 513 | pll_comp_val = duration * dec_start_multiple; |
| 514 | pll_comp_val = div_s64(pll_comp_val, multiplier); |
| 515 | do_div(pll_comp_val, 10); |
| 516 | |
| 517 | pout->plllock_cmp = (u32)pll_comp_val; |
| 518 | |
| 519 | pout->pll_txclk_en = 1; |
| 520 | if (pll->revision == MSM8996_DSI_PLL_REVISION_2) |
| 521 | pout->cmn_ldo_cntrl = 0x3c; |
| 522 | else |
| 523 | pout->cmn_ldo_cntrl = 0x1c; |
| 524 | } |
| 525 | |
| 526 | static u32 pll_8996_kvco_slop(u32 vrate) |
| 527 | { |
| 528 | u32 slop = 0; |
| 529 | |
| 530 | if (vrate > 1300000000UL && vrate <= 1800000000UL) |
| 531 | slop = 600; |
| 532 | else if (vrate > 1800000000UL && vrate < 2300000000UL) |
| 533 | slop = 400; |
| 534 | else if (vrate > 2300000000UL && vrate < 2600000000UL) |
| 535 | slop = 280; |
| 536 | |
| 537 | return slop; |
| 538 | } |
| 539 | |
| 540 | static inline u32 pll_8996_calc_kvco_code(s64 vco_clk_rate) |
| 541 | { |
| 542 | u32 kvco_code; |
| 543 | |
| 544 | if ((vco_clk_rate >= 2300000000ULL) && |
| 545 | (vco_clk_rate <= 2600000000ULL)) |
| 546 | kvco_code = 0x2f; |
| 547 | else if ((vco_clk_rate >= 1800000000ULL) && |
| 548 | (vco_clk_rate < 2300000000ULL)) |
| 549 | kvco_code = 0x2c; |
| 550 | else |
| 551 | kvco_code = 0x28; |
| 552 | |
| 553 | pr_debug("rate: %llu kvco_code: 0x%x\n", |
| 554 | vco_clk_rate, kvco_code); |
| 555 | return kvco_code; |
| 556 | } |
| 557 | |
| 558 | static void pll_8996_calc_vco_count(struct dsi_pll_db *pdb, |
| 559 | s64 vco_clk_rate, s64 fref) |
| 560 | { |
| 561 | struct dsi_pll_input *pin = &pdb->in; |
| 562 | struct dsi_pll_output *pout = &pdb->out; |
| 563 | s64 data; |
| 564 | u32 cnt; |
| 565 | |
| 566 | data = fref * pin->vco_measure_time; |
| 567 | do_div(data, 1000000); |
| 568 | data &= 0x03ff; /* 10 bits */ |
| 569 | data -= 2; |
| 570 | pout->pll_vco_div_ref = data; |
| 571 | |
| 572 | data = (unsigned long)vco_clk_rate / 1000000; /* unit is Mhz */ |
| 573 | data *= pin->vco_measure_time; |
| 574 | do_div(data, 10); |
| 575 | pout->pll_vco_count = data; /* reg: 0x0474, 0x0478 */ |
| 576 | |
| 577 | data = fref * pin->kvco_measure_time; |
| 578 | do_div(data, 1000000); |
| 579 | data &= 0x03ff; /* 10 bits */ |
| 580 | data -= 1; |
| 581 | pout->pll_kvco_div_ref = data; |
| 582 | |
| 583 | cnt = pll_8996_kvco_slop(vco_clk_rate); |
| 584 | cnt *= 2; |
| 585 | do_div(cnt, 100); |
| 586 | cnt *= pin->kvco_measure_time; |
| 587 | pout->pll_kvco_count = cnt; |
| 588 | |
| 589 | pout->pll_misc1 = 16; |
| 590 | pout->pll_resetsm_cntrl = 48; |
| 591 | pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3; |
| 592 | pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer; |
| 593 | pout->pll_kvco_code = pll_8996_calc_kvco_code(vco_clk_rate); |
| 594 | } |
| 595 | |
| 596 | static void pll_db_commit_ssc(struct mdss_pll_resources *pll, |
| 597 | struct dsi_pll_db *pdb) |
| 598 | { |
| 599 | void __iomem *pll_base = pll->pll_base; |
| 600 | struct dsi_pll_input *pin = &pdb->in; |
| 601 | struct dsi_pll_output *pout = &pdb->out; |
| 602 | char data; |
| 603 | |
| 604 | data = pin->ssc_adj_period; |
| 605 | data &= 0x0ff; |
| 606 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_ADJ_PER1, data); |
| 607 | data = (pin->ssc_adj_period >> 8); |
| 608 | data &= 0x03; |
| 609 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_ADJ_PER2, data); |
| 610 | |
| 611 | data = pout->ssc_period; |
| 612 | data &= 0x0ff; |
| 613 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_PER1, data); |
| 614 | data = (pout->ssc_period >> 8); |
| 615 | data &= 0x0ff; |
| 616 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_PER2, data); |
| 617 | |
| 618 | data = pout->ssc_step_size; |
| 619 | data &= 0x0ff; |
| 620 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_STEP_SIZE1, data); |
| 621 | data = (pout->ssc_step_size >> 8); |
| 622 | data &= 0x0ff; |
| 623 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_STEP_SIZE2, data); |
| 624 | |
| 625 | data = (pin->ssc_center & 0x01); |
| 626 | data <<= 1; |
| 627 | data |= 0x01; /* enable */ |
| 628 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SSC_EN_CENTER, data); |
| 629 | |
| 630 | wmb(); /* make sure register committed */ |
| 631 | } |
| 632 | |
| 633 | static int pll_precal_commit_8996(struct mdss_pll_resources *pll, |
| 634 | struct dsi_pll_db *pdb) |
| 635 | { |
| 636 | void __iomem *pll_base = pll->pll_base; |
| 637 | struct dsi_pll_output *pout = &pdb->out; |
| 638 | char data; |
| 639 | |
| 640 | /* |
| 641 | * if pre-calibrated values cannot be used, return |
| 642 | * error, so we use full sequence. |
| 643 | */ |
| 644 | if (!pll_use_precal(pll)) { |
| 645 | pr_debug("cannot use precal sequence ndx:%d\n", pll->index); |
| 646 | return -EINVAL; |
| 647 | } |
| 648 | |
| 649 | data = pout->cmn_ldo_cntrl; |
| 650 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_LDO_CNTRL, data); |
| 651 | |
| 652 | /* stop pll */ |
| 653 | data = 0; |
| 654 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, data); |
| 655 | |
| 656 | data = 0x7f; |
| 657 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_0, data); |
| 658 | |
| 659 | data = 0x20; |
| 660 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_1, data); |
| 661 | |
| 662 | data = 0x38; |
| 663 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_RESETSM_CNTRL, data); |
| 664 | |
| 665 | data = BIT(7); |
| 666 | data |= pll->cache_pll_trim_codes[1]; /* vco tune */ |
| 667 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_VCO_TUNE, data); |
| 668 | |
| 669 | data = BIT(5); |
| 670 | data |= pll->cache_pll_trim_codes[0]; /* kvco code */ |
| 671 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_CODE, data); |
| 672 | |
| 673 | data = 0xff; /* data, clk, pll normal operation */ |
| 674 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_0, data); |
| 675 | |
| 676 | data = 0x0; |
| 677 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_1, data); |
| 678 | wmb(); /* make sure register committed */ |
| 679 | |
| 680 | return 0; |
| 681 | } |
| 682 | |
| 683 | static void pll_db_commit_common(struct mdss_pll_resources *pll, |
| 684 | struct dsi_pll_db *pdb) |
| 685 | { |
| 686 | void __iomem *pll_base = pll->pll_base; |
| 687 | struct dsi_pll_input *pin = &pdb->in; |
| 688 | struct dsi_pll_output *pout = &pdb->out; |
| 689 | char data; |
| 690 | |
| 691 | /* confgiure the non frequency dependent pll registers */ |
| 692 | data = 0; |
| 693 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_SYSCLK_EN_RESET, data); |
| 694 | |
| 695 | /* DSIPHY_PLL_CLKBUFLR_EN updated at dsi phy */ |
| 696 | |
| 697 | data = pout->pll_txclk_en; |
| 698 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_TXCLK_EN, data); |
| 699 | |
| 700 | data = pout->pll_resetsm_cntrl; |
| 701 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_RESETSM_CNTRL, data); |
| 702 | data = pout->pll_resetsm_cntrl2; |
| 703 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_RESETSM_CNTRL2, data); |
| 704 | data = pout->pll_resetsm_cntrl5; |
| 705 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_RESETSM_CNTRL5, data); |
| 706 | |
| 707 | data = pout->pll_vco_div_ref; |
| 708 | data &= 0x0ff; |
| 709 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_DIV_REF1, data); |
| 710 | data = (pout->pll_vco_div_ref >> 8); |
| 711 | data &= 0x03; |
| 712 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_DIV_REF2, data); |
| 713 | |
| 714 | data = pout->pll_kvco_div_ref; |
| 715 | data &= 0x0ff; |
| 716 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_DIV_REF1, data); |
| 717 | data = (pout->pll_kvco_div_ref >> 8); |
| 718 | data &= 0x03; |
| 719 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_DIV_REF2, data); |
| 720 | |
| 721 | data = pout->pll_misc1; |
| 722 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_MISC1, data); |
| 723 | |
| 724 | data = pin->pll_ie_trim; |
| 725 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IE_TRIM, data); |
| 726 | |
| 727 | data = pin->pll_ip_trim; |
| 728 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IP_TRIM, data); |
| 729 | |
| 730 | data = ((pin->pll_cpmset_cur << 3) | pin->pll_cpcset_cur); |
| 731 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CP_SET_CUR, data); |
| 732 | |
| 733 | data = ((pin->pll_icpcset_p << 3) | pin->pll_icpcset_m); |
| 734 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_ICPCSET, data); |
| 735 | |
| 736 | data = ((pin->pll_icpmset_p << 3) | pin->pll_icpcset_m); |
| 737 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_ICPMSET, data); |
| 738 | |
| 739 | data = ((pin->pll_icpmset << 3) | pin->pll_icpcset); |
| 740 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_ICP_SET, data); |
| 741 | |
| 742 | data = ((pdb->in.pll_lpf_cap2 << 4) | pdb->in.pll_lpf_cap1); |
| 743 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_LPF1, data); |
| 744 | |
| 745 | data = pin->pll_iptat_trim; |
| 746 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_IPTAT_TRIM, data); |
| 747 | |
| 748 | data = (pdb->in.pll_c3ctrl | (pdb->in.pll_r3ctrl << 4)); |
| 749 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_CRCTRL, data); |
| 750 | } |
| 751 | |
| 752 | static void pll_db_commit_8996(struct mdss_pll_resources *pll, |
| 753 | struct dsi_pll_db *pdb) |
| 754 | { |
| 755 | void __iomem *pll_base = pll->pll_base; |
| 756 | struct dsi_pll_input *pin = &pdb->in; |
| 757 | struct dsi_pll_output *pout = &pdb->out; |
| 758 | char data; |
| 759 | |
| 760 | data = pout->cmn_ldo_cntrl; |
| 761 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_LDO_CNTRL, data); |
| 762 | |
| 763 | pll_db_commit_common(pll, pdb); |
| 764 | |
| 765 | /* de assert pll start and apply pll sw reset */ |
| 766 | /* stop pll */ |
| 767 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_PLL_CNTRL, 0); |
| 768 | |
| 769 | /* pll sw reset */ |
| 770 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_1, 0x20); |
| 771 | wmb(); /* make sure register committed */ |
| 772 | udelay(10); |
| 773 | |
| 774 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_1, 0); |
| 775 | wmb(); /* make sure register committed */ |
| 776 | |
| 777 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_VCO_TUNE, 0); |
| 778 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_CODE, 0); |
| 779 | wmb(); /* make sure register committed */ |
| 780 | |
| 781 | data = pdb->in.dsiclk_sel; /* set dsiclk_sel = 1 */ |
| 782 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CLK_CFG1, data); |
| 783 | |
| 784 | data = 0xff; /* data, clk, pll normal operation */ |
| 785 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CTRL_0, data); |
| 786 | |
| 787 | /* configure the frequency dependent pll registers */ |
| 788 | data = pout->dec_start; |
| 789 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DEC_START, data); |
| 790 | |
| 791 | data = pout->div_frac_start; |
| 792 | data &= 0x0ff; |
| 793 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START1, data); |
| 794 | data = (pout->div_frac_start >> 8); |
| 795 | data &= 0x0ff; |
| 796 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START2, data); |
| 797 | data = (pout->div_frac_start >> 16); |
| 798 | data &= 0x0f; |
| 799 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START3, data); |
| 800 | |
| 801 | data = pout->plllock_cmp; |
| 802 | data &= 0x0ff; |
| 803 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP1, data); |
| 804 | data = (pout->plllock_cmp >> 8); |
| 805 | data &= 0x0ff; |
| 806 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP2, data); |
| 807 | data = (pout->plllock_cmp >> 16); |
| 808 | data &= 0x03; |
| 809 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP3, data); |
| 810 | |
| 811 | data = ((pin->plllock_cnt << 1) | (pin->plllock_rng << 3)); |
| 812 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLLLOCK_CMP_EN, data); |
| 813 | |
| 814 | data = pout->pll_vco_count; |
| 815 | data &= 0x0ff; |
| 816 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_COUNT1, data); |
| 817 | data = (pout->pll_vco_count >> 8); |
| 818 | data &= 0x0ff; |
| 819 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_COUNT2, data); |
| 820 | |
| 821 | data = pout->pll_kvco_count; |
| 822 | data &= 0x0ff; |
| 823 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_COUNT1, data); |
| 824 | data = (pout->pll_kvco_count >> 8); |
| 825 | data &= 0x03; |
| 826 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_COUNT2, data); |
| 827 | |
| 828 | data = (((pout->pll_postdiv - 1) << 4) | pdb->in.pll_lpf_res1); |
| 829 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_PLL_LPF2_POSTDIV, data); |
| 830 | |
| 831 | data = pout->pll_kvco_code; |
| 832 | MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_KVCO_CODE, data); |
| 833 | pr_debug("kvco_code:0x%x\n", data); |
| 834 | |
| 835 | data = (pout->pll_n1div | (pout->pll_n2div << 4)); |
| 836 | MDSS_PLL_REG_W(pll_base, DSIPHY_CMN_CLK_CFG0, data); |
| 837 | |
| 838 | if (pll->ssc_en) |
| 839 | pll_db_commit_ssc(pll, pdb); |
| 840 | |
| 841 | pr_debug("pll:%d\n", pll->index); |
| 842 | wmb(); /* make sure register committed */ |
| 843 | } |
| 844 | |
| 845 | /* |
| 846 | * pll_source_finding: |
| 847 | * Both GLBL_TEST_CTRL and CLKBUFLR_EN are configured |
| 848 | * at mdss_dsi_8996_phy_config() |
| 849 | */ |
| 850 | static int pll_source_finding(struct mdss_pll_resources *pll) |
| 851 | { |
| 852 | u32 clk_buf_en; |
| 853 | u32 glbl_test_ctrl; |
| 854 | |
| 855 | glbl_test_ctrl = MDSS_PLL_REG_R(pll->pll_base, |
| 856 | DSIPHY_CMN_GLBL_TEST_CTRL); |
| 857 | clk_buf_en = MDSS_PLL_REG_R(pll->pll_base, |
| 858 | DSIPHY_PLL_CLKBUFLR_EN); |
| 859 | |
| 860 | glbl_test_ctrl &= BIT(2); |
| 861 | glbl_test_ctrl >>= 2; |
| 862 | |
| 863 | pr_debug("%s: pll=%d clk_buf_en=%x glbl_test_ctrl=%x\n", |
| 864 | __func__, pll->index, clk_buf_en, glbl_test_ctrl); |
| 865 | |
| 866 | clk_buf_en &= (PLL_OUTPUT_RIGHT | PLL_OUTPUT_LEFT); |
| 867 | |
| 868 | if ((glbl_test_ctrl == PLL_SOURCE_FROM_LEFT) && |
| 869 | (clk_buf_en == PLL_OUTPUT_BOTH)) |
| 870 | return PLL_MASTER; |
| 871 | |
| 872 | if ((glbl_test_ctrl == PLL_SOURCE_FROM_RIGHT) && |
| 873 | (clk_buf_en == PLL_OUTPUT_NONE)) |
| 874 | return PLL_SLAVE; |
| 875 | |
| 876 | if ((glbl_test_ctrl == PLL_SOURCE_FROM_LEFT) && |
| 877 | (clk_buf_en == PLL_OUTPUT_RIGHT)) |
| 878 | return PLL_STANDALONE; |
| 879 | |
| 880 | pr_debug("%s: Error pll setup, clk_buf_en=%x glbl_test_ctrl=%x\n", |
| 881 | __func__, clk_buf_en, glbl_test_ctrl); |
| 882 | |
| 883 | return PLL_UNKNOWN; |
| 884 | } |
| 885 | |
| 886 | static void pll_source_setup(struct mdss_pll_resources *pll) |
| 887 | { |
| 888 | int status; |
| 889 | struct dsi_pll_db *pdb = (struct dsi_pll_db *)pll->priv; |
| 890 | struct mdss_pll_resources *other; |
| 891 | |
| 892 | if (pdb->source_setup_done) |
| 893 | return; |
| 894 | |
| 895 | pdb->source_setup_done++; |
| 896 | |
| 897 | status = pll_source_finding(pll); |
| 898 | |
| 899 | if (status == PLL_STANDALONE || status == PLL_UNKNOWN) |
| 900 | return; |
| 901 | |
| 902 | other = pdb->next->pll; |
| 903 | if (!other) |
| 904 | return; |
| 905 | |
| 906 | pr_debug("%s: status=%d pll=%d other=%d\n", __func__, |
| 907 | status, pll->index, other->index); |
| 908 | |
| 909 | if (status == PLL_MASTER) |
| 910 | pll->slave = other; |
| 911 | else |
| 912 | other->slave = pll; |
| 913 | } |
| 914 | |
| 915 | int pll_vco_set_rate_8996(struct clk *c, unsigned long rate) |
| 916 | { |
| 917 | int rc; |
| 918 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 919 | struct mdss_pll_resources *pll = vco->priv; |
| 920 | struct mdss_pll_resources *slave; |
| 921 | struct dsi_pll_db *pdb; |
| 922 | |
| 923 | pdb = (struct dsi_pll_db *)pll->priv; |
| 924 | if (!pdb) { |
| 925 | pr_err("No prov found\n"); |
| 926 | return -EINVAL; |
| 927 | } |
| 928 | |
| 929 | rc = mdss_pll_resource_enable(pll, true); |
| 930 | if (rc) { |
| 931 | pr_err("Failed to enable mdss dsi plla=%d\n", pll->index); |
| 932 | return rc; |
| 933 | } |
| 934 | |
| 935 | pll_source_setup(pll); |
| 936 | |
| 937 | pr_debug("%s: ndx=%d base=%pk rate=%lu slave=%pk\n", __func__, |
| 938 | pll->index, pll->pll_base, rate, pll->slave); |
| 939 | |
| 940 | pll->vco_current_rate = rate; |
| 941 | pll->vco_ref_clk_rate = vco->ref_clk_rate; |
| 942 | |
| 943 | mdss_dsi_pll_8996_input_init(pll, pdb); |
| 944 | /* |
| 945 | * tx_band = pll_postdiv |
| 946 | * 0: divided by 1 <== for now |
| 947 | * 1: divided by 2 |
| 948 | * 2: divided by 4 |
| 949 | * 3: divided by 8 |
| 950 | */ |
| 951 | pdb->out.pll_postdiv = DSI_PLL_DEFAULT_POSTDIV; |
| 952 | |
| 953 | pll_8996_dec_frac_calc(pll, pdb); |
| 954 | |
| 955 | if (pll->ssc_en) |
| 956 | pll_8996_ssc_calc(pll, pdb); |
| 957 | |
| 958 | pll_8996_calc_vco_count(pdb, pll->vco_current_rate, |
| 959 | pll->vco_ref_clk_rate); |
| 960 | |
| 961 | /* precal sequence, only for the master */ |
| 962 | if (pll_precal_commit_8996(pll, pdb)) { |
| 963 | pr_debug("retry full sequence\n"); |
| 964 | slave = pll->slave; |
| 965 | |
| 966 | /* commit slave if split display is enabled */ |
| 967 | if (slave) |
| 968 | pll_db_commit_8996(slave, pdb); |
| 969 | |
| 970 | /* commit master itself */ |
| 971 | pll_db_commit_8996(pll, pdb); |
| 972 | } |
| 973 | |
| 974 | mdss_pll_resource_enable(pll, false); |
| 975 | |
| 976 | return rc; |
| 977 | } |
| 978 | |
| 979 | static void shadow_pll_dynamic_refresh_8996(struct mdss_pll_resources *pll, |
| 980 | struct dsi_pll_db *pdb, int *pll_trim_codes) |
| 981 | { |
| 982 | struct dsi_pll_output *pout = &pdb->out; |
| 983 | |
| 984 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 985 | DSI_DYNAMIC_REFRESH_PLL_CTRL20, |
| 986 | DSIPHY_CMN_CTRL_0, DSIPHY_PLL_SYSCLK_EN_RESET, |
| 987 | 0xFF, 0x0); |
| 988 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 989 | DSI_DYNAMIC_REFRESH_PLL_CTRL21, |
| 990 | DSIPHY_PLL_DEC_START, DSIPHY_PLL_DIV_FRAC_START1, |
| 991 | pout->dec_start, (pout->div_frac_start & 0x0FF)); |
| 992 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 993 | DSI_DYNAMIC_REFRESH_PLL_CTRL22, |
| 994 | DSIPHY_PLL_DIV_FRAC_START2, DSIPHY_PLL_DIV_FRAC_START3, |
| 995 | ((pout->div_frac_start >> 8) & 0x0FF), |
| 996 | ((pout->div_frac_start >> 16) & 0x0F)); |
| 997 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 998 | DSI_DYNAMIC_REFRESH_PLL_CTRL23, |
| 999 | DSIPHY_PLL_PLLLOCK_CMP1, DSIPHY_PLL_PLLLOCK_CMP2, |
| 1000 | (pout->plllock_cmp & 0x0FF), |
| 1001 | ((pout->plllock_cmp >> 8) & 0x0FF)); |
| 1002 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 1003 | DSI_DYNAMIC_REFRESH_PLL_CTRL24, |
| 1004 | DSIPHY_PLL_PLLLOCK_CMP3, DSIPHY_PLL_PLL_VCO_TUNE, |
| 1005 | ((pout->plllock_cmp >> 16) & 0x03), |
| 1006 | (pll_trim_codes[1] | BIT(7))); /* VCO tune*/ |
| 1007 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 1008 | DSI_DYNAMIC_REFRESH_PLL_CTRL25, |
| 1009 | DSIPHY_PLL_KVCO_CODE, DSIPHY_PLL_RESETSM_CNTRL, |
| 1010 | (pll_trim_codes[0] | BIT(5)), 0x38); |
| 1011 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 1012 | DSI_DYNAMIC_REFRESH_PLL_CTRL26, |
| 1013 | DSIPHY_PLL_PLL_LPF2_POSTDIV, DSIPHY_CMN_PLL_CNTRL, |
| 1014 | (((pout->pll_postdiv - 1) << 4) | pdb->in.pll_lpf_res1), 0x01); |
| 1015 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 1016 | DSI_DYNAMIC_REFRESH_PLL_CTRL27, |
| 1017 | DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL, |
| 1018 | 0x01, 0x01); |
| 1019 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 1020 | DSI_DYNAMIC_REFRESH_PLL_CTRL28, |
| 1021 | DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL, |
| 1022 | 0x01, 0x01); |
| 1023 | MDSS_DYN_PLL_REG_W(pll->dyn_pll_base, |
| 1024 | DSI_DYNAMIC_REFRESH_PLL_CTRL29, |
| 1025 | DSIPHY_CMN_PLL_CNTRL, DSIPHY_CMN_PLL_CNTRL, |
| 1026 | 0x01, 0x01); |
| 1027 | MDSS_PLL_REG_W(pll->dyn_pll_base, |
| 1028 | DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR, 0x0000001E); |
| 1029 | MDSS_PLL_REG_W(pll->dyn_pll_base, |
| 1030 | DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0x001FFE00); |
| 1031 | |
| 1032 | pr_debug("core_kvco_code=0x%x core_vco_tune=0x%x\n", |
| 1033 | pll_trim_codes[0], pll_trim_codes[1]); |
| 1034 | |
| 1035 | /* |
| 1036 | * Ensure all the dynamic refresh registers are written before |
| 1037 | * dynamic refresh to change the fps is triggered |
| 1038 | */ |
| 1039 | wmb(); |
| 1040 | } |
| 1041 | |
| 1042 | int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate) |
| 1043 | { |
| 1044 | int rc; |
| 1045 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 1046 | struct mdss_pll_resources *pll = vco->priv; |
| 1047 | struct dsi_pll_db *pdb; |
Sachin Bhayare | 230b7fb | 2018-01-22 11:54:14 +0530 | [diff] [blame] | 1048 | int pll_trim_codes[2] = {0, 0}; |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 1049 | |
| 1050 | if (!pll) { |
| 1051 | pr_err("PLL data not found\n"); |
| 1052 | return -EINVAL; |
| 1053 | } |
| 1054 | |
| 1055 | pdb = pll->priv; |
| 1056 | if (!pdb) { |
| 1057 | pr_err("No priv data found\n"); |
| 1058 | return -EINVAL; |
| 1059 | } |
| 1060 | |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 1061 | rc = mdss_pll_resource_enable(pll, true); |
| 1062 | if (rc) { |
| 1063 | pr_err("Failed to enable mdss dsi plla=%d\n", pll->index); |
| 1064 | return rc; |
| 1065 | } |
| 1066 | |
| 1067 | pr_debug("%s: ndx=%d base=%pk rate=%lu\n", __func__, |
| 1068 | pll->index, pll->pll_base, rate); |
| 1069 | |
| 1070 | pll->vco_current_rate = rate; |
| 1071 | pll->vco_ref_clk_rate = vco->ref_clk_rate; |
| 1072 | |
| 1073 | mdss_dsi_pll_8996_input_init(pll, pdb); |
| 1074 | |
| 1075 | pll_8996_dec_frac_calc(pll, pdb); |
| 1076 | |
| 1077 | pll_8996_calc_vco_count(pdb, pll->vco_current_rate, |
| 1078 | pll->vco_ref_clk_rate); |
| 1079 | |
| 1080 | shadow_pll_dynamic_refresh_8996(pll, pdb, pll_trim_codes); |
| 1081 | |
| 1082 | rc = mdss_pll_resource_enable(pll, false); |
| 1083 | if (rc) { |
| 1084 | pr_err("Failed to enable mdss dsi plla=%d\n", pll->index); |
| 1085 | return rc; |
| 1086 | } |
| 1087 | |
| 1088 | return rc; |
| 1089 | } |
| 1090 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 1091 | static unsigned long pll_vco_get_rate_8996(struct clk *c) |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 1092 | { |
| 1093 | u64 vco_rate, multiplier = BIT(20); |
| 1094 | s32 div_frac_start; |
| 1095 | u32 dec_start; |
| 1096 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 1097 | u64 ref_clk = vco->ref_clk_rate; |
| 1098 | int rc; |
| 1099 | struct mdss_pll_resources *pll = vco->priv; |
| 1100 | |
| 1101 | if (is_gdsc_disabled(pll)) |
| 1102 | return 0; |
| 1103 | |
| 1104 | rc = mdss_pll_resource_enable(pll, true); |
| 1105 | if (rc) { |
| 1106 | pr_err("Failed to enable mdss dsi pll=%d\n", pll->index); |
| 1107 | return rc; |
| 1108 | } |
| 1109 | |
| 1110 | dec_start = MDSS_PLL_REG_R(pll->pll_base, |
| 1111 | DSIPHY_PLL_DEC_START); |
| 1112 | dec_start &= 0x0ff; |
| 1113 | pr_debug("dec_start = 0x%x\n", dec_start); |
| 1114 | |
| 1115 | div_frac_start = (MDSS_PLL_REG_R(pll->pll_base, |
| 1116 | DSIPHY_PLL_DIV_FRAC_START3) & 0x0f) << 16; |
| 1117 | div_frac_start |= (MDSS_PLL_REG_R(pll->pll_base, |
| 1118 | DSIPHY_PLL_DIV_FRAC_START2) & 0x0ff) << 8; |
| 1119 | div_frac_start |= MDSS_PLL_REG_R(pll->pll_base, |
| 1120 | DSIPHY_PLL_DIV_FRAC_START1) & 0x0ff; |
| 1121 | pr_debug("div_frac_start = 0x%x\n", div_frac_start); |
| 1122 | |
| 1123 | vco_rate = ref_clk * dec_start; |
| 1124 | vco_rate += ((ref_clk * div_frac_start) / multiplier); |
| 1125 | |
| 1126 | pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate); |
| 1127 | |
| 1128 | mdss_pll_resource_enable(pll, false); |
| 1129 | |
| 1130 | return (unsigned long)vco_rate; |
| 1131 | } |
| 1132 | |
| 1133 | long pll_vco_round_rate_8996(struct clk *c, unsigned long rate) |
| 1134 | { |
| 1135 | unsigned long rrate = rate; |
| 1136 | u32 div; |
| 1137 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 1138 | |
| 1139 | div = vco->min_rate / rate; |
| 1140 | if (div > 15) { |
| 1141 | /* rate < 86.67 Mhz */ |
| 1142 | pr_err("rate=%lu NOT supportted\n", rate); |
| 1143 | return -EINVAL; |
| 1144 | } |
| 1145 | |
| 1146 | if (rate < vco->min_rate) |
| 1147 | rrate = vco->min_rate; |
| 1148 | if (rate > vco->max_rate) |
| 1149 | rrate = vco->max_rate; |
| 1150 | |
| 1151 | return rrate; |
| 1152 | } |
| 1153 | |
| 1154 | enum handoff pll_vco_handoff_8996(struct clk *c) |
| 1155 | { |
| 1156 | int rc; |
| 1157 | enum handoff ret = HANDOFF_DISABLED_CLK; |
| 1158 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 1159 | struct mdss_pll_resources *pll = vco->priv; |
| 1160 | |
| 1161 | if (is_gdsc_disabled(pll)) |
| 1162 | return HANDOFF_DISABLED_CLK; |
| 1163 | |
| 1164 | rc = mdss_pll_resource_enable(pll, true); |
| 1165 | if (rc) { |
| 1166 | pr_err("Failed to enable mdss dsi pll=%d\n", pll->index); |
| 1167 | return ret; |
| 1168 | } |
| 1169 | |
| 1170 | if (pll_is_pll_locked_8996(pll)) { |
| 1171 | pll->handoff_resources = true; |
| 1172 | pll->pll_on = true; |
| 1173 | c->rate = pll_vco_get_rate_8996(c); |
| 1174 | ret = HANDOFF_ENABLED_CLK; |
| 1175 | } else { |
| 1176 | mdss_pll_resource_enable(pll, false); |
| 1177 | } |
| 1178 | |
| 1179 | return ret; |
| 1180 | } |
| 1181 | |
| 1182 | enum handoff shadow_pll_vco_handoff_8996(struct clk *c) |
| 1183 | { |
| 1184 | return HANDOFF_DISABLED_CLK; |
| 1185 | } |
| 1186 | |
| 1187 | int pll_vco_prepare_8996(struct clk *c) |
| 1188 | { |
| 1189 | int rc = 0; |
| 1190 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 1191 | struct mdss_pll_resources *pll = vco->priv; |
| 1192 | |
| 1193 | if (!pll) { |
| 1194 | pr_err("Dsi pll resources are not available\n"); |
| 1195 | return -EINVAL; |
| 1196 | } |
| 1197 | |
| 1198 | rc = mdss_pll_resource_enable(pll, true); |
| 1199 | if (rc) { |
| 1200 | pr_err("ndx=%d Failed to enable mdss dsi pll resources\n", |
| 1201 | pll->index); |
| 1202 | return rc; |
| 1203 | } |
| 1204 | |
| 1205 | if ((pll->vco_cached_rate != 0) |
| 1206 | && (pll->vco_cached_rate == c->rate)) { |
| 1207 | rc = c->ops->set_rate(c, pll->vco_cached_rate); |
| 1208 | if (rc) { |
| 1209 | pr_err("index=%d vco_set_rate failed. rc=%d\n", |
| 1210 | rc, pll->index); |
| 1211 | mdss_pll_resource_enable(pll, false); |
| 1212 | goto error; |
| 1213 | } |
| 1214 | } |
| 1215 | |
| 1216 | rc = dsi_pll_enable(c); |
| 1217 | |
| 1218 | if (rc) { |
| 1219 | mdss_pll_resource_enable(pll, false); |
| 1220 | pr_err("ndx=%d failed to enable dsi pll\n", pll->index); |
| 1221 | } |
| 1222 | |
| 1223 | error: |
| 1224 | return rc; |
| 1225 | } |
| 1226 | |
| 1227 | void pll_vco_unprepare_8996(struct clk *c) |
| 1228 | { |
| 1229 | struct dsi_pll_vco_clk *vco = to_vco_clk(c); |
| 1230 | struct mdss_pll_resources *pll = vco->priv; |
| 1231 | |
| 1232 | if (!pll) { |
| 1233 | pr_err("Dsi pll resources are not available\n"); |
| 1234 | return; |
| 1235 | } |
| 1236 | |
| 1237 | pll->vco_cached_rate = c->rate; |
| 1238 | dsi_pll_disable(c); |
| 1239 | } |