Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014-2016, 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/iopoll.h> |
| 18 | #include <linux/clk/msm-clk-provider.h> |
| 19 | #include <linux/clk/msm-clk.h> |
| 20 | #include <linux/clk/msm-clock-generic.h> |
| 21 | #include <dt-bindings/clock/msm-clocks-8996.h> |
| 22 | |
| 23 | #include "mdss-pll.h" |
| 24 | #include "mdss-hdmi-pll.h" |
| 25 | |
| 26 | /* CONSTANTS */ |
| 27 | #define HDMI_BIT_CLK_TO_PIX_CLK_RATIO 10 |
| 28 | #define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000UL |
| 29 | #define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000UL |
| 30 | #define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 750000000 |
| 31 | #define HDMI_CLKS_PLL_DIVSEL 0 |
| 32 | #define HDMI_CORECLK_DIV 5 |
| 33 | #define HDMI_REF_CLOCK 19200000 |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 34 | #define HDMI_64B_ERR_VAL 0xFFFFFFFFFFFFFFFFULL |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 35 | #define HDMI_VERSION_8996_V1 1 |
| 36 | #define HDMI_VERSION_8996_V2 2 |
| 37 | #define HDMI_VERSION_8996_V3 3 |
| 38 | #define HDMI_VERSION_8996_V3_1_8 4 |
| 39 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 40 | #define HDMI_VCO_MAX_FREQ 12000000000UL |
| 41 | #define HDMI_VCO_MIN_FREQ 8000000000UL |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 42 | #define HDMI_2400MHZ_BIT_CLK_HZ 2400000000UL |
| 43 | #define HDMI_2250MHZ_BIT_CLK_HZ 2250000000UL |
| 44 | #define HDMI_2000MHZ_BIT_CLK_HZ 2000000000UL |
| 45 | #define HDMI_1700MHZ_BIT_CLK_HZ 1700000000UL |
| 46 | #define HDMI_1200MHZ_BIT_CLK_HZ 1200000000UL |
| 47 | #define HDMI_1334MHZ_BIT_CLK_HZ 1334000000UL |
| 48 | #define HDMI_1000MHZ_BIT_CLK_HZ 1000000000UL |
| 49 | #define HDMI_850MHZ_BIT_CLK_HZ 850000000 |
| 50 | #define HDMI_667MHZ_BIT_CLK_HZ 667000000 |
| 51 | #define HDMI_600MHZ_BIT_CLK_HZ 600000000 |
| 52 | #define HDMI_500MHZ_BIT_CLK_HZ 500000000 |
| 53 | #define HDMI_450MHZ_BIT_CLK_HZ 450000000 |
| 54 | #define HDMI_334MHZ_BIT_CLK_HZ 334000000 |
| 55 | #define HDMI_300MHZ_BIT_CLK_HZ 300000000 |
| 56 | #define HDMI_282MHZ_BIT_CLK_HZ 282000000 |
| 57 | #define HDMI_250MHZ_BIT_CLK_HZ 250000000 |
| 58 | #define HDMI_KHZ_TO_HZ 1000 |
| 59 | |
| 60 | /* PLL REGISTERS */ |
| 61 | #define QSERDES_COM_ATB_SEL1 (0x000) |
| 62 | #define QSERDES_COM_ATB_SEL2 (0x004) |
| 63 | #define QSERDES_COM_FREQ_UPDATE (0x008) |
| 64 | #define QSERDES_COM_BG_TIMER (0x00C) |
| 65 | #define QSERDES_COM_SSC_EN_CENTER (0x010) |
| 66 | #define QSERDES_COM_SSC_ADJ_PER1 (0x014) |
| 67 | #define QSERDES_COM_SSC_ADJ_PER2 (0x018) |
| 68 | #define QSERDES_COM_SSC_PER1 (0x01C) |
| 69 | #define QSERDES_COM_SSC_PER2 (0x020) |
| 70 | #define QSERDES_COM_SSC_STEP_SIZE1 (0x024) |
| 71 | #define QSERDES_COM_SSC_STEP_SIZE2 (0x028) |
| 72 | #define QSERDES_COM_POST_DIV (0x02C) |
| 73 | #define QSERDES_COM_POST_DIV_MUX (0x030) |
| 74 | #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x034) |
| 75 | #define QSERDES_COM_CLK_ENABLE1 (0x038) |
| 76 | #define QSERDES_COM_SYS_CLK_CTRL (0x03C) |
| 77 | #define QSERDES_COM_SYSCLK_BUF_ENABLE (0x040) |
| 78 | #define QSERDES_COM_PLL_EN (0x044) |
| 79 | #define QSERDES_COM_PLL_IVCO (0x048) |
| 80 | #define QSERDES_COM_LOCK_CMP1_MODE0 (0x04C) |
| 81 | #define QSERDES_COM_LOCK_CMP2_MODE0 (0x050) |
| 82 | #define QSERDES_COM_LOCK_CMP3_MODE0 (0x054) |
| 83 | #define QSERDES_COM_LOCK_CMP1_MODE1 (0x058) |
| 84 | #define QSERDES_COM_LOCK_CMP2_MODE1 (0x05C) |
| 85 | #define QSERDES_COM_LOCK_CMP3_MODE1 (0x060) |
| 86 | #define QSERDES_COM_LOCK_CMP1_MODE2 (0x064) |
| 87 | #define QSERDES_COM_CMN_RSVD0 (0x064) |
| 88 | #define QSERDES_COM_LOCK_CMP2_MODE2 (0x068) |
| 89 | #define QSERDES_COM_EP_CLOCK_DETECT_CTRL (0x068) |
| 90 | #define QSERDES_COM_LOCK_CMP3_MODE2 (0x06C) |
| 91 | #define QSERDES_COM_SYSCLK_DET_COMP_STATUS (0x06C) |
| 92 | #define QSERDES_COM_BG_TRIM (0x070) |
| 93 | #define QSERDES_COM_CLK_EP_DIV (0x074) |
| 94 | #define QSERDES_COM_CP_CTRL_MODE0 (0x078) |
| 95 | #define QSERDES_COM_CP_CTRL_MODE1 (0x07C) |
| 96 | #define QSERDES_COM_CP_CTRL_MODE2 (0x080) |
| 97 | #define QSERDES_COM_CMN_RSVD1 (0x080) |
| 98 | #define QSERDES_COM_PLL_RCTRL_MODE0 (0x084) |
| 99 | #define QSERDES_COM_PLL_RCTRL_MODE1 (0x088) |
| 100 | #define QSERDES_COM_PLL_RCTRL_MODE2 (0x08C) |
| 101 | #define QSERDES_COM_CMN_RSVD2 (0x08C) |
| 102 | #define QSERDES_COM_PLL_CCTRL_MODE0 (0x090) |
| 103 | #define QSERDES_COM_PLL_CCTRL_MODE1 (0x094) |
| 104 | #define QSERDES_COM_PLL_CCTRL_MODE2 (0x098) |
| 105 | #define QSERDES_COM_CMN_RSVD3 (0x098) |
| 106 | #define QSERDES_COM_PLL_CNTRL (0x09C) |
| 107 | #define QSERDES_COM_PHASE_SEL_CTRL (0x0A0) |
| 108 | #define QSERDES_COM_PHASE_SEL_DC (0x0A4) |
| 109 | #define QSERDES_COM_CORE_CLK_IN_SYNC_SEL (0x0A8) |
| 110 | #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM (0x0A8) |
| 111 | #define QSERDES_COM_SYSCLK_EN_SEL (0x0AC) |
| 112 | #define QSERDES_COM_CML_SYSCLK_SEL (0x0B0) |
| 113 | #define QSERDES_COM_RESETSM_CNTRL (0x0B4) |
| 114 | #define QSERDES_COM_RESETSM_CNTRL2 (0x0B8) |
| 115 | #define QSERDES_COM_RESTRIM_CTRL (0x0BC) |
| 116 | #define QSERDES_COM_RESTRIM_CTRL2 (0x0C0) |
| 117 | #define QSERDES_COM_RESCODE_DIV_NUM (0x0C4) |
| 118 | #define QSERDES_COM_LOCK_CMP_EN (0x0C8) |
| 119 | #define QSERDES_COM_LOCK_CMP_CFG (0x0CC) |
| 120 | #define QSERDES_COM_DEC_START_MODE0 (0x0D0) |
| 121 | #define QSERDES_COM_DEC_START_MODE1 (0x0D4) |
| 122 | #define QSERDES_COM_DEC_START_MODE2 (0x0D8) |
| 123 | #define QSERDES_COM_VCOCAL_DEADMAN_CTRL (0x0D8) |
| 124 | #define QSERDES_COM_DIV_FRAC_START1_MODE0 (0x0DC) |
| 125 | #define QSERDES_COM_DIV_FRAC_START2_MODE0 (0x0E0) |
| 126 | #define QSERDES_COM_DIV_FRAC_START3_MODE0 (0x0E4) |
| 127 | #define QSERDES_COM_DIV_FRAC_START1_MODE1 (0x0E8) |
| 128 | #define QSERDES_COM_DIV_FRAC_START2_MODE1 (0x0EC) |
| 129 | #define QSERDES_COM_DIV_FRAC_START3_MODE1 (0x0F0) |
| 130 | #define QSERDES_COM_DIV_FRAC_START1_MODE2 (0x0F4) |
| 131 | #define QSERDES_COM_VCO_TUNE_MINVAL1 (0x0F4) |
| 132 | #define QSERDES_COM_DIV_FRAC_START2_MODE2 (0x0F8) |
| 133 | #define QSERDES_COM_VCO_TUNE_MINVAL2 (0x0F8) |
| 134 | #define QSERDES_COM_DIV_FRAC_START3_MODE2 (0x0FC) |
| 135 | #define QSERDES_COM_CMN_RSVD4 (0x0FC) |
| 136 | #define QSERDES_COM_INTEGLOOP_INITVAL (0x100) |
| 137 | #define QSERDES_COM_INTEGLOOP_EN (0x104) |
| 138 | #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 (0x108) |
| 139 | #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 (0x10C) |
| 140 | #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 (0x110) |
| 141 | #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 (0x114) |
| 142 | #define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 (0x118) |
| 143 | #define QSERDES_COM_VCO_TUNE_MAXVAL1 (0x118) |
| 144 | #define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 (0x11C) |
| 145 | #define QSERDES_COM_VCO_TUNE_MAXVAL2 (0x11C) |
| 146 | #define QSERDES_COM_RES_TRIM_CONTROL2 (0x120) |
| 147 | #define QSERDES_COM_VCO_TUNE_CTRL (0x124) |
| 148 | #define QSERDES_COM_VCO_TUNE_MAP (0x128) |
| 149 | #define QSERDES_COM_VCO_TUNE1_MODE0 (0x12C) |
| 150 | #define QSERDES_COM_VCO_TUNE2_MODE0 (0x130) |
| 151 | #define QSERDES_COM_VCO_TUNE1_MODE1 (0x134) |
| 152 | #define QSERDES_COM_VCO_TUNE2_MODE1 (0x138) |
| 153 | #define QSERDES_COM_VCO_TUNE1_MODE2 (0x13C) |
| 154 | #define QSERDES_COM_VCO_TUNE_INITVAL1 (0x13C) |
| 155 | #define QSERDES_COM_VCO_TUNE2_MODE2 (0x140) |
| 156 | #define QSERDES_COM_VCO_TUNE_INITVAL2 (0x140) |
| 157 | #define QSERDES_COM_VCO_TUNE_TIMER1 (0x144) |
| 158 | #define QSERDES_COM_VCO_TUNE_TIMER2 (0x148) |
| 159 | #define QSERDES_COM_SAR (0x14C) |
| 160 | #define QSERDES_COM_SAR_CLK (0x150) |
| 161 | #define QSERDES_COM_SAR_CODE_OUT_STATUS (0x154) |
| 162 | #define QSERDES_COM_SAR_CODE_READY_STATUS (0x158) |
| 163 | #define QSERDES_COM_CMN_STATUS (0x15C) |
| 164 | #define QSERDES_COM_RESET_SM_STATUS (0x160) |
| 165 | #define QSERDES_COM_RESTRIM_CODE_STATUS (0x164) |
| 166 | #define QSERDES_COM_PLLCAL_CODE1_STATUS (0x168) |
| 167 | #define QSERDES_COM_PLLCAL_CODE2_STATUS (0x16C) |
| 168 | #define QSERDES_COM_BG_CTRL (0x170) |
| 169 | #define QSERDES_COM_CLK_SELECT (0x174) |
| 170 | #define QSERDES_COM_HSCLK_SEL (0x178) |
| 171 | #define QSERDES_COM_INTEGLOOP_BINCODE_STATUS (0x17C) |
| 172 | #define QSERDES_COM_PLL_ANALOG (0x180) |
| 173 | #define QSERDES_COM_CORECLK_DIV (0x184) |
| 174 | #define QSERDES_COM_SW_RESET (0x188) |
| 175 | #define QSERDES_COM_CORE_CLK_EN (0x18C) |
| 176 | #define QSERDES_COM_C_READY_STATUS (0x190) |
| 177 | #define QSERDES_COM_CMN_CONFIG (0x194) |
| 178 | #define QSERDES_COM_CMN_RATE_OVERRIDE (0x198) |
| 179 | #define QSERDES_COM_SVS_MODE_CLK_SEL (0x19C) |
| 180 | #define QSERDES_COM_DEBUG_BUS0 (0x1A0) |
| 181 | #define QSERDES_COM_DEBUG_BUS1 (0x1A4) |
| 182 | #define QSERDES_COM_DEBUG_BUS2 (0x1A8) |
| 183 | #define QSERDES_COM_DEBUG_BUS3 (0x1AC) |
| 184 | #define QSERDES_COM_DEBUG_BUS_SEL (0x1B0) |
| 185 | #define QSERDES_COM_CMN_MISC1 (0x1B4) |
| 186 | #define QSERDES_COM_CMN_MISC2 (0x1B8) |
| 187 | #define QSERDES_COM_CORECLK_DIV_MODE1 (0x1BC) |
| 188 | #define QSERDES_COM_CORECLK_DIV_MODE2 (0x1C0) |
| 189 | #define QSERDES_COM_CMN_RSVD5 (0x1C0) |
| 190 | |
| 191 | /* Tx Channel base addresses */ |
| 192 | #define HDMI_TX_L0_BASE_OFFSET (0x400) |
| 193 | #define HDMI_TX_L1_BASE_OFFSET (0x600) |
| 194 | #define HDMI_TX_L2_BASE_OFFSET (0x800) |
| 195 | #define HDMI_TX_L3_BASE_OFFSET (0xA00) |
| 196 | |
| 197 | /* Tx Channel PHY registers */ |
| 198 | #define QSERDES_TX_L0_BIST_MODE_LANENO (0x000) |
| 199 | #define QSERDES_TX_L0_BIST_INVERT (0x004) |
| 200 | #define QSERDES_TX_L0_CLKBUF_ENABLE (0x008) |
| 201 | #define QSERDES_TX_L0_CMN_CONTROL_ONE (0x00C) |
| 202 | #define QSERDES_TX_L0_CMN_CONTROL_TWO (0x010) |
| 203 | #define QSERDES_TX_L0_CMN_CONTROL_THREE (0x014) |
| 204 | #define QSERDES_TX_L0_TX_EMP_POST1_LVL (0x018) |
| 205 | #define QSERDES_TX_L0_TX_POST2_EMPH (0x01C) |
| 206 | #define QSERDES_TX_L0_TX_BOOST_LVL_UP_DN (0x020) |
| 207 | #define QSERDES_TX_L0_HP_PD_ENABLES (0x024) |
| 208 | #define QSERDES_TX_L0_TX_IDLE_LVL_LARGE_AMP (0x028) |
| 209 | #define QSERDES_TX_L0_TX_DRV_LVL (0x02C) |
| 210 | #define QSERDES_TX_L0_TX_DRV_LVL_OFFSET (0x030) |
| 211 | #define QSERDES_TX_L0_RESET_TSYNC_EN (0x034) |
| 212 | #define QSERDES_TX_L0_PRE_STALL_LDO_BOOST_EN (0x038) |
| 213 | #define QSERDES_TX_L0_TX_BAND (0x03C) |
| 214 | #define QSERDES_TX_L0_SLEW_CNTL (0x040) |
| 215 | #define QSERDES_TX_L0_INTERFACE_SELECT (0x044) |
| 216 | #define QSERDES_TX_L0_LPB_EN (0x048) |
| 217 | #define QSERDES_TX_L0_RES_CODE_LANE_TX (0x04C) |
| 218 | #define QSERDES_TX_L0_RES_CODE_LANE_RX (0x050) |
| 219 | #define QSERDES_TX_L0_RES_CODE_LANE_OFFSET (0x054) |
| 220 | #define QSERDES_TX_L0_PERL_LENGTH1 (0x058) |
| 221 | #define QSERDES_TX_L0_PERL_LENGTH2 (0x05C) |
| 222 | #define QSERDES_TX_L0_SERDES_BYP_EN_OUT (0x060) |
| 223 | #define QSERDES_TX_L0_DEBUG_BUS_SEL (0x064) |
| 224 | #define QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x068) |
| 225 | #define QSERDES_TX_L0_TX_POL_INV (0x06C) |
| 226 | #define QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN (0x070) |
| 227 | #define QSERDES_TX_L0_BIST_PATTERN1 (0x074) |
| 228 | #define QSERDES_TX_L0_BIST_PATTERN2 (0x078) |
| 229 | #define QSERDES_TX_L0_BIST_PATTERN3 (0x07C) |
| 230 | #define QSERDES_TX_L0_BIST_PATTERN4 (0x080) |
| 231 | #define QSERDES_TX_L0_BIST_PATTERN5 (0x084) |
| 232 | #define QSERDES_TX_L0_BIST_PATTERN6 (0x088) |
| 233 | #define QSERDES_TX_L0_BIST_PATTERN7 (0x08C) |
| 234 | #define QSERDES_TX_L0_BIST_PATTERN8 (0x090) |
| 235 | #define QSERDES_TX_L0_LANE_MODE (0x094) |
| 236 | #define QSERDES_TX_L0_IDAC_CAL_LANE_MODE (0x098) |
| 237 | #define QSERDES_TX_L0_IDAC_CAL_LANE_MODE_CONFIGURATION (0x09C) |
| 238 | #define QSERDES_TX_L0_ATB_SEL1 (0x0A0) |
| 239 | #define QSERDES_TX_L0_ATB_SEL2 (0x0A4) |
| 240 | #define QSERDES_TX_L0_RCV_DETECT_LVL (0x0A8) |
| 241 | #define QSERDES_TX_L0_RCV_DETECT_LVL_2 (0x0AC) |
| 242 | #define QSERDES_TX_L0_PRBS_SEED1 (0x0B0) |
| 243 | #define QSERDES_TX_L0_PRBS_SEED2 (0x0B4) |
| 244 | #define QSERDES_TX_L0_PRBS_SEED3 (0x0B8) |
| 245 | #define QSERDES_TX_L0_PRBS_SEED4 (0x0BC) |
| 246 | #define QSERDES_TX_L0_RESET_GEN (0x0C0) |
| 247 | #define QSERDES_TX_L0_RESET_GEN_MUXES (0x0C4) |
| 248 | #define QSERDES_TX_L0_TRAN_DRVR_EMP_EN (0x0C8) |
| 249 | #define QSERDES_TX_L0_TX_INTERFACE_MODE (0x0CC) |
| 250 | #define QSERDES_TX_L0_PWM_CTRL (0x0D0) |
| 251 | #define QSERDES_TX_L0_PWM_ENCODED_OR_DATA (0x0D4) |
| 252 | #define QSERDES_TX_L0_PWM_GEAR_1_DIVIDER_BAND2 (0x0D8) |
| 253 | #define QSERDES_TX_L0_PWM_GEAR_2_DIVIDER_BAND2 (0x0DC) |
| 254 | #define QSERDES_TX_L0_PWM_GEAR_3_DIVIDER_BAND2 (0x0E0) |
| 255 | #define QSERDES_TX_L0_PWM_GEAR_4_DIVIDER_BAND2 (0x0E4) |
| 256 | #define QSERDES_TX_L0_PWM_GEAR_1_DIVIDER_BAND0_1 (0x0E8) |
| 257 | #define QSERDES_TX_L0_PWM_GEAR_2_DIVIDER_BAND0_1 (0x0EC) |
| 258 | #define QSERDES_TX_L0_PWM_GEAR_3_DIVIDER_BAND0_1 (0x0F0) |
| 259 | #define QSERDES_TX_L0_PWM_GEAR_4_DIVIDER_BAND0_1 (0x0F4) |
| 260 | #define QSERDES_TX_L0_VMODE_CTRL1 (0x0F8) |
| 261 | #define QSERDES_TX_L0_VMODE_CTRL2 (0x0FC) |
| 262 | #define QSERDES_TX_L0_TX_ALOG_INTF_OBSV_CNTL (0x100) |
| 263 | #define QSERDES_TX_L0_BIST_STATUS (0x104) |
| 264 | #define QSERDES_TX_L0_BIST_ERROR_COUNT1 (0x108) |
| 265 | #define QSERDES_TX_L0_BIST_ERROR_COUNT2 (0x10C) |
| 266 | #define QSERDES_TX_L0_TX_ALOG_INTF_OBSV (0x110) |
| 267 | |
| 268 | /* HDMI PHY REGISTERS */ |
| 269 | #define HDMI_PHY_BASE_OFFSET (0xC00) |
| 270 | |
| 271 | #define HDMI_PHY_CFG (0x00) |
| 272 | #define HDMI_PHY_PD_CTL (0x04) |
| 273 | #define HDMI_PHY_MODE (0x08) |
| 274 | #define HDMI_PHY_MISR_CLEAR (0x0C) |
| 275 | #define HDMI_PHY_TX0_TX1_BIST_CFG0 (0x10) |
| 276 | #define HDMI_PHY_TX0_TX1_BIST_CFG1 (0x14) |
| 277 | #define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE0 (0x18) |
| 278 | #define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE1 (0x1C) |
| 279 | #define HDMI_PHY_TX0_TX1_BIST_PATTERN0 (0x20) |
| 280 | #define HDMI_PHY_TX0_TX1_BIST_PATTERN1 (0x24) |
| 281 | #define HDMI_PHY_TX2_TX3_BIST_CFG0 (0x28) |
| 282 | #define HDMI_PHY_TX2_TX3_BIST_CFG1 (0x2C) |
| 283 | #define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE0 (0x30) |
| 284 | #define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE1 (0x34) |
| 285 | #define HDMI_PHY_TX2_TX3_BIST_PATTERN0 (0x38) |
| 286 | #define HDMI_PHY_TX2_TX3_BIST_PATTERN1 (0x3C) |
| 287 | #define HDMI_PHY_DEBUG_BUS_SEL (0x40) |
| 288 | #define HDMI_PHY_TXCAL_CFG0 (0x44) |
| 289 | #define HDMI_PHY_TXCAL_CFG1 (0x48) |
| 290 | #define HDMI_PHY_TX0_TX1_LANE_CTL (0x4C) |
| 291 | #define HDMI_PHY_TX2_TX3_LANE_CTL (0x50) |
| 292 | #define HDMI_PHY_LANE_BIST_CONFIG (0x54) |
| 293 | #define HDMI_PHY_CLOCK (0x58) |
| 294 | #define HDMI_PHY_MISC1 (0x5C) |
| 295 | #define HDMI_PHY_MISC2 (0x60) |
| 296 | #define HDMI_PHY_TX0_TX1_BIST_STATUS0 (0x64) |
| 297 | #define HDMI_PHY_TX0_TX1_BIST_STATUS1 (0x68) |
| 298 | #define HDMI_PHY_TX0_TX1_BIST_STATUS2 (0x6C) |
| 299 | #define HDMI_PHY_TX2_TX3_BIST_STATUS0 (0x70) |
| 300 | #define HDMI_PHY_TX2_TX3_BIST_STATUS1 (0x74) |
| 301 | #define HDMI_PHY_TX2_TX3_BIST_STATUS2 (0x78) |
| 302 | #define HDMI_PHY_PRE_MISR_STATUS0 (0x7C) |
| 303 | #define HDMI_PHY_PRE_MISR_STATUS1 (0x80) |
| 304 | #define HDMI_PHY_PRE_MISR_STATUS2 (0x84) |
| 305 | #define HDMI_PHY_PRE_MISR_STATUS3 (0x88) |
| 306 | #define HDMI_PHY_POST_MISR_STATUS0 (0x8C) |
| 307 | #define HDMI_PHY_POST_MISR_STATUS1 (0x90) |
| 308 | #define HDMI_PHY_POST_MISR_STATUS2 (0x94) |
| 309 | #define HDMI_PHY_POST_MISR_STATUS3 (0x98) |
| 310 | #define HDMI_PHY_STATUS (0x9C) |
| 311 | #define HDMI_PHY_MISC3_STATUS (0xA0) |
| 312 | #define HDMI_PHY_MISC4_STATUS (0xA4) |
| 313 | #define HDMI_PHY_DEBUG_BUS0 (0xA8) |
| 314 | #define HDMI_PHY_DEBUG_BUS1 (0xAC) |
| 315 | #define HDMI_PHY_DEBUG_BUS2 (0xB0) |
| 316 | #define HDMI_PHY_DEBUG_BUS3 (0xB4) |
| 317 | #define HDMI_PHY_PHY_REVISION_ID0 (0xB8) |
| 318 | #define HDMI_PHY_PHY_REVISION_ID1 (0xBC) |
| 319 | #define HDMI_PHY_PHY_REVISION_ID2 (0xC0) |
| 320 | #define HDMI_PHY_PHY_REVISION_ID3 (0xC4) |
| 321 | |
| 322 | #define HDMI_PLL_POLL_MAX_READS 100 |
| 323 | #define HDMI_PLL_POLL_TIMEOUT_US 1500 |
| 324 | |
| 325 | enum hdmi_pll_freqs { |
| 326 | HDMI_PCLK_25200_KHZ, |
| 327 | HDMI_PCLK_27027_KHZ, |
| 328 | HDMI_PCLK_27000_KHZ, |
| 329 | HDMI_PCLK_74250_KHZ, |
| 330 | HDMI_PCLK_148500_KHZ, |
| 331 | HDMI_PCLK_154000_KHZ, |
| 332 | HDMI_PCLK_268500_KHZ, |
| 333 | HDMI_PCLK_297000_KHZ, |
| 334 | HDMI_PCLK_594000_KHZ, |
| 335 | HDMI_PCLK_MAX |
| 336 | }; |
| 337 | |
| 338 | struct hdmi_8996_phy_pll_reg_cfg { |
| 339 | u32 tx_l0_lane_mode; |
| 340 | u32 tx_l2_lane_mode; |
| 341 | u32 tx_l0_tx_band; |
| 342 | u32 tx_l1_tx_band; |
| 343 | u32 tx_l2_tx_band; |
| 344 | u32 tx_l3_tx_band; |
| 345 | u32 com_svs_mode_clk_sel; |
| 346 | u32 com_hsclk_sel; |
| 347 | u32 com_pll_cctrl_mode0; |
| 348 | u32 com_pll_rctrl_mode0; |
| 349 | u32 com_cp_ctrl_mode0; |
| 350 | u32 com_dec_start_mode0; |
| 351 | u32 com_div_frac_start1_mode0; |
| 352 | u32 com_div_frac_start2_mode0; |
| 353 | u32 com_div_frac_start3_mode0; |
| 354 | u32 com_integloop_gain0_mode0; |
| 355 | u32 com_integloop_gain1_mode0; |
| 356 | u32 com_lock_cmp_en; |
| 357 | u32 com_lock_cmp1_mode0; |
| 358 | u32 com_lock_cmp2_mode0; |
| 359 | u32 com_lock_cmp3_mode0; |
| 360 | u32 com_core_clk_en; |
| 361 | u32 com_coreclk_div; |
| 362 | u32 com_restrim_ctrl; |
| 363 | u32 com_vco_tune_ctrl; |
| 364 | |
| 365 | u32 tx_l0_tx_drv_lvl; |
| 366 | u32 tx_l0_tx_emp_post1_lvl; |
| 367 | u32 tx_l1_tx_drv_lvl; |
| 368 | u32 tx_l1_tx_emp_post1_lvl; |
| 369 | u32 tx_l2_tx_drv_lvl; |
| 370 | u32 tx_l2_tx_emp_post1_lvl; |
| 371 | u32 tx_l3_tx_drv_lvl; |
| 372 | u32 tx_l3_tx_emp_post1_lvl; |
| 373 | u32 tx_l0_vmode_ctrl1; |
| 374 | u32 tx_l0_vmode_ctrl2; |
| 375 | u32 tx_l1_vmode_ctrl1; |
| 376 | u32 tx_l1_vmode_ctrl2; |
| 377 | u32 tx_l2_vmode_ctrl1; |
| 378 | u32 tx_l2_vmode_ctrl2; |
| 379 | u32 tx_l3_vmode_ctrl1; |
| 380 | u32 tx_l3_vmode_ctrl2; |
| 381 | u32 tx_l0_res_code_lane_tx; |
| 382 | u32 tx_l1_res_code_lane_tx; |
| 383 | u32 tx_l2_res_code_lane_tx; |
| 384 | u32 tx_l3_res_code_lane_tx; |
| 385 | |
| 386 | u32 phy_mode; |
| 387 | }; |
| 388 | |
| 389 | struct hdmi_8996_v3_post_divider { |
| 390 | u64 vco_freq; |
| 391 | u64 hsclk_divsel; |
| 392 | u64 vco_ratio; |
| 393 | u64 tx_band_sel; |
| 394 | u64 half_rate_mode; |
| 395 | }; |
| 396 | |
| 397 | static inline struct hdmi_pll_vco_clk *to_hdmi_8996_vco_clk(struct clk *clk) |
| 398 | { |
| 399 | return container_of(clk, struct hdmi_pll_vco_clk, c); |
| 400 | } |
| 401 | |
| 402 | static inline u64 hdmi_8996_v1_get_post_div_lt_2g(u64 bclk) |
| 403 | { |
| 404 | if (bclk >= HDMI_2400MHZ_BIT_CLK_HZ) |
| 405 | return 2; |
| 406 | else if (bclk >= HDMI_1700MHZ_BIT_CLK_HZ) |
| 407 | return 3; |
| 408 | else if (bclk >= HDMI_1200MHZ_BIT_CLK_HZ) |
| 409 | return 4; |
| 410 | else if (bclk >= HDMI_850MHZ_BIT_CLK_HZ) |
| 411 | return 3; |
| 412 | else if (bclk >= HDMI_600MHZ_BIT_CLK_HZ) |
| 413 | return 4; |
| 414 | else if (bclk >= HDMI_450MHZ_BIT_CLK_HZ) |
| 415 | return 3; |
| 416 | else if (bclk >= HDMI_300MHZ_BIT_CLK_HZ) |
| 417 | return 4; |
| 418 | |
| 419 | return HDMI_64B_ERR_VAL; |
| 420 | } |
| 421 | |
| 422 | static inline u64 hdmi_8996_v2_get_post_div_lt_2g(u64 bclk, u64 vco_range) |
| 423 | { |
| 424 | u64 hdmi_8ghz = vco_range; |
| 425 | u64 tmp_calc; |
| 426 | |
| 427 | hdmi_8ghz <<= 2; |
| 428 | tmp_calc = hdmi_8ghz; |
| 429 | do_div(tmp_calc, 6U); |
| 430 | |
| 431 | if (bclk >= vco_range) |
| 432 | return 2; |
| 433 | else if (bclk >= tmp_calc) |
| 434 | return 3; |
| 435 | else if (bclk >= vco_range >> 1) |
| 436 | return 4; |
| 437 | |
| 438 | tmp_calc = hdmi_8ghz; |
| 439 | do_div(tmp_calc, 12U); |
| 440 | if (bclk >= tmp_calc) |
| 441 | return 3; |
| 442 | else if (bclk >= vco_range >> 2) |
| 443 | return 4; |
| 444 | |
| 445 | tmp_calc = hdmi_8ghz; |
| 446 | do_div(tmp_calc, 24U); |
| 447 | if (bclk >= tmp_calc) |
| 448 | return 3; |
| 449 | else if (bclk >= vco_range >> 3) |
| 450 | return 4; |
| 451 | |
| 452 | return HDMI_64B_ERR_VAL; |
| 453 | } |
| 454 | |
| 455 | static inline u64 hdmi_8996_v2_get_post_div_gt_2g(u64 hsclk) |
| 456 | { |
| 457 | if (hsclk >= 0 && hsclk <= 3) |
| 458 | return hsclk + 1; |
| 459 | |
| 460 | return HDMI_64B_ERR_VAL; |
| 461 | } |
| 462 | |
| 463 | static inline u64 hdmi_8996_get_coreclk_div_lt_2g(u64 bclk) |
| 464 | { |
| 465 | if (bclk >= HDMI_1334MHZ_BIT_CLK_HZ) |
| 466 | return 1; |
| 467 | else if (bclk >= HDMI_1000MHZ_BIT_CLK_HZ) |
| 468 | return 1; |
| 469 | else if (bclk >= HDMI_667MHZ_BIT_CLK_HZ) |
| 470 | return 2; |
| 471 | else if (bclk >= HDMI_500MHZ_BIT_CLK_HZ) |
| 472 | return 2; |
| 473 | else if (bclk >= HDMI_334MHZ_BIT_CLK_HZ) |
| 474 | return 3; |
| 475 | else if (bclk >= HDMI_250MHZ_BIT_CLK_HZ) |
| 476 | return 3; |
| 477 | |
| 478 | return HDMI_64B_ERR_VAL; |
| 479 | } |
| 480 | |
| 481 | static inline u64 hdmi_8996_get_coreclk_div_ratio(u64 clks_pll_divsel, |
| 482 | u64 coreclk_div) |
| 483 | { |
| 484 | if (clks_pll_divsel == 0) |
| 485 | return coreclk_div*2; |
| 486 | else if (clks_pll_divsel == 1) |
| 487 | return coreclk_div*4; |
| 488 | |
| 489 | return HDMI_64B_ERR_VAL; |
| 490 | } |
| 491 | |
| 492 | static inline u64 hdmi_8996_v1_get_tx_band(u64 bclk) |
| 493 | { |
| 494 | if (bclk >= 2400000000UL) |
| 495 | return 0; |
| 496 | if (bclk >= 1200000000UL) |
| 497 | return 1; |
| 498 | if (bclk >= 600000000UL) |
| 499 | return 2; |
| 500 | if (bclk >= 300000000UL) |
| 501 | return 3; |
| 502 | |
| 503 | return HDMI_64B_ERR_VAL; |
| 504 | } |
| 505 | |
| 506 | static inline u64 hdmi_8996_v2_get_tx_band(u64 bclk, u64 vco_range) |
| 507 | { |
| 508 | if (bclk >= vco_range) |
| 509 | return 0; |
| 510 | else if (bclk >= vco_range >> 1) |
| 511 | return 1; |
| 512 | else if (bclk >= vco_range >> 2) |
| 513 | return 2; |
| 514 | else if (bclk >= vco_range >> 3) |
| 515 | return 3; |
| 516 | |
| 517 | return HDMI_64B_ERR_VAL; |
| 518 | } |
| 519 | |
| 520 | static inline u64 hdmi_8996_v1_get_hsclk(u64 fdata) |
| 521 | { |
| 522 | if (fdata >= 9600000000UL) |
| 523 | return 0; |
| 524 | else if (fdata >= 4800000000UL) |
| 525 | return 1; |
| 526 | else if (fdata >= 3200000000UL) |
| 527 | return 2; |
| 528 | else if (fdata >= 2400000000UL) |
| 529 | return 3; |
| 530 | |
| 531 | return HDMI_64B_ERR_VAL; |
| 532 | } |
| 533 | |
| 534 | static inline u64 hdmi_8996_v2_get_hsclk(u64 fdata, u64 vco_range) |
| 535 | { |
| 536 | u64 tmp_calc = vco_range; |
| 537 | |
| 538 | tmp_calc <<= 2; |
| 539 | do_div(tmp_calc, 3U); |
| 540 | if (fdata >= (vco_range << 2)) |
| 541 | return 0; |
| 542 | else if (fdata >= (vco_range << 1)) |
| 543 | return 1; |
| 544 | else if (fdata >= tmp_calc) |
| 545 | return 2; |
| 546 | else if (fdata >= vco_range) |
| 547 | return 3; |
| 548 | |
| 549 | return HDMI_64B_ERR_VAL; |
| 550 | |
| 551 | } |
| 552 | |
| 553 | static inline u64 hdmi_8996_v2_get_vco_freq(u64 bclk, u64 vco_range) |
| 554 | { |
| 555 | u64 tx_band_div_ratio = 1U << hdmi_8996_v2_get_tx_band(bclk, vco_range); |
| 556 | u64 pll_post_div_ratio; |
| 557 | |
| 558 | if (bclk >= vco_range) { |
| 559 | u64 hsclk = hdmi_8996_v2_get_hsclk(bclk, vco_range); |
| 560 | |
| 561 | pll_post_div_ratio = hdmi_8996_v2_get_post_div_gt_2g(hsclk); |
| 562 | } else { |
| 563 | pll_post_div_ratio = hdmi_8996_v2_get_post_div_lt_2g(bclk, |
| 564 | vco_range); |
| 565 | } |
| 566 | |
| 567 | return bclk * (pll_post_div_ratio * tx_band_div_ratio); |
| 568 | } |
| 569 | |
| 570 | static inline u64 hdmi_8996_v2_get_fdata(u64 bclk, u64 vco_range) |
| 571 | { |
| 572 | if (bclk >= vco_range) |
| 573 | return bclk; |
| 574 | |
| 575 | { |
| 576 | u64 tmp_calc = hdmi_8996_v2_get_vco_freq(bclk, vco_range); |
| 577 | u64 pll_post_div_ratio_lt_2g = hdmi_8996_v2_get_post_div_lt_2g( |
| 578 | bclk, vco_range); |
| 579 | if (pll_post_div_ratio_lt_2g == HDMI_64B_ERR_VAL) |
| 580 | return HDMI_64B_ERR_VAL; |
| 581 | |
| 582 | do_div(tmp_calc, pll_post_div_ratio_lt_2g); |
| 583 | return tmp_calc; |
| 584 | } |
| 585 | } |
| 586 | |
| 587 | static inline u64 hdmi_8996_get_cpctrl(u64 frac_start, bool gen_ssc) |
| 588 | { |
| 589 | if ((frac_start != 0) || |
| 590 | (gen_ssc == true)) |
| 591 | /* |
| 592 | * This should be ROUND(11/(19.2/20))). |
| 593 | * Since ref clock does not change, hardcoding to 11 |
| 594 | */ |
| 595 | return 0xB; |
| 596 | |
| 597 | return 0x23; |
| 598 | } |
| 599 | |
| 600 | static inline u64 hdmi_8996_get_rctrl(u64 frac_start, bool gen_ssc) |
| 601 | { |
| 602 | if ((frac_start != 0) || (gen_ssc == true)) |
| 603 | return 0x16; |
| 604 | |
| 605 | return 0x10; |
| 606 | } |
| 607 | |
| 608 | static inline u64 hdmi_8996_get_cctrl(u64 frac_start, bool gen_ssc) |
| 609 | { |
| 610 | if ((frac_start != 0) || (gen_ssc == true)) |
| 611 | return 0x28; |
| 612 | |
| 613 | return 0x1; |
| 614 | } |
| 615 | |
| 616 | static inline u64 hdmi_8996_get_integloop_gain(u64 frac_start, bool gen_ssc) |
| 617 | { |
| 618 | if ((frac_start != 0) || (gen_ssc == true)) |
| 619 | return 0x80; |
| 620 | |
| 621 | return 0xC4; |
| 622 | } |
| 623 | |
| 624 | static inline u64 hdmi_8996_v3_get_integloop_gain(u64 frac_start, u64 bclk, |
| 625 | bool gen_ssc) |
| 626 | { |
| 627 | u64 digclk_divsel = bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2; |
| 628 | u64 base = ((frac_start != 0) || (gen_ssc == true)) ? 0x40 : 0xC4; |
| 629 | |
| 630 | base <<= digclk_divsel; |
| 631 | |
| 632 | return (base <= 2046 ? base : 0x7FE); |
| 633 | } |
| 634 | |
| 635 | static inline u64 hdmi_8996_get_vco_tune(u64 fdata, u64 div) |
| 636 | { |
| 637 | u64 vco_tune; |
| 638 | |
| 639 | vco_tune = fdata * div; |
| 640 | do_div(vco_tune, 1000000); |
| 641 | vco_tune = 13000 - vco_tune - 256; |
| 642 | do_div(vco_tune, 5); |
| 643 | |
| 644 | return vco_tune; |
| 645 | } |
| 646 | |
| 647 | static inline u64 hdmi_8996_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk) |
| 648 | { |
| 649 | u64 pll_cmp; |
| 650 | u64 rem; |
| 651 | |
| 652 | pll_cmp = pll_cmp_cnt * core_clk; |
| 653 | rem = do_div(pll_cmp, HDMI_REF_CLOCK); |
| 654 | if (rem > (HDMI_REF_CLOCK >> 1)) |
| 655 | pll_cmp++; |
| 656 | pll_cmp -= 1; |
| 657 | |
| 658 | return pll_cmp; |
| 659 | } |
| 660 | |
| 661 | static inline u64 hdmi_8996_v3_get_pll_cmp(u64 pll_cmp_cnt, u64 fdata) |
| 662 | { |
| 663 | u64 dividend = pll_cmp_cnt * fdata; |
| 664 | u64 divisor = HDMI_REF_CLOCK * 10; |
| 665 | u64 rem; |
| 666 | |
| 667 | rem = do_div(dividend, divisor); |
| 668 | if (rem > (divisor >> 1)) |
| 669 | dividend++; |
| 670 | |
| 671 | return dividend - 1; |
| 672 | } |
| 673 | |
| 674 | static int hdmi_8996_v3_get_post_div(struct hdmi_8996_v3_post_divider *pd, |
| 675 | u64 bclk) |
| 676 | { |
| 677 | u32 ratio[] = {2, 3, 4, 5, 6, 9, 10, 12, 14, 15, 20, 21, 25, 28, 35}; |
| 678 | u32 tx_band_sel[] = {0, 1, 2, 3}; |
| 679 | u64 vco_freq[60]; |
| 680 | u64 vco, vco_optimal, half_rate_mode = 0; |
| 681 | int vco_optimal_index, vco_freq_index; |
| 682 | int i, j, k, x; |
| 683 | |
| 684 | for (i = 0; i <= 1; i++) { |
| 685 | vco_optimal = HDMI_VCO_MAX_FREQ; |
| 686 | vco_optimal_index = -1; |
| 687 | vco_freq_index = 0; |
| 688 | for (j = 0; j < 15; j++) { |
| 689 | for (k = 0; k < 4; k++) { |
| 690 | u64 ratio_mult = ratio[j] << tx_band_sel[k]; |
| 691 | |
| 692 | vco = bclk >> half_rate_mode; |
| 693 | vco *= ratio_mult; |
| 694 | vco_freq[vco_freq_index++] = vco; |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | for (x = 0; x < 60; x++) { |
| 699 | u64 vco_tmp = vco_freq[x]; |
| 700 | |
| 701 | if ((vco_tmp >= HDMI_VCO_MIN_FREQ) && |
| 702 | (vco_tmp <= vco_optimal)) { |
| 703 | vco_optimal = vco_tmp; |
| 704 | vco_optimal_index = x; |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | if (vco_optimal_index == -1) { |
| 709 | if (!half_rate_mode) |
| 710 | half_rate_mode++; |
| 711 | else |
| 712 | return -EINVAL; |
| 713 | } else { |
| 714 | pd->vco_freq = vco_optimal; |
| 715 | pd->tx_band_sel = tx_band_sel[vco_optimal_index % 4]; |
| 716 | pd->vco_ratio = ratio[vco_optimal_index / 4]; |
| 717 | break; |
| 718 | } |
| 719 | } |
| 720 | |
| 721 | switch (pd->vco_ratio) { |
| 722 | case 2: |
| 723 | pd->hsclk_divsel = 0; |
| 724 | break; |
| 725 | case 3: |
| 726 | pd->hsclk_divsel = 4; |
| 727 | break; |
| 728 | case 4: |
| 729 | pd->hsclk_divsel = 8; |
| 730 | break; |
| 731 | case 5: |
| 732 | pd->hsclk_divsel = 12; |
| 733 | break; |
| 734 | case 6: |
| 735 | pd->hsclk_divsel = 1; |
| 736 | break; |
| 737 | case 9: |
| 738 | pd->hsclk_divsel = 5; |
| 739 | break; |
| 740 | case 10: |
| 741 | pd->hsclk_divsel = 2; |
| 742 | break; |
| 743 | case 12: |
| 744 | pd->hsclk_divsel = 9; |
| 745 | break; |
| 746 | case 14: |
| 747 | pd->hsclk_divsel = 3; |
| 748 | break; |
| 749 | case 15: |
| 750 | pd->hsclk_divsel = 13; |
| 751 | break; |
| 752 | case 20: |
| 753 | pd->hsclk_divsel = 10; |
| 754 | break; |
| 755 | case 21: |
| 756 | pd->hsclk_divsel = 7; |
| 757 | break; |
| 758 | case 25: |
| 759 | pd->hsclk_divsel = 14; |
| 760 | break; |
| 761 | case 28: |
| 762 | pd->hsclk_divsel = 11; |
| 763 | break; |
| 764 | case 35: |
| 765 | pd->hsclk_divsel = 15; |
| 766 | break; |
| 767 | }; |
| 768 | |
| 769 | return 0; |
| 770 | } |
| 771 | |
| 772 | static int hdmi_8996_v1_calculate(u32 pix_clk, |
| 773 | struct hdmi_8996_phy_pll_reg_cfg *cfg) |
| 774 | { |
| 775 | int rc = -EINVAL; |
| 776 | u64 fdata, clk_divtx, tmds_clk; |
| 777 | u64 bclk; |
| 778 | u64 post_div_gt_2g; |
| 779 | u64 post_div_lt_2g; |
| 780 | u64 coreclk_div1_lt_2g; |
| 781 | u64 core_clk_div_ratio; |
| 782 | u64 core_clk; |
| 783 | u64 pll_cmp; |
| 784 | u64 tx_band; |
| 785 | u64 tx_band_div_ratio; |
| 786 | u64 hsclk; |
| 787 | u64 dec_start; |
| 788 | u64 frac_start; |
| 789 | u64 pll_divisor = 4 * HDMI_REF_CLOCK; |
| 790 | u64 cpctrl; |
| 791 | u64 rctrl; |
| 792 | u64 cctrl; |
| 793 | u64 integloop_gain; |
| 794 | u64 vco_tune; |
| 795 | u64 vco_freq; |
| 796 | u64 rem; |
| 797 | |
| 798 | /* FDATA, CLK_DIVTX, PIXEL_CLK, TMDS_CLK */ |
| 799 | bclk = ((u64)pix_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; |
| 800 | |
| 801 | if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) |
| 802 | tmds_clk = bclk/4; |
| 803 | else |
| 804 | tmds_clk = bclk; |
| 805 | |
| 806 | post_div_lt_2g = hdmi_8996_v1_get_post_div_lt_2g(bclk); |
| 807 | if (post_div_lt_2g == HDMI_64B_ERR_VAL) |
| 808 | goto fail; |
| 809 | |
| 810 | coreclk_div1_lt_2g = hdmi_8996_get_coreclk_div_lt_2g(bclk); |
| 811 | |
| 812 | core_clk_div_ratio = hdmi_8996_get_coreclk_div_ratio( |
| 813 | HDMI_CLKS_PLL_DIVSEL, HDMI_CORECLK_DIV); |
| 814 | |
| 815 | tx_band = hdmi_8996_v1_get_tx_band(bclk); |
| 816 | if (tx_band == HDMI_64B_ERR_VAL) |
| 817 | goto fail; |
| 818 | |
| 819 | tx_band_div_ratio = 1 << tx_band; |
| 820 | |
| 821 | if (bclk >= HDMI_2400MHZ_BIT_CLK_HZ) { |
| 822 | fdata = bclk; |
| 823 | hsclk = hdmi_8996_v1_get_hsclk(fdata); |
| 824 | if (hsclk == HDMI_64B_ERR_VAL) |
| 825 | goto fail; |
| 826 | |
| 827 | post_div_gt_2g = (hsclk <= 3) ? (hsclk + 1) : HDMI_64B_ERR_VAL; |
| 828 | if (post_div_gt_2g == HDMI_64B_ERR_VAL) |
| 829 | goto fail; |
| 830 | |
| 831 | vco_freq = bclk * (post_div_gt_2g * tx_band_div_ratio); |
| 832 | clk_divtx = vco_freq; |
| 833 | do_div(clk_divtx, post_div_gt_2g); |
| 834 | } else { |
| 835 | vco_freq = bclk * (post_div_lt_2g * tx_band_div_ratio); |
| 836 | fdata = vco_freq; |
| 837 | do_div(fdata, post_div_lt_2g); |
| 838 | hsclk = hdmi_8996_v1_get_hsclk(fdata); |
| 839 | if (hsclk == HDMI_64B_ERR_VAL) |
| 840 | goto fail; |
| 841 | |
| 842 | clk_divtx = vco_freq; |
| 843 | do_div(clk_divtx, post_div_lt_2g); |
| 844 | post_div_gt_2g = (hsclk <= 3) ? (hsclk + 1) : HDMI_64B_ERR_VAL; |
| 845 | if (post_div_gt_2g == HDMI_64B_ERR_VAL) |
| 846 | goto fail; |
| 847 | } |
| 848 | |
| 849 | /* Decimal and fraction values */ |
| 850 | dec_start = fdata * post_div_gt_2g; |
| 851 | do_div(dec_start, pll_divisor); |
| 852 | frac_start = ((pll_divisor - (((dec_start + 1) * pll_divisor) - |
| 853 | (fdata * post_div_gt_2g))) * (1 << 20)); |
| 854 | rem = do_div(frac_start, pll_divisor); |
| 855 | /* Round off frac_start to closest integer */ |
| 856 | if (rem >= (pll_divisor >> 1)) |
| 857 | frac_start++; |
| 858 | |
| 859 | cpctrl = hdmi_8996_get_cpctrl(frac_start, false); |
| 860 | rctrl = hdmi_8996_get_rctrl(frac_start, false); |
| 861 | cctrl = hdmi_8996_get_cctrl(frac_start, false); |
| 862 | integloop_gain = hdmi_8996_get_integloop_gain(frac_start, false); |
| 863 | vco_tune = hdmi_8996_get_vco_tune(fdata, post_div_gt_2g); |
| 864 | |
| 865 | core_clk = clk_divtx; |
| 866 | do_div(core_clk, core_clk_div_ratio); |
| 867 | pll_cmp = hdmi_8996_get_pll_cmp(1024, core_clk); |
| 868 | |
| 869 | /* Debug dump */ |
| 870 | DEV_DBG("%s: VCO freq: %llu\n", __func__, vco_freq); |
| 871 | DEV_DBG("%s: fdata: %llu\n", __func__, fdata); |
| 872 | DEV_DBG("%s: CLK_DIVTX: %llu\n", __func__, clk_divtx); |
| 873 | DEV_DBG("%s: pix_clk: %d\n", __func__, pix_clk); |
| 874 | DEV_DBG("%s: tmds clk: %llu\n", __func__, tmds_clk); |
| 875 | DEV_DBG("%s: HSCLK_SEL: %llu\n", __func__, hsclk); |
| 876 | DEV_DBG("%s: DEC_START: %llu\n", __func__, dec_start); |
| 877 | DEV_DBG("%s: DIV_FRAC_START: %llu\n", __func__, frac_start); |
| 878 | DEV_DBG("%s: PLL_CPCTRL: %llu\n", __func__, cpctrl); |
| 879 | DEV_DBG("%s: PLL_RCTRL: %llu\n", __func__, rctrl); |
| 880 | DEV_DBG("%s: PLL_CCTRL: %llu\n", __func__, cctrl); |
| 881 | DEV_DBG("%s: INTEGLOOP_GAIN: %llu\n", __func__, integloop_gain); |
| 882 | DEV_DBG("%s: VCO_TUNE: %llu\n", __func__, vco_tune); |
| 883 | DEV_DBG("%s: TX_BAND: %llu\n", __func__, tx_band); |
| 884 | DEV_DBG("%s: PLL_CMP: %llu\n", __func__, pll_cmp); |
| 885 | |
| 886 | /* Convert these values to register specific values */ |
| 887 | cfg->tx_l0_lane_mode = 0x3; |
| 888 | cfg->tx_l2_lane_mode = 0x3; |
| 889 | cfg->tx_l0_tx_band = tx_band + 4; |
| 890 | cfg->tx_l1_tx_band = tx_band + 4; |
| 891 | cfg->tx_l2_tx_band = tx_band + 4; |
| 892 | cfg->tx_l3_tx_band = tx_band + 4; |
| 893 | cfg->tx_l0_res_code_lane_tx = 0x33; |
| 894 | cfg->tx_l1_res_code_lane_tx = 0x33; |
| 895 | cfg->tx_l2_res_code_lane_tx = 0x33; |
| 896 | cfg->tx_l3_res_code_lane_tx = 0x33; |
| 897 | cfg->com_restrim_ctrl = 0x0; |
| 898 | cfg->com_vco_tune_ctrl = 0x1C; |
| 899 | |
| 900 | cfg->com_svs_mode_clk_sel = |
| 901 | (bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2); |
| 902 | cfg->com_hsclk_sel = (0x28 | hsclk); |
| 903 | cfg->com_pll_cctrl_mode0 = cctrl; |
| 904 | cfg->com_pll_rctrl_mode0 = rctrl; |
| 905 | cfg->com_cp_ctrl_mode0 = cpctrl; |
| 906 | cfg->com_dec_start_mode0 = dec_start; |
| 907 | cfg->com_div_frac_start1_mode0 = (frac_start & 0xFF); |
| 908 | cfg->com_div_frac_start2_mode0 = ((frac_start & 0xFF00) >> 8); |
| 909 | cfg->com_div_frac_start3_mode0 = ((frac_start & 0xF0000) >> 16); |
| 910 | cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xFF); |
| 911 | cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xF00) >> 8); |
| 912 | cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xFF); |
| 913 | cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8); |
| 914 | cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); |
| 915 | cfg->com_core_clk_en = (0x6C | (HDMI_CLKS_PLL_DIVSEL << 4)); |
| 916 | cfg->com_coreclk_div = HDMI_CORECLK_DIV; |
| 917 | |
| 918 | if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { |
| 919 | cfg->tx_l0_tx_drv_lvl = 0x25; |
| 920 | cfg->tx_l0_tx_emp_post1_lvl = 0x23; |
| 921 | cfg->tx_l1_tx_drv_lvl = 0x25; |
| 922 | cfg->tx_l1_tx_emp_post1_lvl = 0x23; |
| 923 | cfg->tx_l2_tx_drv_lvl = 0x25; |
| 924 | cfg->tx_l2_tx_emp_post1_lvl = 0x23; |
| 925 | cfg->tx_l3_tx_drv_lvl = 0x22; |
| 926 | cfg->tx_l3_tx_emp_post1_lvl = 0x27; |
| 927 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 928 | cfg->tx_l0_vmode_ctrl2 = 0x0D; |
| 929 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 930 | cfg->tx_l1_vmode_ctrl2 = 0x0D; |
| 931 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 932 | cfg->tx_l2_vmode_ctrl2 = 0x0D; |
| 933 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 934 | cfg->tx_l3_vmode_ctrl2 = 0x00; |
| 935 | cfg->com_restrim_ctrl = 0x0; |
| 936 | } else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) { |
| 937 | cfg->tx_l0_tx_drv_lvl = 0x25; |
| 938 | cfg->tx_l0_tx_emp_post1_lvl = 0x23; |
| 939 | cfg->tx_l1_tx_drv_lvl = 0x25; |
| 940 | cfg->tx_l1_tx_emp_post1_lvl = 0x23; |
| 941 | cfg->tx_l2_tx_drv_lvl = 0x25; |
| 942 | cfg->tx_l2_tx_emp_post1_lvl = 0x23; |
| 943 | cfg->tx_l3_tx_drv_lvl = 0x25; |
| 944 | cfg->tx_l3_tx_emp_post1_lvl = 0x23; |
| 945 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 946 | cfg->tx_l0_vmode_ctrl2 = 0x0D; |
| 947 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 948 | cfg->tx_l1_vmode_ctrl2 = 0x0D; |
| 949 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 950 | cfg->tx_l2_vmode_ctrl2 = 0x0D; |
| 951 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 952 | cfg->tx_l3_vmode_ctrl2 = 0x00; |
| 953 | cfg->com_restrim_ctrl = 0x0; |
| 954 | } else { |
| 955 | cfg->tx_l0_tx_drv_lvl = 0x20; |
| 956 | cfg->tx_l0_tx_emp_post1_lvl = 0x20; |
| 957 | cfg->tx_l1_tx_drv_lvl = 0x20; |
| 958 | cfg->tx_l1_tx_emp_post1_lvl = 0x20; |
| 959 | cfg->tx_l2_tx_drv_lvl = 0x20; |
| 960 | cfg->tx_l2_tx_emp_post1_lvl = 0x20; |
| 961 | cfg->tx_l3_tx_drv_lvl = 0x20; |
| 962 | cfg->tx_l3_tx_emp_post1_lvl = 0x20; |
| 963 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 964 | cfg->tx_l0_vmode_ctrl2 = 0x0E; |
| 965 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 966 | cfg->tx_l1_vmode_ctrl2 = 0x0E; |
| 967 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 968 | cfg->tx_l2_vmode_ctrl2 = 0x0E; |
| 969 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 970 | cfg->tx_l3_vmode_ctrl2 = 0x0E; |
| 971 | cfg->com_restrim_ctrl = 0xD8; |
| 972 | } |
| 973 | |
| 974 | cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; |
| 975 | DEV_DBG("HDMI 8996 PLL: PLL Settings\n"); |
| 976 | DEV_DBG("PLL PARAM: tx_l0_lane_mode = 0x%x\n", cfg->tx_l0_lane_mode); |
| 977 | DEV_DBG("PLL PARAM: tx_l2_lane_mode = 0x%x\n", cfg->tx_l2_lane_mode); |
| 978 | DEV_DBG("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band); |
| 979 | DEV_DBG("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band); |
| 980 | DEV_DBG("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band); |
| 981 | DEV_DBG("PLL PARAM: tx_l3_tx_band = 0x%x\n", cfg->tx_l3_tx_band); |
| 982 | DEV_DBG("PLL PARAM: com_svs_mode_clk_sel = 0x%x\n", |
| 983 | cfg->com_svs_mode_clk_sel); |
| 984 | DEV_DBG("PLL PARAM: com_hsclk_sel = 0x%x\n", cfg->com_hsclk_sel); |
| 985 | DEV_DBG("PLL PARAM: com_pll_cctrl_mode0 = 0x%x\n", |
| 986 | cfg->com_pll_cctrl_mode0); |
| 987 | DEV_DBG("PLL PARAM: com_pll_rctrl_mode0 = 0x%x\n", |
| 988 | cfg->com_pll_rctrl_mode0); |
| 989 | DEV_DBG("PLL PARAM: com_cp_ctrl_mode0 = 0x%x\n", |
| 990 | cfg->com_cp_ctrl_mode0); |
| 991 | DEV_DBG("PLL PARAM: com_dec_start_mode0 = 0x%x\n", |
| 992 | cfg->com_dec_start_mode0); |
| 993 | DEV_DBG("PLL PARAM: com_div_frac_start1_mode0 = 0x%x\n", |
| 994 | cfg->com_div_frac_start1_mode0); |
| 995 | DEV_DBG("PLL PARAM: com_div_frac_start2_mode0 = 0x%x\n", |
| 996 | cfg->com_div_frac_start2_mode0); |
| 997 | DEV_DBG("PLL PARAM: com_div_frac_start3_mode0 = 0x%x\n", |
| 998 | cfg->com_div_frac_start3_mode0); |
| 999 | DEV_DBG("PLL PARAM: com_integloop_gain0_mode0 = 0x%x\n", |
| 1000 | cfg->com_integloop_gain0_mode0); |
| 1001 | DEV_DBG("PLL PARAM: com_integloop_gain1_mode0 = 0x%x\n", |
| 1002 | cfg->com_integloop_gain1_mode0); |
| 1003 | DEV_DBG("PLL PARAM: com_lock_cmp1_mode0 = 0x%x\n", |
| 1004 | cfg->com_lock_cmp1_mode0); |
| 1005 | DEV_DBG("PLL PARAM: com_lock_cmp2_mode0 = 0x%x\n", |
| 1006 | cfg->com_lock_cmp2_mode0); |
| 1007 | DEV_DBG("PLL PARAM: com_lock_cmp3_mode0 = 0x%x\n", |
| 1008 | cfg->com_lock_cmp3_mode0); |
| 1009 | DEV_DBG("PLL PARAM: com_core_clk_en = 0x%x\n", cfg->com_core_clk_en); |
| 1010 | DEV_DBG("PLL PARAM: com_coreclk_div = 0x%x\n", cfg->com_coreclk_div); |
| 1011 | DEV_DBG("PLL PARAM: com_restrim_ctrl = 0x%x\n", cfg->com_restrim_ctrl); |
| 1012 | |
| 1013 | DEV_DBG("PLL PARAM: l0_tx_drv_lvl = 0x%x\n", cfg->tx_l0_tx_drv_lvl); |
| 1014 | DEV_DBG("PLL PARAM: l0_tx_emp_post1_lvl = 0x%x\n", |
| 1015 | cfg->tx_l0_tx_emp_post1_lvl); |
| 1016 | DEV_DBG("PLL PARAM: l1_tx_drv_lvl = 0x%x\n", cfg->tx_l1_tx_drv_lvl); |
| 1017 | DEV_DBG("PLL PARAM: l1_tx_emp_post1_lvl = 0x%x\n", |
| 1018 | cfg->tx_l1_tx_emp_post1_lvl); |
| 1019 | DEV_DBG("PLL PARAM: l2_tx_drv_lvl = 0x%x\n", cfg->tx_l2_tx_drv_lvl); |
| 1020 | DEV_DBG("PLL PARAM: l2_tx_emp_post1_lvl = 0x%x\n", |
| 1021 | cfg->tx_l2_tx_emp_post1_lvl); |
| 1022 | DEV_DBG("PLL PARAM: l3_tx_drv_lvl = 0x%x\n", cfg->tx_l3_tx_drv_lvl); |
| 1023 | DEV_DBG("PLL PARAM: l3_tx_emp_post1_lvl = 0x%x\n", |
| 1024 | cfg->tx_l3_tx_emp_post1_lvl); |
| 1025 | |
| 1026 | DEV_DBG("PLL PARAM: l0_vmode_ctrl1 = 0x%x\n", cfg->tx_l0_vmode_ctrl1); |
| 1027 | DEV_DBG("PLL PARAM: l0_vmode_ctrl2 = 0x%x\n", cfg->tx_l0_vmode_ctrl2); |
| 1028 | DEV_DBG("PLL PARAM: l1_vmode_ctrl1 = 0x%x\n", cfg->tx_l1_vmode_ctrl1); |
| 1029 | DEV_DBG("PLL PARAM: l1_vmode_ctrl2 = 0x%x\n", cfg->tx_l1_vmode_ctrl2); |
| 1030 | DEV_DBG("PLL PARAM: l2_vmode_ctrl1 = 0x%x\n", cfg->tx_l2_vmode_ctrl1); |
| 1031 | DEV_DBG("PLL PARAM: l2_vmode_ctrl2 = 0x%x\n", cfg->tx_l2_vmode_ctrl2); |
| 1032 | DEV_DBG("PLL PARAM: l3_vmode_ctrl1 = 0x%x\n", cfg->tx_l3_vmode_ctrl1); |
| 1033 | DEV_DBG("PLL PARAM: l3_vmode_ctrl2 = 0x%x\n", cfg->tx_l3_vmode_ctrl2); |
| 1034 | DEV_DBG("PLL PARAM: tx_l0_res_code_lane_tx = 0x%x\n", |
| 1035 | cfg->tx_l0_res_code_lane_tx); |
| 1036 | DEV_DBG("PLL PARAM: tx_l1_res_code_lane_tx = 0x%x\n", |
| 1037 | cfg->tx_l1_res_code_lane_tx); |
| 1038 | DEV_DBG("PLL PARAM: tx_l2_res_code_lane_tx = 0x%x\n", |
| 1039 | cfg->tx_l2_res_code_lane_tx); |
| 1040 | DEV_DBG("PLL PARAM: tx_l3_res_code_lane_tx = 0x%x\n", |
| 1041 | cfg->tx_l3_res_code_lane_tx); |
| 1042 | |
| 1043 | DEV_DBG("PLL PARAM: phy_mode = 0x%x\n", cfg->phy_mode); |
| 1044 | rc = 0; |
| 1045 | fail: |
| 1046 | return rc; |
| 1047 | } |
| 1048 | |
| 1049 | static int hdmi_8996_v2_calculate(u32 pix_clk, |
| 1050 | struct hdmi_8996_phy_pll_reg_cfg *cfg) |
| 1051 | { |
| 1052 | int rc = -EINVAL; |
| 1053 | u64 fdata, clk_divtx, tmds_clk; |
| 1054 | u64 bclk; |
| 1055 | u64 post_div; |
| 1056 | u64 core_clk_div; |
| 1057 | u64 core_clk_div_ratio; |
| 1058 | u64 core_clk; |
| 1059 | u64 pll_cmp; |
| 1060 | u64 tx_band; |
| 1061 | u64 tx_band_div_ratio; |
| 1062 | u64 hsclk; |
| 1063 | u64 dec_start; |
| 1064 | u64 frac_start; |
| 1065 | u64 pll_divisor = 4 * HDMI_REF_CLOCK; |
| 1066 | u64 cpctrl; |
| 1067 | u64 rctrl; |
| 1068 | u64 cctrl; |
| 1069 | u64 integloop_gain; |
| 1070 | u64 vco_tune; |
| 1071 | u64 vco_freq; |
| 1072 | u64 vco_range; |
| 1073 | u64 rem; |
| 1074 | |
| 1075 | /* FDATA, CLK_DIVTX, PIXEL_CLK, TMDS_CLK */ |
| 1076 | bclk = ((u64)pix_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; |
| 1077 | |
| 1078 | if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) |
| 1079 | tmds_clk = pix_clk >> 2; |
| 1080 | else |
| 1081 | tmds_clk = pix_clk; |
| 1082 | |
| 1083 | vco_range = bclk < HDMI_282MHZ_BIT_CLK_HZ ? HDMI_2000MHZ_BIT_CLK_HZ : |
| 1084 | HDMI_2250MHZ_BIT_CLK_HZ; |
| 1085 | |
| 1086 | fdata = hdmi_8996_v2_get_fdata(bclk, vco_range); |
| 1087 | if (fdata == HDMI_64B_ERR_VAL) |
| 1088 | goto fail; |
| 1089 | |
| 1090 | hsclk = hdmi_8996_v2_get_hsclk(fdata, vco_range); |
| 1091 | if (hsclk == HDMI_64B_ERR_VAL) |
| 1092 | goto fail; |
| 1093 | |
| 1094 | if (bclk >= vco_range) |
| 1095 | post_div = hdmi_8996_v2_get_post_div_gt_2g(hsclk); |
| 1096 | else |
| 1097 | post_div = hdmi_8996_v2_get_post_div_lt_2g(bclk, vco_range); |
| 1098 | |
| 1099 | if (post_div == HDMI_64B_ERR_VAL) |
| 1100 | goto fail; |
| 1101 | |
| 1102 | core_clk_div = 5; |
| 1103 | core_clk_div_ratio = core_clk_div * 2; |
| 1104 | |
| 1105 | tx_band = hdmi_8996_v2_get_tx_band(bclk, vco_range); |
| 1106 | if (tx_band == HDMI_64B_ERR_VAL) |
| 1107 | goto fail; |
| 1108 | |
| 1109 | tx_band_div_ratio = 1 << tx_band; |
| 1110 | |
| 1111 | vco_freq = hdmi_8996_v2_get_vco_freq(bclk, vco_range); |
| 1112 | clk_divtx = vco_freq; |
| 1113 | do_div(clk_divtx, post_div); |
| 1114 | |
| 1115 | /* Decimal and fraction values */ |
| 1116 | dec_start = fdata * post_div; |
| 1117 | do_div(dec_start, pll_divisor); |
| 1118 | frac_start = ((pll_divisor - (((dec_start + 1) * pll_divisor) - |
| 1119 | (fdata * post_div))) * (1 << 20)); |
| 1120 | rem = do_div(frac_start, pll_divisor); |
| 1121 | /* Round off frac_start to closest integer */ |
| 1122 | if (rem >= (pll_divisor >> 1)) |
| 1123 | frac_start++; |
| 1124 | |
| 1125 | cpctrl = hdmi_8996_get_cpctrl(frac_start, false); |
| 1126 | rctrl = hdmi_8996_get_rctrl(frac_start, false); |
| 1127 | cctrl = hdmi_8996_get_cctrl(frac_start, false); |
| 1128 | integloop_gain = hdmi_8996_get_integloop_gain(frac_start, false); |
| 1129 | vco_tune = hdmi_8996_get_vco_tune(fdata, post_div); |
| 1130 | |
| 1131 | core_clk = clk_divtx; |
| 1132 | do_div(core_clk, core_clk_div_ratio); |
| 1133 | pll_cmp = hdmi_8996_get_pll_cmp(1024, core_clk); |
| 1134 | |
| 1135 | /* Debug dump */ |
| 1136 | DEV_DBG("%s: VCO freq: %llu\n", __func__, vco_freq); |
| 1137 | DEV_DBG("%s: fdata: %llu\n", __func__, fdata); |
| 1138 | DEV_DBG("%s: CLK_DIVTX: %llu\n", __func__, clk_divtx); |
| 1139 | DEV_DBG("%s: pix_clk: %d\n", __func__, pix_clk); |
| 1140 | DEV_DBG("%s: tmds clk: %llu\n", __func__, tmds_clk); |
| 1141 | DEV_DBG("%s: HSCLK_SEL: %llu\n", __func__, hsclk); |
| 1142 | DEV_DBG("%s: DEC_START: %llu\n", __func__, dec_start); |
| 1143 | DEV_DBG("%s: DIV_FRAC_START: %llu\n", __func__, frac_start); |
| 1144 | DEV_DBG("%s: PLL_CPCTRL: %llu\n", __func__, cpctrl); |
| 1145 | DEV_DBG("%s: PLL_RCTRL: %llu\n", __func__, rctrl); |
| 1146 | DEV_DBG("%s: PLL_CCTRL: %llu\n", __func__, cctrl); |
| 1147 | DEV_DBG("%s: INTEGLOOP_GAIN: %llu\n", __func__, integloop_gain); |
| 1148 | DEV_DBG("%s: VCO_TUNE: %llu\n", __func__, vco_tune); |
| 1149 | DEV_DBG("%s: TX_BAND: %llu\n", __func__, tx_band); |
| 1150 | DEV_DBG("%s: PLL_CMP: %llu\n", __func__, pll_cmp); |
| 1151 | |
| 1152 | /* Convert these values to register specific values */ |
| 1153 | cfg->tx_l0_lane_mode = 0x3; |
| 1154 | cfg->tx_l2_lane_mode = 0x3; |
| 1155 | cfg->tx_l0_tx_band = tx_band + 4; |
| 1156 | cfg->tx_l1_tx_band = tx_band + 4; |
| 1157 | cfg->tx_l2_tx_band = tx_band + 4; |
| 1158 | cfg->tx_l3_tx_band = tx_band + 4; |
| 1159 | |
| 1160 | if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) |
| 1161 | cfg->com_svs_mode_clk_sel = 1; |
| 1162 | else |
| 1163 | cfg->com_svs_mode_clk_sel = 2; |
| 1164 | |
| 1165 | cfg->com_hsclk_sel = (0x28 | hsclk); |
| 1166 | cfg->com_pll_cctrl_mode0 = cctrl; |
| 1167 | cfg->com_pll_rctrl_mode0 = rctrl; |
| 1168 | cfg->com_cp_ctrl_mode0 = cpctrl; |
| 1169 | cfg->com_dec_start_mode0 = dec_start; |
| 1170 | cfg->com_div_frac_start1_mode0 = (frac_start & 0xFF); |
| 1171 | cfg->com_div_frac_start2_mode0 = ((frac_start & 0xFF00) >> 8); |
| 1172 | cfg->com_div_frac_start3_mode0 = ((frac_start & 0xF0000) >> 16); |
| 1173 | cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xFF); |
| 1174 | cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xF00) >> 8); |
| 1175 | cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xFF); |
| 1176 | cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8); |
| 1177 | cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); |
| 1178 | cfg->com_core_clk_en = (0x6C | (HDMI_CLKS_PLL_DIVSEL << 4)); |
| 1179 | cfg->com_coreclk_div = HDMI_CORECLK_DIV; |
| 1180 | cfg->com_vco_tune_ctrl = 0x0; |
| 1181 | |
| 1182 | if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { |
| 1183 | cfg->tx_l0_tx_drv_lvl = 0x25; |
| 1184 | cfg->tx_l0_tx_emp_post1_lvl = 0x23; |
| 1185 | cfg->tx_l1_tx_drv_lvl = 0x25; |
| 1186 | cfg->tx_l1_tx_emp_post1_lvl = 0x23; |
| 1187 | cfg->tx_l2_tx_drv_lvl = 0x25; |
| 1188 | cfg->tx_l2_tx_emp_post1_lvl = 0x23; |
| 1189 | cfg->tx_l3_tx_drv_lvl = 0x22; |
| 1190 | cfg->tx_l3_tx_emp_post1_lvl = 0x27; |
| 1191 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 1192 | cfg->tx_l0_vmode_ctrl2 = 0x0D; |
| 1193 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 1194 | cfg->tx_l1_vmode_ctrl2 = 0x0D; |
| 1195 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 1196 | cfg->tx_l2_vmode_ctrl2 = 0x0D; |
| 1197 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 1198 | cfg->tx_l3_vmode_ctrl2 = 0x00; |
| 1199 | cfg->tx_l0_res_code_lane_tx = 0x3F; |
| 1200 | cfg->tx_l1_res_code_lane_tx = 0x3F; |
| 1201 | cfg->tx_l2_res_code_lane_tx = 0x3F; |
| 1202 | cfg->tx_l3_res_code_lane_tx = 0x3F; |
| 1203 | cfg->com_restrim_ctrl = 0x0; |
| 1204 | } else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) { |
| 1205 | cfg->tx_l0_tx_drv_lvl = 0x25; |
| 1206 | cfg->tx_l0_tx_emp_post1_lvl = 0x23; |
| 1207 | cfg->tx_l1_tx_drv_lvl = 0x25; |
| 1208 | cfg->tx_l1_tx_emp_post1_lvl = 0x23; |
| 1209 | cfg->tx_l2_tx_drv_lvl = 0x25; |
| 1210 | cfg->tx_l2_tx_emp_post1_lvl = 0x23; |
| 1211 | cfg->tx_l3_tx_drv_lvl = 0x25; |
| 1212 | cfg->tx_l3_tx_emp_post1_lvl = 0x23; |
| 1213 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 1214 | cfg->tx_l0_vmode_ctrl2 = 0x0D; |
| 1215 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 1216 | cfg->tx_l1_vmode_ctrl2 = 0x0D; |
| 1217 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 1218 | cfg->tx_l2_vmode_ctrl2 = 0x0D; |
| 1219 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 1220 | cfg->tx_l3_vmode_ctrl2 = 0x00; |
| 1221 | cfg->tx_l0_res_code_lane_tx = 0x39; |
| 1222 | cfg->tx_l1_res_code_lane_tx = 0x39; |
| 1223 | cfg->tx_l2_res_code_lane_tx = 0x39; |
| 1224 | cfg->tx_l3_res_code_lane_tx = 0x39; |
| 1225 | cfg->com_restrim_ctrl = 0x0; |
| 1226 | } else { |
| 1227 | cfg->tx_l0_tx_drv_lvl = 0x20; |
| 1228 | cfg->tx_l0_tx_emp_post1_lvl = 0x20; |
| 1229 | cfg->tx_l1_tx_drv_lvl = 0x20; |
| 1230 | cfg->tx_l1_tx_emp_post1_lvl = 0x20; |
| 1231 | cfg->tx_l2_tx_drv_lvl = 0x20; |
| 1232 | cfg->tx_l2_tx_emp_post1_lvl = 0x20; |
| 1233 | cfg->tx_l3_tx_drv_lvl = 0x20; |
| 1234 | cfg->tx_l3_tx_emp_post1_lvl = 0x20; |
| 1235 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 1236 | cfg->tx_l0_vmode_ctrl2 = 0x0E; |
| 1237 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 1238 | cfg->tx_l1_vmode_ctrl2 = 0x0E; |
| 1239 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 1240 | cfg->tx_l2_vmode_ctrl2 = 0x0E; |
| 1241 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 1242 | cfg->tx_l3_vmode_ctrl2 = 0x0E; |
| 1243 | cfg->tx_l0_res_code_lane_tx = 0x3F; |
| 1244 | cfg->tx_l1_res_code_lane_tx = 0x3F; |
| 1245 | cfg->tx_l2_res_code_lane_tx = 0x3F; |
| 1246 | cfg->tx_l3_res_code_lane_tx = 0x3F; |
| 1247 | cfg->com_restrim_ctrl = 0xD8; |
| 1248 | } |
| 1249 | |
| 1250 | cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; |
| 1251 | DEV_DBG("HDMI 8996 PLL: PLL Settings\n"); |
| 1252 | DEV_DBG("PLL PARAM: tx_l0_lane_mode = 0x%x\n", cfg->tx_l0_lane_mode); |
| 1253 | DEV_DBG("PLL PARAM: tx_l2_lane_mode = 0x%x\n", cfg->tx_l2_lane_mode); |
| 1254 | DEV_DBG("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band); |
| 1255 | DEV_DBG("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band); |
| 1256 | DEV_DBG("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band); |
| 1257 | DEV_DBG("PLL PARAM: tx_l3_tx_band = 0x%x\n", cfg->tx_l3_tx_band); |
| 1258 | DEV_DBG("PLL PARAM: com_svs_mode_clk_sel = 0x%x\n", |
| 1259 | cfg->com_svs_mode_clk_sel); |
| 1260 | DEV_DBG("PLL PARAM: com_vco_tune_ctrl = 0x%x\n", |
| 1261 | cfg->com_vco_tune_ctrl); |
| 1262 | DEV_DBG("PLL PARAM: com_hsclk_sel = 0x%x\n", cfg->com_hsclk_sel); |
| 1263 | DEV_DBG("PLL PARAM: com_lock_cmp_en = 0x%x\n", cfg->com_lock_cmp_en); |
| 1264 | DEV_DBG("PLL PARAM: com_pll_cctrl_mode0 = 0x%x\n", |
| 1265 | cfg->com_pll_cctrl_mode0); |
| 1266 | DEV_DBG("PLL PARAM: com_pll_rctrl_mode0 = 0x%x\n", |
| 1267 | cfg->com_pll_rctrl_mode0); |
| 1268 | DEV_DBG("PLL PARAM: com_cp_ctrl_mode0 = 0x%x\n", |
| 1269 | cfg->com_cp_ctrl_mode0); |
| 1270 | DEV_DBG("PLL PARAM: com_dec_start_mode0 = 0x%x\n", |
| 1271 | cfg->com_dec_start_mode0); |
| 1272 | DEV_DBG("PLL PARAM: com_div_frac_start1_mode0 = 0x%x\n", |
| 1273 | cfg->com_div_frac_start1_mode0); |
| 1274 | DEV_DBG("PLL PARAM: com_div_frac_start2_mode0 = 0x%x\n", |
| 1275 | cfg->com_div_frac_start2_mode0); |
| 1276 | DEV_DBG("PLL PARAM: com_div_frac_start3_mode0 = 0x%x\n", |
| 1277 | cfg->com_div_frac_start3_mode0); |
| 1278 | DEV_DBG("PLL PARAM: com_integloop_gain0_mode0 = 0x%x\n", |
| 1279 | cfg->com_integloop_gain0_mode0); |
| 1280 | DEV_DBG("PLL PARAM: com_integloop_gain1_mode0 = 0x%x\n", |
| 1281 | cfg->com_integloop_gain1_mode0); |
| 1282 | DEV_DBG("PLL PARAM: com_lock_cmp1_mode0 = 0x%x\n", |
| 1283 | cfg->com_lock_cmp1_mode0); |
| 1284 | DEV_DBG("PLL PARAM: com_lock_cmp2_mode0 = 0x%x\n", |
| 1285 | cfg->com_lock_cmp2_mode0); |
| 1286 | DEV_DBG("PLL PARAM: com_lock_cmp3_mode0 = 0x%x\n", |
| 1287 | cfg->com_lock_cmp3_mode0); |
| 1288 | DEV_DBG("PLL PARAM: com_core_clk_en = 0x%x\n", cfg->com_core_clk_en); |
| 1289 | DEV_DBG("PLL PARAM: com_coreclk_div = 0x%x\n", cfg->com_coreclk_div); |
| 1290 | |
| 1291 | DEV_DBG("PLL PARAM: l0_tx_drv_lvl = 0x%x\n", cfg->tx_l0_tx_drv_lvl); |
| 1292 | DEV_DBG("PLL PARAM: l0_tx_emp_post1_lvl = 0x%x\n", |
| 1293 | cfg->tx_l0_tx_emp_post1_lvl); |
| 1294 | DEV_DBG("PLL PARAM: l1_tx_drv_lvl = 0x%x\n", cfg->tx_l1_tx_drv_lvl); |
| 1295 | DEV_DBG("PLL PARAM: l1_tx_emp_post1_lvl = 0x%x\n", |
| 1296 | cfg->tx_l1_tx_emp_post1_lvl); |
| 1297 | DEV_DBG("PLL PARAM: l2_tx_drv_lvl = 0x%x\n", cfg->tx_l2_tx_drv_lvl); |
| 1298 | DEV_DBG("PLL PARAM: l2_tx_emp_post1_lvl = 0x%x\n", |
| 1299 | cfg->tx_l2_tx_emp_post1_lvl); |
| 1300 | DEV_DBG("PLL PARAM: l3_tx_drv_lvl = 0x%x\n", cfg->tx_l3_tx_drv_lvl); |
| 1301 | DEV_DBG("PLL PARAM: l3_tx_emp_post1_lvl = 0x%x\n", |
| 1302 | cfg->tx_l3_tx_emp_post1_lvl); |
| 1303 | |
| 1304 | DEV_DBG("PLL PARAM: l0_vmode_ctrl1 = 0x%x\n", cfg->tx_l0_vmode_ctrl1); |
| 1305 | DEV_DBG("PLL PARAM: l0_vmode_ctrl2 = 0x%x\n", cfg->tx_l0_vmode_ctrl2); |
| 1306 | DEV_DBG("PLL PARAM: l1_vmode_ctrl1 = 0x%x\n", cfg->tx_l1_vmode_ctrl1); |
| 1307 | DEV_DBG("PLL PARAM: l1_vmode_ctrl2 = 0x%x\n", cfg->tx_l1_vmode_ctrl2); |
| 1308 | DEV_DBG("PLL PARAM: l2_vmode_ctrl1 = 0x%x\n", cfg->tx_l2_vmode_ctrl1); |
| 1309 | DEV_DBG("PLL PARAM: l2_vmode_ctrl2 = 0x%x\n", cfg->tx_l2_vmode_ctrl2); |
| 1310 | DEV_DBG("PLL PARAM: l3_vmode_ctrl1 = 0x%x\n", cfg->tx_l3_vmode_ctrl1); |
| 1311 | DEV_DBG("PLL PARAM: l3_vmode_ctrl2 = 0x%x\n", cfg->tx_l3_vmode_ctrl2); |
| 1312 | DEV_DBG("PLL PARAM: tx_l0_res_code_lane_tx = 0x%x\n", |
| 1313 | cfg->tx_l0_res_code_lane_tx); |
| 1314 | DEV_DBG("PLL PARAM: tx_l1_res_code_lane_tx = 0x%x\n", |
| 1315 | cfg->tx_l1_res_code_lane_tx); |
| 1316 | DEV_DBG("PLL PARAM: tx_l2_res_code_lane_tx = 0x%x\n", |
| 1317 | cfg->tx_l2_res_code_lane_tx); |
| 1318 | DEV_DBG("PLL PARAM: tx_l3_res_code_lane_tx = 0x%x\n", |
| 1319 | cfg->tx_l3_res_code_lane_tx); |
| 1320 | DEV_DBG("PLL PARAM: com_restrim_ctrl = 0x%x\n", cfg->com_restrim_ctrl); |
| 1321 | |
| 1322 | DEV_DBG("PLL PARAM: phy_mode = 0x%x\n", cfg->phy_mode); |
| 1323 | rc = 0; |
| 1324 | fail: |
| 1325 | return rc; |
| 1326 | } |
| 1327 | |
| 1328 | static int hdmi_8996_v3_calculate(u32 pix_clk, |
| 1329 | struct hdmi_8996_phy_pll_reg_cfg *cfg) |
| 1330 | { |
| 1331 | int rc = -EINVAL; |
| 1332 | struct hdmi_8996_v3_post_divider pd; |
| 1333 | u64 fdata, tmds_clk; |
| 1334 | u64 bclk; |
| 1335 | u64 pll_cmp; |
| 1336 | u64 tx_band; |
| 1337 | u64 hsclk; |
| 1338 | u64 dec_start; |
| 1339 | u64 frac_start; |
| 1340 | u64 pll_divisor = 4 * HDMI_REF_CLOCK; |
| 1341 | u64 cpctrl; |
| 1342 | u64 rctrl; |
| 1343 | u64 cctrl; |
| 1344 | u64 integloop_gain; |
| 1345 | u64 vco_freq; |
| 1346 | u64 rem; |
| 1347 | |
| 1348 | /* FDATA, HSCLK, PIXEL_CLK, TMDS_CLK */ |
| 1349 | bclk = ((u64)pix_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; |
| 1350 | |
| 1351 | if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) |
| 1352 | tmds_clk = pix_clk >> 2; |
| 1353 | else |
| 1354 | tmds_clk = pix_clk; |
| 1355 | |
| 1356 | if (hdmi_8996_v3_get_post_div(&pd, bclk) || pd.vco_ratio <= 0 || |
| 1357 | pd.vco_freq <= 0) |
| 1358 | goto fail; |
| 1359 | |
| 1360 | vco_freq = pd.vco_freq; |
| 1361 | fdata = pd.vco_freq; |
| 1362 | do_div(fdata, pd.vco_ratio); |
| 1363 | |
| 1364 | hsclk = pd.hsclk_divsel; |
| 1365 | dec_start = vco_freq; |
| 1366 | do_div(dec_start, pll_divisor); |
| 1367 | |
| 1368 | frac_start = vco_freq * (1 << 20); |
| 1369 | rem = do_div(frac_start, pll_divisor); |
| 1370 | frac_start -= dec_start * (1 << 20); |
| 1371 | if (rem > (pll_divisor >> 1)) |
| 1372 | frac_start++; |
| 1373 | |
| 1374 | cpctrl = hdmi_8996_get_cpctrl(frac_start, false); |
| 1375 | rctrl = hdmi_8996_get_rctrl(frac_start, false); |
| 1376 | cctrl = hdmi_8996_get_cctrl(frac_start, false); |
| 1377 | integloop_gain = hdmi_8996_v3_get_integloop_gain(frac_start, bclk, |
| 1378 | false); |
| 1379 | pll_cmp = hdmi_8996_v3_get_pll_cmp(1024, fdata); |
| 1380 | tx_band = pd.tx_band_sel; |
| 1381 | |
| 1382 | /* Debug dump */ |
| 1383 | DEV_DBG("%s: VCO freq: %llu\n", __func__, vco_freq); |
| 1384 | DEV_DBG("%s: fdata: %llu\n", __func__, fdata); |
| 1385 | DEV_DBG("%s: pix_clk: %d\n", __func__, pix_clk); |
| 1386 | DEV_DBG("%s: tmds clk: %llu\n", __func__, tmds_clk); |
| 1387 | DEV_DBG("%s: HSCLK_SEL: %llu\n", __func__, hsclk); |
| 1388 | DEV_DBG("%s: DEC_START: %llu\n", __func__, dec_start); |
| 1389 | DEV_DBG("%s: DIV_FRAC_START: %llu\n", __func__, frac_start); |
| 1390 | DEV_DBG("%s: PLL_CPCTRL: %llu\n", __func__, cpctrl); |
| 1391 | DEV_DBG("%s: PLL_RCTRL: %llu\n", __func__, rctrl); |
| 1392 | DEV_DBG("%s: PLL_CCTRL: %llu\n", __func__, cctrl); |
| 1393 | DEV_DBG("%s: INTEGLOOP_GAIN: %llu\n", __func__, integloop_gain); |
| 1394 | DEV_DBG("%s: TX_BAND: %llu\n", __func__, tx_band); |
| 1395 | DEV_DBG("%s: PLL_CMP: %llu\n", __func__, pll_cmp); |
| 1396 | |
| 1397 | /* Convert these values to register specific values */ |
| 1398 | cfg->tx_l0_tx_band = tx_band + 4; |
| 1399 | cfg->tx_l1_tx_band = tx_band + 4; |
| 1400 | cfg->tx_l2_tx_band = tx_band + 4; |
| 1401 | cfg->tx_l3_tx_band = tx_band + 4; |
| 1402 | |
| 1403 | if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) |
| 1404 | cfg->com_svs_mode_clk_sel = 1; |
| 1405 | else |
| 1406 | cfg->com_svs_mode_clk_sel = 2; |
| 1407 | |
| 1408 | cfg->com_hsclk_sel = (0x20 | hsclk); |
| 1409 | cfg->com_pll_cctrl_mode0 = cctrl; |
| 1410 | cfg->com_pll_rctrl_mode0 = rctrl; |
| 1411 | cfg->com_cp_ctrl_mode0 = cpctrl; |
| 1412 | cfg->com_dec_start_mode0 = dec_start; |
| 1413 | cfg->com_div_frac_start1_mode0 = (frac_start & 0xFF); |
| 1414 | cfg->com_div_frac_start2_mode0 = ((frac_start & 0xFF00) >> 8); |
| 1415 | cfg->com_div_frac_start3_mode0 = ((frac_start & 0xF0000) >> 16); |
| 1416 | cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xFF); |
| 1417 | cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xF00) >> 8); |
| 1418 | cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xFF); |
| 1419 | cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8); |
| 1420 | cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16); |
| 1421 | cfg->com_lock_cmp_en = 0x04; |
| 1422 | cfg->com_core_clk_en = 0x2C; |
| 1423 | cfg->com_coreclk_div = HDMI_CORECLK_DIV; |
| 1424 | cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; |
| 1425 | cfg->com_vco_tune_ctrl = 0x0; |
| 1426 | |
| 1427 | cfg->tx_l0_lane_mode = 0x43; |
| 1428 | cfg->tx_l2_lane_mode = 0x43; |
| 1429 | |
| 1430 | if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { |
| 1431 | cfg->tx_l0_tx_drv_lvl = 0x25; |
| 1432 | cfg->tx_l0_tx_emp_post1_lvl = 0x23; |
| 1433 | cfg->tx_l1_tx_drv_lvl = 0x25; |
| 1434 | cfg->tx_l1_tx_emp_post1_lvl = 0x23; |
| 1435 | cfg->tx_l2_tx_drv_lvl = 0x25; |
| 1436 | cfg->tx_l2_tx_emp_post1_lvl = 0x23; |
| 1437 | cfg->tx_l3_tx_drv_lvl = 0x22; |
| 1438 | cfg->tx_l3_tx_emp_post1_lvl = 0x27; |
| 1439 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 1440 | cfg->tx_l0_vmode_ctrl2 = 0x0D; |
| 1441 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 1442 | cfg->tx_l1_vmode_ctrl2 = 0x0D; |
| 1443 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 1444 | cfg->tx_l2_vmode_ctrl2 = 0x0D; |
| 1445 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 1446 | cfg->tx_l3_vmode_ctrl2 = 0x00; |
| 1447 | } else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) { |
| 1448 | cfg->tx_l0_tx_drv_lvl = 0x25; |
| 1449 | cfg->tx_l0_tx_emp_post1_lvl = 0x23; |
| 1450 | cfg->tx_l1_tx_drv_lvl = 0x25; |
| 1451 | cfg->tx_l1_tx_emp_post1_lvl = 0x23; |
| 1452 | cfg->tx_l2_tx_drv_lvl = 0x25; |
| 1453 | cfg->tx_l2_tx_emp_post1_lvl = 0x23; |
| 1454 | cfg->tx_l3_tx_drv_lvl = 0x25; |
| 1455 | cfg->tx_l3_tx_emp_post1_lvl = 0x23; |
| 1456 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 1457 | cfg->tx_l0_vmode_ctrl2 = 0x0D; |
| 1458 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 1459 | cfg->tx_l1_vmode_ctrl2 = 0x0D; |
| 1460 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 1461 | cfg->tx_l2_vmode_ctrl2 = 0x0D; |
| 1462 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 1463 | cfg->tx_l3_vmode_ctrl2 = 0x00; |
| 1464 | } else { |
| 1465 | cfg->tx_l0_tx_drv_lvl = 0x20; |
| 1466 | cfg->tx_l0_tx_emp_post1_lvl = 0x20; |
| 1467 | cfg->tx_l1_tx_drv_lvl = 0x20; |
| 1468 | cfg->tx_l1_tx_emp_post1_lvl = 0x20; |
| 1469 | cfg->tx_l2_tx_drv_lvl = 0x20; |
| 1470 | cfg->tx_l2_tx_emp_post1_lvl = 0x20; |
| 1471 | cfg->tx_l3_tx_drv_lvl = 0x20; |
| 1472 | cfg->tx_l3_tx_emp_post1_lvl = 0x20; |
| 1473 | cfg->tx_l0_vmode_ctrl1 = 0x00; |
| 1474 | cfg->tx_l0_vmode_ctrl2 = 0x0E; |
| 1475 | cfg->tx_l1_vmode_ctrl1 = 0x00; |
| 1476 | cfg->tx_l1_vmode_ctrl2 = 0x0E; |
| 1477 | cfg->tx_l2_vmode_ctrl1 = 0x00; |
| 1478 | cfg->tx_l2_vmode_ctrl2 = 0x0E; |
| 1479 | cfg->tx_l3_vmode_ctrl1 = 0x00; |
| 1480 | cfg->tx_l3_vmode_ctrl2 = 0x0E; |
| 1481 | } |
| 1482 | |
| 1483 | DEV_DBG("HDMI 8996 PLL: PLL Settings\n"); |
| 1484 | DEV_DBG("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band); |
| 1485 | DEV_DBG("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band); |
| 1486 | DEV_DBG("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band); |
| 1487 | DEV_DBG("PLL PARAM: tx_l3_tx_band = 0x%x\n", cfg->tx_l3_tx_band); |
| 1488 | DEV_DBG("PLL PARAM: com_svs_mode_clk_sel = 0x%x\n", |
| 1489 | cfg->com_svs_mode_clk_sel); |
| 1490 | DEV_DBG("PLL PARAM: com_hsclk_sel = 0x%x\n", cfg->com_hsclk_sel); |
| 1491 | DEV_DBG("PLL PARAM: com_lock_cmp_en = 0x%x\n", cfg->com_lock_cmp_en); |
| 1492 | DEV_DBG("PLL PARAM: com_pll_cctrl_mode0 = 0x%x\n", |
| 1493 | cfg->com_pll_cctrl_mode0); |
| 1494 | DEV_DBG("PLL PARAM: com_pll_rctrl_mode0 = 0x%x\n", |
| 1495 | cfg->com_pll_rctrl_mode0); |
| 1496 | DEV_DBG("PLL PARAM: com_cp_ctrl_mode0 = 0x%x\n", |
| 1497 | cfg->com_cp_ctrl_mode0); |
| 1498 | DEV_DBG("PLL PARAM: com_dec_start_mode0 = 0x%x\n", |
| 1499 | cfg->com_dec_start_mode0); |
| 1500 | DEV_DBG("PLL PARAM: com_div_frac_start1_mode0 = 0x%x\n", |
| 1501 | cfg->com_div_frac_start1_mode0); |
| 1502 | DEV_DBG("PLL PARAM: com_div_frac_start2_mode0 = 0x%x\n", |
| 1503 | cfg->com_div_frac_start2_mode0); |
| 1504 | DEV_DBG("PLL PARAM: com_div_frac_start3_mode0 = 0x%x\n", |
| 1505 | cfg->com_div_frac_start3_mode0); |
| 1506 | DEV_DBG("PLL PARAM: com_integloop_gain0_mode0 = 0x%x\n", |
| 1507 | cfg->com_integloop_gain0_mode0); |
| 1508 | DEV_DBG("PLL PARAM: com_integloop_gain1_mode0 = 0x%x\n", |
| 1509 | cfg->com_integloop_gain1_mode0); |
| 1510 | DEV_DBG("PLL PARAM: com_lock_cmp1_mode0 = 0x%x\n", |
| 1511 | cfg->com_lock_cmp1_mode0); |
| 1512 | DEV_DBG("PLL PARAM: com_lock_cmp2_mode0 = 0x%x\n", |
| 1513 | cfg->com_lock_cmp2_mode0); |
| 1514 | DEV_DBG("PLL PARAM: com_lock_cmp3_mode0 = 0x%x\n", |
| 1515 | cfg->com_lock_cmp3_mode0); |
| 1516 | DEV_DBG("PLL PARAM: com_core_clk_en = 0x%x\n", cfg->com_core_clk_en); |
| 1517 | DEV_DBG("PLL PARAM: com_coreclk_div = 0x%x\n", cfg->com_coreclk_div); |
| 1518 | DEV_DBG("PLL PARAM: phy_mode = 0x%x\n", cfg->phy_mode); |
| 1519 | |
| 1520 | DEV_DBG("PLL PARAM: tx_l0_lane_mode = 0x%x\n", cfg->tx_l0_lane_mode); |
| 1521 | DEV_DBG("PLL PARAM: tx_l2_lane_mode = 0x%x\n", cfg->tx_l2_lane_mode); |
| 1522 | DEV_DBG("PLL PARAM: l0_tx_drv_lvl = 0x%x\n", cfg->tx_l0_tx_drv_lvl); |
| 1523 | DEV_DBG("PLL PARAM: l0_tx_emp_post1_lvl = 0x%x\n", |
| 1524 | cfg->tx_l0_tx_emp_post1_lvl); |
| 1525 | DEV_DBG("PLL PARAM: l1_tx_drv_lvl = 0x%x\n", cfg->tx_l1_tx_drv_lvl); |
| 1526 | DEV_DBG("PLL PARAM: l1_tx_emp_post1_lvl = 0x%x\n", |
| 1527 | cfg->tx_l1_tx_emp_post1_lvl); |
| 1528 | DEV_DBG("PLL PARAM: l2_tx_drv_lvl = 0x%x\n", cfg->tx_l2_tx_drv_lvl); |
| 1529 | DEV_DBG("PLL PARAM: l2_tx_emp_post1_lvl = 0x%x\n", |
| 1530 | cfg->tx_l2_tx_emp_post1_lvl); |
| 1531 | DEV_DBG("PLL PARAM: l3_tx_drv_lvl = 0x%x\n", cfg->tx_l3_tx_drv_lvl); |
| 1532 | DEV_DBG("PLL PARAM: l3_tx_emp_post1_lvl = 0x%x\n", |
| 1533 | cfg->tx_l3_tx_emp_post1_lvl); |
| 1534 | |
| 1535 | DEV_DBG("PLL PARAM: l0_vmode_ctrl1 = 0x%x\n", cfg->tx_l0_vmode_ctrl1); |
| 1536 | DEV_DBG("PLL PARAM: l0_vmode_ctrl2 = 0x%x\n", cfg->tx_l0_vmode_ctrl2); |
| 1537 | DEV_DBG("PLL PARAM: l1_vmode_ctrl1 = 0x%x\n", cfg->tx_l1_vmode_ctrl1); |
| 1538 | DEV_DBG("PLL PARAM: l1_vmode_ctrl2 = 0x%x\n", cfg->tx_l1_vmode_ctrl2); |
| 1539 | DEV_DBG("PLL PARAM: l2_vmode_ctrl1 = 0x%x\n", cfg->tx_l2_vmode_ctrl1); |
| 1540 | DEV_DBG("PLL PARAM: l2_vmode_ctrl2 = 0x%x\n", cfg->tx_l2_vmode_ctrl2); |
| 1541 | DEV_DBG("PLL PARAM: l3_vmode_ctrl1 = 0x%x\n", cfg->tx_l3_vmode_ctrl1); |
| 1542 | DEV_DBG("PLL PARAM: l3_vmode_ctrl2 = 0x%x\n", cfg->tx_l3_vmode_ctrl2); |
| 1543 | rc = 0; |
| 1544 | fail: |
| 1545 | return rc; |
| 1546 | } |
| 1547 | |
| 1548 | static int hdmi_8996_calculate(u32 pix_clk, |
| 1549 | struct hdmi_8996_phy_pll_reg_cfg *cfg, u32 ver) |
| 1550 | { |
| 1551 | switch (ver) { |
| 1552 | case HDMI_VERSION_8996_V3: |
| 1553 | case HDMI_VERSION_8996_V3_1_8: |
| 1554 | return hdmi_8996_v3_calculate(pix_clk, cfg); |
| 1555 | case HDMI_VERSION_8996_V2: |
| 1556 | return hdmi_8996_v2_calculate(pix_clk, cfg); |
| 1557 | default: |
| 1558 | return hdmi_8996_v1_calculate(pix_clk, cfg); |
| 1559 | } |
| 1560 | } |
| 1561 | |
| 1562 | static int hdmi_8996_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk, u32 ver) |
| 1563 | { |
| 1564 | int rc = 0; |
| 1565 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 1566 | struct mdss_pll_resources *io = vco->priv; |
| 1567 | struct hdmi_8996_phy_pll_reg_cfg cfg = {0}; |
| 1568 | |
| 1569 | rc = hdmi_8996_calculate(tmds_clk, &cfg, ver); |
| 1570 | if (rc) { |
| 1571 | DEV_ERR("%s: PLL calculation failed\n", __func__); |
| 1572 | return rc; |
| 1573 | } |
| 1574 | |
| 1575 | /* Initially shut down PHY */ |
| 1576 | DEV_DBG("%s: Disabling PHY\n", __func__); |
| 1577 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x0); |
| 1578 | udelay(500); |
| 1579 | |
| 1580 | /* Power up sequence */ |
| 1581 | switch (ver) { |
| 1582 | case HDMI_VERSION_8996_V2: |
| 1583 | case HDMI_VERSION_8996_V3: |
| 1584 | case HDMI_VERSION_8996_V3_1_8: |
| 1585 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x04); |
| 1586 | break; |
| 1587 | }; |
| 1588 | |
| 1589 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x1); |
| 1590 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESETSM_CNTRL, 0x20); |
| 1591 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TX0_TX1_LANE_CTL, 0x0F); |
| 1592 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TX2_TX3_LANE_CTL, 0x0F); |
| 1593 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1594 | QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); |
| 1595 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1596 | QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); |
| 1597 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1598 | QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); |
| 1599 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1600 | QSERDES_TX_L0_CLKBUF_ENABLE, 0x03); |
| 1601 | |
| 1602 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1603 | QSERDES_TX_L0_LANE_MODE, cfg.tx_l0_lane_mode); |
| 1604 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1605 | QSERDES_TX_L0_LANE_MODE, cfg.tx_l2_lane_mode); |
| 1606 | |
| 1607 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1608 | QSERDES_TX_L0_TX_BAND, cfg.tx_l0_tx_band); |
| 1609 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1610 | QSERDES_TX_L0_TX_BAND, cfg.tx_l1_tx_band); |
| 1611 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1612 | QSERDES_TX_L0_TX_BAND, cfg.tx_l2_tx_band); |
| 1613 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1614 | QSERDES_TX_L0_TX_BAND, cfg.tx_l3_tx_band); |
| 1615 | |
| 1616 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1617 | QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); |
| 1618 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1619 | QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); |
| 1620 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1621 | QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); |
| 1622 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1623 | QSERDES_TX_L0_RESET_TSYNC_EN, 0x03); |
| 1624 | |
| 1625 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E); |
| 1626 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x07); |
| 1627 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYSCLK_EN_SEL, 0x37); |
| 1628 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x02); |
| 1629 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CLK_ENABLE1, 0x0E); |
| 1630 | if (ver == HDMI_VERSION_8996_V1) |
| 1631 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x06); |
| 1632 | |
| 1633 | /* Bypass VCO calibration */ |
| 1634 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, |
| 1635 | cfg.com_svs_mode_clk_sel); |
| 1636 | |
| 1637 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_TRIM, 0x0F); |
| 1638 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IVCO, 0x0F); |
| 1639 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE_CTRL, |
| 1640 | cfg.com_vco_tune_ctrl); |
| 1641 | |
| 1642 | switch (ver) { |
| 1643 | case HDMI_VERSION_8996_V1: |
| 1644 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, |
| 1645 | cfg.com_svs_mode_clk_sel); |
| 1646 | break; |
| 1647 | default: |
| 1648 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BG_CTRL, 0x06); |
| 1649 | } |
| 1650 | |
| 1651 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CLK_SELECT, 0x30); |
| 1652 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_HSCLK_SEL, |
| 1653 | cfg.com_hsclk_sel); |
| 1654 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_EN, |
| 1655 | cfg.com_lock_cmp_en); |
| 1656 | |
| 1657 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CCTRL_MODE0, |
| 1658 | cfg.com_pll_cctrl_mode0); |
| 1659 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_RCTRL_MODE0, |
| 1660 | cfg.com_pll_rctrl_mode0); |
| 1661 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CP_CTRL_MODE0, |
| 1662 | cfg.com_cp_ctrl_mode0); |
| 1663 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START_MODE0, |
| 1664 | cfg.com_dec_start_mode0); |
| 1665 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START1_MODE0, |
| 1666 | cfg.com_div_frac_start1_mode0); |
| 1667 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START2_MODE0, |
| 1668 | cfg.com_div_frac_start2_mode0); |
| 1669 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START3_MODE0, |
| 1670 | cfg.com_div_frac_start3_mode0); |
| 1671 | |
| 1672 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, |
| 1673 | cfg.com_integloop_gain0_mode0); |
| 1674 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, |
| 1675 | cfg.com_integloop_gain1_mode0); |
| 1676 | |
| 1677 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP1_MODE0, |
| 1678 | cfg.com_lock_cmp1_mode0); |
| 1679 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP2_MODE0, |
| 1680 | cfg.com_lock_cmp2_mode0); |
| 1681 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP3_MODE0, |
| 1682 | cfg.com_lock_cmp3_mode0); |
| 1683 | |
| 1684 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE_MAP, 0x00); |
| 1685 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CORE_CLK_EN, |
| 1686 | cfg.com_core_clk_en); |
| 1687 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CORECLK_DIV, |
| 1688 | cfg.com_coreclk_div); |
| 1689 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_CONFIG, 0x02); |
| 1690 | |
| 1691 | if (ver == HDMI_VERSION_8996_V3 || ver == HDMI_VERSION_8996_V3_1_8) |
| 1692 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESCODE_DIV_NUM, 0x15); |
| 1693 | |
| 1694 | /* TX lanes setup (TX 0/1/2/3) */ |
| 1695 | if (ver == HDMI_VERSION_8996_V3_1_8) { |
| 1696 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1697 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1698 | 0x00000023); |
| 1699 | } else { |
| 1700 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1701 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1702 | cfg.tx_l0_tx_drv_lvl); |
| 1703 | } |
| 1704 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1705 | QSERDES_TX_L0_TX_EMP_POST1_LVL, |
| 1706 | cfg.tx_l0_tx_emp_post1_lvl); |
| 1707 | |
| 1708 | if (ver == HDMI_VERSION_8996_V3_1_8) { |
| 1709 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1710 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1711 | 0x00000023); |
| 1712 | } else { |
| 1713 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1714 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1715 | cfg.tx_l1_tx_drv_lvl); |
| 1716 | } |
| 1717 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1718 | QSERDES_TX_L0_TX_EMP_POST1_LVL, |
| 1719 | cfg.tx_l1_tx_emp_post1_lvl); |
| 1720 | |
| 1721 | if (ver == HDMI_VERSION_8996_V3_1_8) { |
| 1722 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1723 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1724 | 0x00000023); |
| 1725 | } else { |
| 1726 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1727 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1728 | cfg.tx_l2_tx_drv_lvl); |
| 1729 | } |
| 1730 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1731 | QSERDES_TX_L0_TX_EMP_POST1_LVL, |
| 1732 | cfg.tx_l2_tx_emp_post1_lvl); |
| 1733 | |
| 1734 | if (ver == HDMI_VERSION_8996_V3_1_8) { |
| 1735 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1736 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1737 | 0x00000020); |
| 1738 | } else { |
| 1739 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1740 | QSERDES_TX_L0_TX_DRV_LVL, |
| 1741 | cfg.tx_l3_tx_drv_lvl); |
| 1742 | } |
| 1743 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1744 | QSERDES_TX_L0_TX_EMP_POST1_LVL, |
| 1745 | cfg.tx_l3_tx_emp_post1_lvl); |
| 1746 | |
| 1747 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1748 | QSERDES_TX_L0_VMODE_CTRL1, |
| 1749 | cfg.tx_l0_vmode_ctrl1); |
| 1750 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1751 | QSERDES_TX_L0_VMODE_CTRL2, |
| 1752 | cfg.tx_l0_vmode_ctrl2); |
| 1753 | |
| 1754 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1755 | QSERDES_TX_L0_VMODE_CTRL1, |
| 1756 | cfg.tx_l1_vmode_ctrl1); |
| 1757 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1758 | QSERDES_TX_L0_VMODE_CTRL2, |
| 1759 | cfg.tx_l1_vmode_ctrl2); |
| 1760 | |
| 1761 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1762 | QSERDES_TX_L0_VMODE_CTRL1, |
| 1763 | cfg.tx_l2_vmode_ctrl1); |
| 1764 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1765 | QSERDES_TX_L0_VMODE_CTRL2, |
| 1766 | cfg.tx_l2_vmode_ctrl2); |
| 1767 | |
| 1768 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1769 | QSERDES_TX_L0_VMODE_CTRL1, |
| 1770 | cfg.tx_l3_vmode_ctrl1); |
| 1771 | if (ver == HDMI_VERSION_8996_V3_1_8) { |
| 1772 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1773 | QSERDES_TX_L0_VMODE_CTRL2, |
| 1774 | 0x0000000D); |
| 1775 | } else { |
| 1776 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1777 | QSERDES_TX_L0_VMODE_CTRL2, |
| 1778 | cfg.tx_l3_vmode_ctrl2); |
| 1779 | } |
| 1780 | |
| 1781 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1782 | QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); |
| 1783 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1784 | QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); |
| 1785 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1786 | QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); |
| 1787 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1788 | QSERDES_TX_L0_TX_DRV_LVL_OFFSET, 0x00); |
| 1789 | |
| 1790 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1791 | QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); |
| 1792 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1793 | QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); |
| 1794 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1795 | QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); |
| 1796 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1797 | QSERDES_TX_L0_RES_CODE_LANE_OFFSET, 0x00); |
| 1798 | |
| 1799 | if (ver < HDMI_VERSION_8996_V3) { |
| 1800 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1801 | QSERDES_TX_L0_RES_CODE_LANE_TX, |
| 1802 | cfg.tx_l0_res_code_lane_tx); |
| 1803 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1804 | QSERDES_TX_L0_RES_CODE_LANE_TX, |
| 1805 | cfg.tx_l1_res_code_lane_tx); |
| 1806 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1807 | QSERDES_TX_L0_RES_CODE_LANE_TX, |
| 1808 | cfg.tx_l2_res_code_lane_tx); |
| 1809 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1810 | QSERDES_TX_L0_RES_CODE_LANE_TX, |
| 1811 | cfg.tx_l3_res_code_lane_tx); |
| 1812 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESTRIM_CTRL, |
| 1813 | cfg.com_restrim_ctrl); |
| 1814 | |
| 1815 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TXCAL_CFG0, 0x00); |
| 1816 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TXCAL_CFG1, 0x05); |
| 1817 | } |
| 1818 | |
| 1819 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_MODE, cfg.phy_mode); |
| 1820 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x1F); |
| 1821 | |
| 1822 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1823 | QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); |
| 1824 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1825 | QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); |
| 1826 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1827 | QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); |
| 1828 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1829 | QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03); |
| 1830 | |
| 1831 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1832 | QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); |
| 1833 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1834 | QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); |
| 1835 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1836 | QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); |
| 1837 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1838 | QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40); |
| 1839 | |
| 1840 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 1841 | QSERDES_TX_L0_HP_PD_ENABLES, 0x0C); |
| 1842 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 1843 | QSERDES_TX_L0_HP_PD_ENABLES, 0x0C); |
| 1844 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 1845 | QSERDES_TX_L0_HP_PD_ENABLES, 0x0C); |
| 1846 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 1847 | QSERDES_TX_L0_HP_PD_ENABLES, 0x03); |
| 1848 | |
| 1849 | if (ver == HDMI_VERSION_8996_V2) { |
| 1850 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL1, 0x01); |
| 1851 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL2, 0x01); |
| 1852 | } |
| 1853 | /* |
| 1854 | * Ensure that vco configuration gets flushed to hardware before |
| 1855 | * enabling the PLL |
| 1856 | */ |
| 1857 | wmb(); |
| 1858 | return 0; |
| 1859 | } |
| 1860 | |
| 1861 | static int hdmi_8996_phy_ready_status(struct mdss_pll_resources *io) |
| 1862 | { |
| 1863 | u32 status = 0; |
| 1864 | int phy_ready = 0; |
| 1865 | int rc; |
| 1866 | u32 read_count = 0; |
| 1867 | |
| 1868 | rc = mdss_pll_resource_enable(io, true); |
| 1869 | if (rc) { |
| 1870 | DEV_ERR("%s: pll resource can't be enabled\n", __func__); |
| 1871 | return rc; |
| 1872 | } |
| 1873 | |
| 1874 | DEV_DBG("%s: Waiting for PHY Ready\n", __func__); |
| 1875 | |
| 1876 | /* Poll for PHY read status */ |
| 1877 | while (read_count < HDMI_PLL_POLL_MAX_READS) { |
| 1878 | status = MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS); |
| 1879 | if ((status & BIT(0)) == 1) { |
| 1880 | phy_ready = 1; |
| 1881 | DEV_DBG("%s: PHY READY\n", __func__); |
| 1882 | break; |
| 1883 | } |
| 1884 | udelay(HDMI_PLL_POLL_TIMEOUT_US); |
| 1885 | read_count++; |
| 1886 | } |
| 1887 | |
| 1888 | if (read_count == HDMI_PLL_POLL_MAX_READS) { |
| 1889 | phy_ready = 0; |
| 1890 | DEV_DBG("%s: PHY READY TIMEOUT\n", __func__); |
| 1891 | } |
| 1892 | |
| 1893 | mdss_pll_resource_enable(io, false); |
| 1894 | |
| 1895 | return phy_ready; |
| 1896 | } |
| 1897 | |
| 1898 | static int hdmi_8996_pll_lock_status(struct mdss_pll_resources *io) |
| 1899 | { |
| 1900 | u32 status; |
| 1901 | int pll_locked = 0; |
| 1902 | int rc; |
| 1903 | u32 read_count = 0; |
| 1904 | |
| 1905 | rc = mdss_pll_resource_enable(io, true); |
| 1906 | if (rc) { |
| 1907 | DEV_ERR("%s: pll resource can't be enabled\n", __func__); |
| 1908 | return rc; |
| 1909 | } |
| 1910 | |
| 1911 | DEV_DBG("%s: Waiting for PLL lock\n", __func__); |
| 1912 | |
| 1913 | while (read_count < HDMI_PLL_POLL_MAX_READS) { |
| 1914 | status = MDSS_PLL_REG_R(io->pll_base, |
| 1915 | QSERDES_COM_C_READY_STATUS); |
| 1916 | if ((status & BIT(0)) == 1) { |
| 1917 | pll_locked = 1; |
| 1918 | DEV_DBG("%s: C READY\n", __func__); |
| 1919 | break; |
| 1920 | } |
| 1921 | udelay(HDMI_PLL_POLL_TIMEOUT_US); |
| 1922 | read_count++; |
| 1923 | } |
| 1924 | |
| 1925 | if (read_count == HDMI_PLL_POLL_MAX_READS) { |
| 1926 | pll_locked = 0; |
| 1927 | DEV_DBG("%s: C READY TIMEOUT\n", __func__); |
| 1928 | } |
| 1929 | |
| 1930 | mdss_pll_resource_enable(io, false); |
| 1931 | |
| 1932 | return pll_locked; |
| 1933 | } |
| 1934 | |
| 1935 | static int hdmi_8996_v1_perform_sw_calibration(struct clk *c) |
| 1936 | { |
| 1937 | int rc = 0; |
| 1938 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 1939 | struct mdss_pll_resources *io = vco->priv; |
| 1940 | |
| 1941 | u32 max_code = 0x190; |
| 1942 | u32 min_code = 0x0; |
| 1943 | u32 max_cnt = 0; |
| 1944 | u32 min_cnt = 0; |
| 1945 | u32 expected_counter_value = 0; |
| 1946 | u32 step = 0; |
| 1947 | u32 dbus_all = 0; |
| 1948 | u32 dbus_sel = 0; |
| 1949 | u32 vco_code = 0; |
| 1950 | u32 val = 0; |
| 1951 | |
| 1952 | vco_code = 0xC8; |
| 1953 | |
| 1954 | DEV_DBG("%s: Starting SW calibration with vco_code = %d\n", __func__, |
| 1955 | vco_code); |
| 1956 | |
| 1957 | expected_counter_value = |
| 1958 | (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP3_MODE0) << 16) | |
| 1959 | (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP2_MODE0) << 8) | |
| 1960 | (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP1_MODE0)); |
| 1961 | |
| 1962 | DEV_DBG("%s: expected_counter_value = %d\n", __func__, |
| 1963 | expected_counter_value); |
| 1964 | |
| 1965 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); |
| 1966 | val |= BIT(4); |
| 1967 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); |
| 1968 | |
| 1969 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); |
| 1970 | val |= BIT(3); |
| 1971 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); |
| 1972 | |
| 1973 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEBUG_BUS_SEL, 0x4); |
| 1974 | |
| 1975 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); |
| 1976 | val |= BIT(1); |
| 1977 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); |
| 1978 | |
| 1979 | udelay(60); |
| 1980 | |
| 1981 | while (1) { |
| 1982 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE1_MODE0, |
| 1983 | vco_code & 0xFF); |
| 1984 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE2_MODE0, |
| 1985 | (vco_code >> 8) & 0x3); |
| 1986 | |
| 1987 | udelay(20); |
| 1988 | |
| 1989 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); |
| 1990 | val &= ~BIT(1); |
| 1991 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); |
| 1992 | |
| 1993 | udelay(60); |
| 1994 | |
| 1995 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); |
| 1996 | val |= BIT(1); |
| 1997 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); |
| 1998 | |
| 1999 | udelay(60); |
| 2000 | |
| 2001 | dbus_all = |
| 2002 | (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS3) << 24) | |
| 2003 | (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS2) << 16) | |
| 2004 | (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS1) << 8) | |
| 2005 | (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEBUG_BUS0)); |
| 2006 | |
| 2007 | dbus_sel = (dbus_all >> 9) & 0x3FFFF; |
| 2008 | DEV_DBG("%s: loop[%d], dbus_all = 0x%x, dbus_sel = 0x%x\n", |
| 2009 | __func__, step, dbus_all, dbus_sel); |
| 2010 | if (dbus_sel == 0) |
| 2011 | DEV_ERR("%s: CHECK HDMI REF CLK\n", __func__); |
| 2012 | |
| 2013 | if (dbus_sel == expected_counter_value) { |
| 2014 | max_code = vco_code; |
| 2015 | max_cnt = dbus_sel; |
| 2016 | min_code = vco_code; |
| 2017 | min_cnt = dbus_sel; |
| 2018 | } else if (dbus_sel == 0) { |
| 2019 | max_code = vco_code; |
| 2020 | max_cnt = dbus_sel; |
| 2021 | vco_code = (max_code + min_code)/2; |
| 2022 | } else if (dbus_sel > expected_counter_value) { |
| 2023 | min_code = vco_code; |
| 2024 | min_cnt = dbus_sel; |
| 2025 | vco_code = (max_code + min_code)/2; |
| 2026 | } else if (dbus_sel < expected_counter_value) { |
| 2027 | max_code = vco_code; |
| 2028 | max_cnt = dbus_sel; |
| 2029 | vco_code = (max_code + min_code)/2; |
| 2030 | } |
| 2031 | |
| 2032 | step++; |
| 2033 | |
| 2034 | if ((vco_code == 0) || (vco_code == 0x3FF) || (step > 0x3FF)) { |
| 2035 | DEV_ERR("%s: VCO tune code search failed\n", __func__); |
| 2036 | rc = -ENOTSUPP; |
| 2037 | break; |
| 2038 | } |
| 2039 | if ((max_code - min_code) <= 1) { |
| 2040 | if ((max_code - min_code) == 1) { |
| 2041 | if (abs((int)(max_cnt - expected_counter_value)) |
| 2042 | < abs((int)(min_cnt - expected_counter_value |
| 2043 | ))) { |
| 2044 | vco_code = max_code; |
| 2045 | } else { |
| 2046 | vco_code = min_code; |
| 2047 | } |
| 2048 | } |
| 2049 | break; |
| 2050 | } |
| 2051 | DEV_DBG("%s: loop[%d], new vco_code = %d\n", __func__, step, |
| 2052 | vco_code); |
| 2053 | } |
| 2054 | |
| 2055 | DEV_DBG("%s: CALIB done. vco_code = %d\n", __func__, vco_code); |
| 2056 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE1_MODE0, |
| 2057 | vco_code & 0xFF); |
| 2058 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VCO_TUNE2_MODE0, |
| 2059 | (vco_code >> 8) & 0x3); |
| 2060 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_LOCK_CMP_CFG); |
| 2061 | val &= ~BIT(1); |
| 2062 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_LOCK_CMP_CFG, val); |
| 2063 | |
| 2064 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); |
| 2065 | val |= BIT(4); |
| 2066 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); |
| 2067 | |
| 2068 | val = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_CMN_MISC1); |
| 2069 | val &= ~BIT(3); |
| 2070 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MISC1, val); |
| 2071 | |
| 2072 | return rc; |
| 2073 | } |
| 2074 | |
| 2075 | static int hdmi_8996_v2_perform_sw_calibration(struct clk *c) |
| 2076 | { |
| 2077 | int rc = 0; |
| 2078 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2079 | struct mdss_pll_resources *io = vco->priv; |
| 2080 | u32 vco_code1, vco_code2, integral_loop, ready_poll; |
| 2081 | u32 read_count = 0; |
| 2082 | |
| 2083 | while (read_count < (HDMI_PLL_POLL_MAX_READS << 1)) { |
| 2084 | ready_poll = MDSS_PLL_REG_R(io->pll_base, |
| 2085 | QSERDES_COM_C_READY_STATUS); |
| 2086 | if ((ready_poll & BIT(0)) == 1) { |
| 2087 | ready_poll = 1; |
| 2088 | DEV_DBG("%s: C READY\n", __func__); |
| 2089 | break; |
| 2090 | } |
| 2091 | udelay(HDMI_PLL_POLL_TIMEOUT_US); |
| 2092 | read_count++; |
| 2093 | } |
| 2094 | |
| 2095 | if (read_count == (HDMI_PLL_POLL_MAX_READS << 1)) { |
| 2096 | ready_poll = 0; |
| 2097 | DEV_DBG("%s: C READY TIMEOUT, TRYING SW CALIBRATION\n", |
| 2098 | __func__); |
| 2099 | } |
| 2100 | |
| 2101 | vco_code1 = MDSS_PLL_REG_R(io->pll_base, |
| 2102 | QSERDES_COM_PLLCAL_CODE1_STATUS); |
| 2103 | vco_code2 = MDSS_PLL_REG_R(io->pll_base, |
| 2104 | QSERDES_COM_PLLCAL_CODE2_STATUS); |
| 2105 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEBUG_BUS_SEL, 0x5); |
| 2106 | integral_loop = MDSS_PLL_REG_R(io->pll_base, |
| 2107 | QSERDES_COM_DEBUG_BUS0); |
| 2108 | |
| 2109 | if (((ready_poll & 0x1) == 0) || (((ready_poll & 1) == 1) && |
| 2110 | (vco_code1 == 0xFF) && ((vco_code2 & 0x3) == 0x1) && |
| 2111 | (integral_loop > 0xC0))) { |
| 2112 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL1, 0x04); |
| 2113 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL2, 0x00); |
| 2114 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x17); |
| 2115 | udelay(100); |
| 2116 | |
| 2117 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x11); |
| 2118 | udelay(100); |
| 2119 | |
| 2120 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19); |
| 2121 | } |
| 2122 | return rc; |
| 2123 | } |
| 2124 | |
| 2125 | static int hdmi_8996_perform_sw_calibration(struct clk *c, u32 ver) |
| 2126 | { |
| 2127 | switch (ver) { |
| 2128 | case HDMI_VERSION_8996_V1: |
| 2129 | return hdmi_8996_v1_perform_sw_calibration(c); |
| 2130 | case HDMI_VERSION_8996_V2: |
| 2131 | return hdmi_8996_v2_perform_sw_calibration(c); |
| 2132 | } |
| 2133 | return 0; |
| 2134 | } |
| 2135 | |
| 2136 | static int hdmi_8996_vco_enable(struct clk *c, u32 ver) |
| 2137 | { |
| 2138 | int rc = 0; |
| 2139 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2140 | struct mdss_pll_resources *io = vco->priv; |
| 2141 | |
| 2142 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x1); |
| 2143 | udelay(100); |
| 2144 | |
| 2145 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19); |
| 2146 | udelay(100); |
| 2147 | |
| 2148 | rc = hdmi_8996_perform_sw_calibration(c, ver); |
| 2149 | if (rc) { |
| 2150 | DEV_ERR("%s: software calibration failed\n", __func__); |
| 2151 | return rc; |
| 2152 | } |
| 2153 | |
| 2154 | rc = hdmi_8996_pll_lock_status(io); |
| 2155 | if (!rc) { |
| 2156 | DEV_ERR("%s: PLL not locked\n", __func__); |
| 2157 | return rc; |
| 2158 | } |
| 2159 | |
| 2160 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 2161 | QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, |
| 2162 | 0x6F); |
| 2163 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L1_BASE_OFFSET, |
| 2164 | QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, |
| 2165 | 0x6F); |
| 2166 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L2_BASE_OFFSET, |
| 2167 | QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, |
| 2168 | 0x6F); |
| 2169 | MDSS_PLL_REG_W(io->pll_base + HDMI_TX_L3_BASE_OFFSET, |
| 2170 | QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, |
| 2171 | 0x6F); |
| 2172 | |
| 2173 | /* Disable SSC */ |
| 2174 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_PER1, 0x0); |
| 2175 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_PER2, 0x0); |
| 2176 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_STEP_SIZE1, 0x0); |
| 2177 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_STEP_SIZE2, 0x0); |
| 2178 | MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_EN_CENTER, 0x2); |
| 2179 | |
| 2180 | rc = hdmi_8996_phy_ready_status(io); |
| 2181 | if (!rc) { |
| 2182 | DEV_ERR("%s: PHY not READY\n", __func__); |
| 2183 | return rc; |
| 2184 | } |
| 2185 | |
| 2186 | /* Restart the retiming buffer */ |
| 2187 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x18); |
| 2188 | udelay(1); |
| 2189 | MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19); |
| 2190 | |
| 2191 | io->pll_on = true; |
| 2192 | return 0; |
| 2193 | } |
| 2194 | |
| 2195 | static int hdmi_8996_v1_vco_enable(struct clk *c) |
| 2196 | { |
| 2197 | return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V1); |
| 2198 | } |
| 2199 | |
| 2200 | static int hdmi_8996_v2_vco_enable(struct clk *c) |
| 2201 | { |
| 2202 | return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V2); |
| 2203 | } |
| 2204 | |
| 2205 | static int hdmi_8996_v3_vco_enable(struct clk *c) |
| 2206 | { |
| 2207 | return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3); |
| 2208 | } |
| 2209 | |
| 2210 | static int hdmi_8996_v3_1p8_vco_enable(struct clk *c) |
| 2211 | { |
| 2212 | return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3_1_8); |
| 2213 | } |
| 2214 | |
| 2215 | static int hdmi_8996_vco_get_lock_range(struct clk *c, unsigned long pixel_clk) |
| 2216 | { |
| 2217 | u32 rng = 64, cmp_cnt = 1024; |
| 2218 | u32 coreclk_div = 5, clks_pll_divsel = 2; |
| 2219 | u32 vco_freq, vco_ratio, ppm_range; |
| 2220 | u64 bclk; |
| 2221 | struct hdmi_8996_v3_post_divider pd; |
| 2222 | |
| 2223 | bclk = ((u64)pixel_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO; |
| 2224 | |
| 2225 | DEV_DBG("%s: rate=%ld\n", __func__, pixel_clk); |
| 2226 | |
| 2227 | if (hdmi_8996_v3_get_post_div(&pd, bclk) || |
| 2228 | pd.vco_ratio <= 0 || pd.vco_freq <= 0) { |
| 2229 | DEV_ERR("%s: couldn't get post div\n", __func__); |
| 2230 | return -EINVAL; |
| 2231 | } |
| 2232 | |
| 2233 | do_div(pd.vco_freq, HDMI_KHZ_TO_HZ * HDMI_KHZ_TO_HZ); |
| 2234 | |
| 2235 | vco_freq = (u32) pd.vco_freq; |
| 2236 | vco_ratio = (u32) pd.vco_ratio; |
| 2237 | |
| 2238 | DEV_DBG("%s: freq %d, ratio %d\n", __func__, |
| 2239 | vco_freq, vco_ratio); |
| 2240 | |
| 2241 | ppm_range = (rng * HDMI_REF_CLOCK) / cmp_cnt; |
| 2242 | ppm_range /= vco_freq / vco_ratio; |
| 2243 | ppm_range *= coreclk_div * clks_pll_divsel; |
| 2244 | |
| 2245 | DEV_DBG("%s: ppm range: %d\n", __func__, ppm_range); |
| 2246 | |
| 2247 | return ppm_range; |
| 2248 | } |
| 2249 | |
| 2250 | static int hdmi_8996_vco_rate_atomic_update(struct clk *c, |
| 2251 | unsigned long rate, u32 ver) |
| 2252 | { |
| 2253 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2254 | struct mdss_pll_resources *io = vco->priv; |
| 2255 | void __iomem *pll; |
| 2256 | struct hdmi_8996_phy_pll_reg_cfg cfg = {0}; |
| 2257 | int rc = 0; |
| 2258 | |
| 2259 | rc = hdmi_8996_calculate(rate, &cfg, ver); |
| 2260 | if (rc) { |
| 2261 | DEV_ERR("%s: PLL calculation failed\n", __func__); |
| 2262 | goto end; |
| 2263 | } |
| 2264 | |
| 2265 | pll = io->pll_base; |
| 2266 | |
| 2267 | MDSS_PLL_REG_W(pll, QSERDES_COM_DEC_START_MODE0, |
| 2268 | cfg.com_dec_start_mode0); |
| 2269 | MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START1_MODE0, |
| 2270 | cfg.com_div_frac_start1_mode0); |
| 2271 | MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START2_MODE0, |
| 2272 | cfg.com_div_frac_start2_mode0); |
| 2273 | MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START3_MODE0, |
| 2274 | cfg.com_div_frac_start3_mode0); |
| 2275 | |
| 2276 | MDSS_PLL_REG_W(pll, QSERDES_COM_FREQ_UPDATE, 0x01); |
| 2277 | MDSS_PLL_REG_W(pll, QSERDES_COM_FREQ_UPDATE, 0x00); |
| 2278 | |
| 2279 | DEV_DBG("%s: updated to rate %ld\n", __func__, rate); |
| 2280 | end: |
| 2281 | return rc; |
| 2282 | } |
| 2283 | |
| 2284 | static int hdmi_8996_vco_set_rate(struct clk *c, unsigned long rate, u32 ver) |
| 2285 | { |
| 2286 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2287 | struct mdss_pll_resources *io = vco->priv; |
| 2288 | unsigned int set_power_dwn = 0; |
| 2289 | bool atomic_update = false; |
| 2290 | int rc, pll_lock_range; |
| 2291 | |
| 2292 | rc = mdss_pll_resource_enable(io, true); |
| 2293 | if (rc) { |
| 2294 | DEV_ERR("pll resource can't be enabled\n"); |
| 2295 | return rc; |
| 2296 | } |
| 2297 | |
| 2298 | DEV_DBG("%s: rate %ld\n", __func__, rate); |
| 2299 | |
| 2300 | if (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_C_READY_STATUS) & BIT(0) && |
| 2301 | MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS) & BIT(0)) { |
| 2302 | pll_lock_range = hdmi_8996_vco_get_lock_range(c, vco->rate); |
| 2303 | |
| 2304 | if (pll_lock_range > 0 && vco->rate) { |
| 2305 | u32 range_limit; |
| 2306 | |
| 2307 | range_limit = vco->rate * |
| 2308 | (pll_lock_range / HDMI_KHZ_TO_HZ); |
| 2309 | range_limit /= HDMI_KHZ_TO_HZ; |
| 2310 | |
| 2311 | DEV_DBG("%s: range limit %d\n", __func__, range_limit); |
| 2312 | |
| 2313 | if (abs(rate - vco->rate) < range_limit) |
| 2314 | atomic_update = true; |
| 2315 | } |
| 2316 | } |
| 2317 | |
| 2318 | if (io->pll_on && !atomic_update) |
| 2319 | set_power_dwn = 1; |
| 2320 | |
| 2321 | if (atomic_update) { |
| 2322 | hdmi_8996_vco_rate_atomic_update(c, rate, ver); |
| 2323 | } else { |
| 2324 | rc = hdmi_8996_phy_pll_set_clk_rate(c, rate, ver); |
| 2325 | if (rc) |
| 2326 | DEV_ERR("%s: Failed to set clk rate\n", __func__); |
| 2327 | } |
| 2328 | |
| 2329 | mdss_pll_resource_enable(io, false); |
| 2330 | |
| 2331 | if (set_power_dwn) |
| 2332 | hdmi_8996_vco_enable(c, ver); |
| 2333 | |
| 2334 | vco->rate = rate; |
| 2335 | vco->rate_set = true; |
| 2336 | |
| 2337 | return 0; |
| 2338 | } |
| 2339 | |
| 2340 | static int hdmi_8996_v1_vco_set_rate(struct clk *c, unsigned long rate) |
| 2341 | { |
| 2342 | return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V1); |
| 2343 | } |
| 2344 | |
| 2345 | static int hdmi_8996_v2_vco_set_rate(struct clk *c, unsigned long rate) |
| 2346 | { |
| 2347 | return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V2); |
| 2348 | } |
| 2349 | |
| 2350 | static int hdmi_8996_v3_vco_set_rate(struct clk *c, unsigned long rate) |
| 2351 | { |
| 2352 | return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3); |
| 2353 | } |
| 2354 | |
| 2355 | static int hdmi_8996_v3_1p8_vco_set_rate(struct clk *c, unsigned long rate) |
| 2356 | { |
| 2357 | return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3_1_8); |
| 2358 | } |
| 2359 | |
| 2360 | static unsigned long hdmi_get_hsclk_sel_divisor(unsigned long hsclk_sel) |
| 2361 | { |
| 2362 | unsigned long divisor; |
| 2363 | |
| 2364 | switch (hsclk_sel) { |
| 2365 | case 0: |
| 2366 | divisor = 2; |
| 2367 | break; |
| 2368 | case 1: |
| 2369 | divisor = 6; |
| 2370 | break; |
| 2371 | case 2: |
| 2372 | divisor = 10; |
| 2373 | break; |
| 2374 | case 3: |
| 2375 | divisor = 14; |
| 2376 | break; |
| 2377 | case 4: |
| 2378 | divisor = 3; |
| 2379 | break; |
| 2380 | case 5: |
| 2381 | divisor = 9; |
| 2382 | break; |
| 2383 | case 6: |
| 2384 | case 13: |
| 2385 | divisor = 15; |
| 2386 | break; |
| 2387 | case 7: |
| 2388 | divisor = 21; |
| 2389 | break; |
| 2390 | case 8: |
| 2391 | divisor = 4; |
| 2392 | break; |
| 2393 | case 9: |
| 2394 | divisor = 12; |
| 2395 | break; |
| 2396 | case 10: |
| 2397 | divisor = 20; |
| 2398 | break; |
| 2399 | case 11: |
| 2400 | divisor = 28; |
| 2401 | break; |
| 2402 | case 12: |
| 2403 | divisor = 5; |
| 2404 | break; |
| 2405 | case 14: |
| 2406 | divisor = 25; |
| 2407 | break; |
| 2408 | case 15: |
| 2409 | divisor = 35; |
| 2410 | break; |
| 2411 | default: |
| 2412 | divisor = 1; |
| 2413 | DEV_ERR("%s: invalid hsclk_sel value = %lu", |
| 2414 | __func__, hsclk_sel); |
| 2415 | break; |
| 2416 | } |
| 2417 | |
| 2418 | return divisor; |
| 2419 | } |
| 2420 | |
| 2421 | static unsigned long hdmi_8996_vco_get_rate(struct clk *c) |
| 2422 | { |
| 2423 | unsigned long freq = 0, hsclk_sel = 0, tx_band = 0, dec_start = 0, |
| 2424 | div_frac_start = 0, vco_clock_freq = 0; |
| 2425 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2426 | struct mdss_pll_resources *io = vco->priv; |
| 2427 | |
| 2428 | if (mdss_pll_resource_enable(io, true)) { |
| 2429 | DEV_ERR("%s: pll resource can't be enabled\n", __func__); |
| 2430 | return freq; |
| 2431 | } |
| 2432 | |
| 2433 | dec_start = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEC_START_MODE0); |
| 2434 | |
| 2435 | div_frac_start = |
| 2436 | MDSS_PLL_REG_R(io->pll_base, |
| 2437 | QSERDES_COM_DIV_FRAC_START1_MODE0) | |
| 2438 | MDSS_PLL_REG_R(io->pll_base, |
| 2439 | QSERDES_COM_DIV_FRAC_START2_MODE0) << 8 | |
| 2440 | MDSS_PLL_REG_R(io->pll_base, |
| 2441 | QSERDES_COM_DIV_FRAC_START3_MODE0) << 16; |
| 2442 | |
| 2443 | vco_clock_freq = (dec_start + (div_frac_start / (1 << 20))) |
| 2444 | * 4 * (HDMI_REF_CLOCK); |
| 2445 | |
| 2446 | hsclk_sel = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_HSCLK_SEL) & 0x15; |
| 2447 | hsclk_sel = hdmi_get_hsclk_sel_divisor(hsclk_sel); |
| 2448 | tx_band = MDSS_PLL_REG_R(io->pll_base + HDMI_TX_L0_BASE_OFFSET, |
| 2449 | QSERDES_TX_L0_TX_BAND) & 0x3; |
| 2450 | |
| 2451 | freq = vco_clock_freq / (10 * hsclk_sel * (1 << tx_band)); |
| 2452 | |
| 2453 | mdss_pll_resource_enable(io, false); |
| 2454 | |
| 2455 | DEV_DBG("%s: freq = %lu\n", __func__, freq); |
| 2456 | |
| 2457 | return freq; |
| 2458 | } |
| 2459 | |
| 2460 | static long hdmi_8996_vco_round_rate(struct clk *c, unsigned long rate) |
| 2461 | { |
| 2462 | unsigned long rrate = rate; |
| 2463 | |
| 2464 | DEV_DBG("rrate=%ld\n", rrate); |
| 2465 | |
| 2466 | return rrate; |
| 2467 | } |
| 2468 | |
| 2469 | static int hdmi_8996_vco_prepare(struct clk *c, u32 ver) |
| 2470 | { |
| 2471 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2472 | struct mdss_pll_resources *io = vco->priv; |
| 2473 | int ret = 0; |
| 2474 | |
| 2475 | DEV_DBG("rate=%ld\n", vco->rate); |
| 2476 | |
| 2477 | if (!vco->rate_set && vco->rate) |
| 2478 | ret = hdmi_8996_vco_set_rate(c, vco->rate, ver); |
| 2479 | |
| 2480 | if (!ret) { |
| 2481 | ret = mdss_pll_resource_enable(io, true); |
| 2482 | if (ret) |
| 2483 | DEV_ERR("pll resource can't be enabled\n"); |
| 2484 | } |
| 2485 | |
| 2486 | return ret; |
| 2487 | } |
| 2488 | |
| 2489 | static int hdmi_8996_v1_vco_prepare(struct clk *c) |
| 2490 | { |
| 2491 | return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V1); |
| 2492 | } |
| 2493 | |
| 2494 | static int hdmi_8996_v2_vco_prepare(struct clk *c) |
| 2495 | { |
| 2496 | return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V2); |
| 2497 | } |
| 2498 | |
| 2499 | static int hdmi_8996_v3_vco_prepare(struct clk *c) |
| 2500 | { |
| 2501 | return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V3); |
| 2502 | } |
| 2503 | |
| 2504 | static int hdmi_8996_v3_1p8_vco_prepare(struct clk *c) |
| 2505 | { |
| 2506 | return hdmi_8996_vco_prepare(c, HDMI_VERSION_8996_V3_1_8); |
| 2507 | } |
| 2508 | |
| 2509 | static void hdmi_8996_vco_unprepare(struct clk *c) |
| 2510 | { |
| 2511 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2512 | struct mdss_pll_resources *io = vco->priv; |
| 2513 | |
| 2514 | vco->rate_set = false; |
| 2515 | |
| 2516 | if (!io) { |
| 2517 | DEV_ERR("Invalid input parameter\n"); |
| 2518 | return; |
| 2519 | } |
| 2520 | |
| 2521 | if (!io->pll_on && |
| 2522 | mdss_pll_resource_enable(io, true)) { |
| 2523 | DEV_ERR("pll resource can't be enabled\n"); |
| 2524 | return; |
| 2525 | } |
| 2526 | |
| 2527 | io->handoff_resources = false; |
| 2528 | mdss_pll_resource_enable(io, false); |
| 2529 | io->pll_on = false; |
| 2530 | } |
| 2531 | |
| 2532 | static enum handoff hdmi_8996_vco_handoff(struct clk *c) |
| 2533 | { |
| 2534 | enum handoff ret = HANDOFF_DISABLED_CLK; |
| 2535 | struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c); |
| 2536 | struct mdss_pll_resources *io = vco->priv; |
| 2537 | |
| 2538 | if (is_gdsc_disabled(io)) |
| 2539 | return HANDOFF_DISABLED_CLK; |
| 2540 | |
| 2541 | if (mdss_pll_resource_enable(io, true)) { |
| 2542 | DEV_ERR("pll resource can't be enabled\n"); |
| 2543 | return ret; |
| 2544 | } |
| 2545 | |
| 2546 | io->handoff_resources = true; |
| 2547 | |
| 2548 | if (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_C_READY_STATUS) & BIT(0)) { |
| 2549 | if (MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS) & BIT(0)) { |
| 2550 | io->pll_on = true; |
| 2551 | c->rate = hdmi_8996_vco_get_rate(c); |
| 2552 | vco->rate = c->rate; |
| 2553 | ret = HANDOFF_ENABLED_CLK; |
| 2554 | } else { |
| 2555 | io->handoff_resources = false; |
| 2556 | mdss_pll_resource_enable(io, false); |
| 2557 | DEV_DBG("%s: PHY not ready\n", __func__); |
| 2558 | } |
| 2559 | } else { |
| 2560 | io->handoff_resources = false; |
| 2561 | mdss_pll_resource_enable(io, false); |
| 2562 | DEV_DBG("%s: PLL not locked\n", __func__); |
| 2563 | } |
| 2564 | |
| 2565 | DEV_DBG("done, ret=%d\n", ret); |
| 2566 | return ret; |
| 2567 | } |
| 2568 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 2569 | static const struct clk_ops hdmi_8996_v1_vco_clk_ops = { |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 2570 | .enable = hdmi_8996_v1_vco_enable, |
| 2571 | .set_rate = hdmi_8996_v1_vco_set_rate, |
| 2572 | .get_rate = hdmi_8996_vco_get_rate, |
| 2573 | .round_rate = hdmi_8996_vco_round_rate, |
| 2574 | .prepare = hdmi_8996_v1_vco_prepare, |
| 2575 | .unprepare = hdmi_8996_vco_unprepare, |
| 2576 | .handoff = hdmi_8996_vco_handoff, |
| 2577 | }; |
| 2578 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 2579 | static const struct clk_ops hdmi_8996_v2_vco_clk_ops = { |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 2580 | .enable = hdmi_8996_v2_vco_enable, |
| 2581 | .set_rate = hdmi_8996_v2_vco_set_rate, |
| 2582 | .get_rate = hdmi_8996_vco_get_rate, |
| 2583 | .round_rate = hdmi_8996_vco_round_rate, |
| 2584 | .prepare = hdmi_8996_v2_vco_prepare, |
| 2585 | .unprepare = hdmi_8996_vco_unprepare, |
| 2586 | .handoff = hdmi_8996_vco_handoff, |
| 2587 | }; |
| 2588 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 2589 | static const struct clk_ops hdmi_8996_v3_vco_clk_ops = { |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 2590 | .enable = hdmi_8996_v3_vco_enable, |
| 2591 | .set_rate = hdmi_8996_v3_vco_set_rate, |
| 2592 | .get_rate = hdmi_8996_vco_get_rate, |
| 2593 | .round_rate = hdmi_8996_vco_round_rate, |
| 2594 | .prepare = hdmi_8996_v3_vco_prepare, |
| 2595 | .unprepare = hdmi_8996_vco_unprepare, |
| 2596 | .handoff = hdmi_8996_vco_handoff, |
| 2597 | }; |
| 2598 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 2599 | static const struct clk_ops hdmi_8996_v3_1p8_vco_clk_ops = { |
Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 2600 | .enable = hdmi_8996_v3_1p8_vco_enable, |
| 2601 | .set_rate = hdmi_8996_v3_1p8_vco_set_rate, |
| 2602 | .get_rate = hdmi_8996_vco_get_rate, |
| 2603 | .round_rate = hdmi_8996_vco_round_rate, |
| 2604 | .prepare = hdmi_8996_v3_1p8_vco_prepare, |
| 2605 | .unprepare = hdmi_8996_vco_unprepare, |
| 2606 | .handoff = hdmi_8996_vco_handoff, |
| 2607 | }; |
| 2608 | |
| 2609 | |
| 2610 | static struct hdmi_pll_vco_clk hdmi_vco_clk = { |
| 2611 | .c = { |
| 2612 | .dbg_name = "hdmi_8996_vco_clk", |
| 2613 | .ops = &hdmi_8996_v1_vco_clk_ops, |
| 2614 | .flags = CLKFLAG_NO_RATE_CACHE, |
| 2615 | CLK_INIT(hdmi_vco_clk.c), |
| 2616 | }, |
| 2617 | }; |
| 2618 | |
| 2619 | static struct clk_lookup hdmipllcc_8996[] = { |
| 2620 | CLK_LIST(hdmi_vco_clk), |
| 2621 | }; |
| 2622 | |
| 2623 | int hdmi_8996_pll_clock_register(struct platform_device *pdev, |
| 2624 | struct mdss_pll_resources *pll_res, u32 ver) |
| 2625 | { |
| 2626 | int rc = -ENOTSUPP; |
| 2627 | |
| 2628 | if (!pll_res || !pll_res->phy_base || !pll_res->pll_base) { |
| 2629 | DEV_ERR("%s: Invalid input parameters\n", __func__); |
| 2630 | return -EPROBE_DEFER; |
| 2631 | } |
| 2632 | |
| 2633 | /* Set client data for vco, mux and div clocks */ |
| 2634 | hdmi_vco_clk.priv = pll_res; |
| 2635 | |
| 2636 | switch (ver) { |
| 2637 | case HDMI_VERSION_8996_V2: |
| 2638 | hdmi_vco_clk.c.ops = &hdmi_8996_v2_vco_clk_ops; |
| 2639 | break; |
| 2640 | case HDMI_VERSION_8996_V3: |
| 2641 | hdmi_vco_clk.c.ops = &hdmi_8996_v3_vco_clk_ops; |
| 2642 | break; |
| 2643 | case HDMI_VERSION_8996_V3_1_8: |
| 2644 | hdmi_vco_clk.c.ops = &hdmi_8996_v3_1p8_vco_clk_ops; |
| 2645 | break; |
| 2646 | default: |
| 2647 | hdmi_vco_clk.c.ops = &hdmi_8996_v1_vco_clk_ops; |
| 2648 | break; |
| 2649 | }; |
| 2650 | |
| 2651 | rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_8996, |
| 2652 | ARRAY_SIZE(hdmipllcc_8996)); |
| 2653 | if (rc) { |
| 2654 | DEV_ERR("%s: Clock register failed rc=%d\n", __func__, rc); |
| 2655 | rc = -EPROBE_DEFER; |
| 2656 | } else { |
| 2657 | DEV_DBG("%s SUCCESS\n", __func__); |
| 2658 | } |
| 2659 | |
| 2660 | return rc; |
| 2661 | } |
| 2662 | |
| 2663 | int hdmi_8996_v1_pll_clock_register(struct platform_device *pdev, |
| 2664 | struct mdss_pll_resources *pll_res) |
| 2665 | { |
| 2666 | return hdmi_8996_pll_clock_register(pdev, pll_res, |
| 2667 | HDMI_VERSION_8996_V1); |
| 2668 | } |
| 2669 | |
| 2670 | int hdmi_8996_v2_pll_clock_register(struct platform_device *pdev, |
| 2671 | struct mdss_pll_resources *pll_res) |
| 2672 | { |
| 2673 | return hdmi_8996_pll_clock_register(pdev, pll_res, |
| 2674 | HDMI_VERSION_8996_V2); |
| 2675 | } |
| 2676 | |
| 2677 | int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev, |
| 2678 | struct mdss_pll_resources *pll_res) |
| 2679 | { |
| 2680 | return hdmi_8996_pll_clock_register(pdev, pll_res, |
| 2681 | HDMI_VERSION_8996_V3); |
| 2682 | } |
| 2683 | |
| 2684 | int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev, |
| 2685 | struct mdss_pll_resources *pll_res) |
| 2686 | { |
| 2687 | return hdmi_8996_pll_clock_register(pdev, pll_res, |
| 2688 | HDMI_VERSION_8996_V3_1_8); |
| 2689 | } |