Srinu Gorle | cf8c675 | 2018-01-19 18:36:13 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef __MSM_VIDC_RESOURCES_H__ |
| 15 | #define __MSM_VIDC_RESOURCES_H__ |
| 16 | |
| 17 | #include <linux/devfreq.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <media/msm_vidc.h> |
| 20 | #define MAX_BUFFER_TYPES 32 |
| 21 | |
| 22 | struct version_table { |
| 23 | u32 version_mask; |
| 24 | u32 version_shift; |
| 25 | }; |
| 26 | |
| 27 | struct load_freq_table { |
| 28 | u32 load; |
| 29 | u32 freq; |
| 30 | u32 supported_codecs; |
| 31 | }; |
| 32 | |
| 33 | struct dcvs_table { |
| 34 | u32 load; |
| 35 | u32 load_low; |
| 36 | u32 load_high; |
| 37 | u32 supported_codecs; |
| 38 | }; |
| 39 | |
| 40 | struct dcvs_limit { |
| 41 | u32 min_mbpf; |
| 42 | u32 fps; |
| 43 | }; |
| 44 | |
| 45 | struct imem_ab_table { |
| 46 | u32 core_freq; |
| 47 | u32 imem_ab; |
| 48 | }; |
| 49 | |
| 50 | struct reg_value_pair { |
| 51 | u32 reg; |
| 52 | u32 value; |
| 53 | }; |
| 54 | |
| 55 | struct reg_set { |
| 56 | struct reg_value_pair *reg_tbl; |
| 57 | int count; |
| 58 | }; |
| 59 | |
| 60 | struct addr_range { |
| 61 | u32 start; |
| 62 | u32 size; |
| 63 | }; |
| 64 | |
| 65 | struct addr_set { |
| 66 | struct addr_range *addr_tbl; |
| 67 | int count; |
| 68 | }; |
| 69 | |
| 70 | struct context_bank_info { |
| 71 | struct list_head list; |
| 72 | const char *name; |
| 73 | u32 buffer_type; |
| 74 | bool is_secure; |
| 75 | struct addr_range addr_range; |
| 76 | struct device *dev; |
| 77 | struct dma_iommu_mapping *mapping; |
| 78 | }; |
| 79 | |
| 80 | struct buffer_usage_table { |
| 81 | u32 buffer_type; |
| 82 | u32 tz_usage; |
| 83 | }; |
| 84 | |
| 85 | struct buffer_usage_set { |
| 86 | struct buffer_usage_table *buffer_usage_tbl; |
| 87 | u32 count; |
| 88 | }; |
| 89 | |
| 90 | struct regulator_info { |
| 91 | struct regulator *regulator; |
| 92 | bool has_hw_power_collapse; |
| 93 | char *name; |
| 94 | }; |
| 95 | |
| 96 | struct regulator_set { |
| 97 | struct regulator_info *regulator_tbl; |
| 98 | u32 count; |
| 99 | }; |
| 100 | |
| 101 | struct clock_info { |
| 102 | const char *name; |
| 103 | struct clk *clk; |
| 104 | struct load_freq_table *load_freq_tbl; |
| 105 | u32 count; |
| 106 | bool has_scaling; |
| 107 | }; |
| 108 | |
| 109 | struct clock_set { |
| 110 | struct clock_info *clock_tbl; |
| 111 | u32 count; |
| 112 | }; |
| 113 | |
| 114 | struct bus_info { |
| 115 | char *name; |
| 116 | int master; |
| 117 | int slave; |
| 118 | unsigned int range[2]; |
| 119 | const char *governor; |
| 120 | struct device *dev; |
| 121 | struct devfreq_dev_profile devfreq_prof; |
| 122 | struct devfreq *devfreq; |
| 123 | struct msm_bus_client_handle *client; |
| 124 | }; |
| 125 | |
| 126 | struct bus_set { |
| 127 | struct bus_info *bus_tbl; |
| 128 | u32 count; |
| 129 | }; |
| 130 | |
| 131 | enum imem_type { |
| 132 | IMEM_NONE, |
| 133 | IMEM_OCMEM, |
| 134 | IMEM_VMEM, |
| 135 | IMEM_MAX, |
| 136 | }; |
| 137 | |
| 138 | struct allowed_clock_rates_table { |
| 139 | u32 clock_rate; |
| 140 | }; |
| 141 | |
| 142 | struct clock_profile_entry { |
| 143 | u32 codec_mask; |
| 144 | u32 cycles; |
| 145 | u32 low_power_factor; |
| 146 | }; |
| 147 | |
| 148 | struct clock_freq_table { |
| 149 | struct clock_profile_entry *clk_prof_entries; |
| 150 | u32 count; |
| 151 | }; |
| 152 | |
| 153 | struct msm_vidc_platform_resources { |
| 154 | phys_addr_t firmware_base; |
| 155 | phys_addr_t register_base; |
| 156 | uint32_t register_size; |
| 157 | uint32_t irq; |
| 158 | struct version_table *pf_ver_tbl; |
| 159 | struct version_table *pf_cap_tbl; |
| 160 | struct version_table *pf_speedbin_tbl; |
| 161 | struct allowed_clock_rates_table *allowed_clks_tbl; |
| 162 | u32 allowed_clks_tbl_size; |
| 163 | struct clock_freq_table clock_freq_tbl; |
| 164 | struct load_freq_table *load_freq_tbl; |
| 165 | uint32_t load_freq_tbl_size; |
| 166 | struct dcvs_table *dcvs_tbl; |
| 167 | uint32_t dcvs_tbl_size; |
| 168 | struct dcvs_limit *dcvs_limit; |
| 169 | struct imem_ab_table *imem_ab_tbl; |
| 170 | u32 imem_ab_tbl_size; |
| 171 | struct reg_set reg_set; |
| 172 | struct addr_set qdss_addr_set; |
| 173 | struct buffer_usage_set buffer_usage_set; |
| 174 | uint32_t imem_size; |
| 175 | enum imem_type imem_type; |
| 176 | uint32_t max_load; |
| 177 | struct platform_device *pdev; |
| 178 | struct regulator_set regulator_set; |
| 179 | struct clock_set clock_set; |
| 180 | struct bus_set bus_set; |
| 181 | bool use_non_secure_pil; |
| 182 | bool sw_power_collapsible; |
| 183 | bool sys_idle_indicator; |
| 184 | bool slave_side_cp; |
| 185 | struct list_head context_banks; |
| 186 | bool thermal_mitigable; |
| 187 | const char *fw_name; |
| 188 | const char *hfi_version; |
| 189 | bool never_unload_fw; |
| 190 | uint32_t pm_qos_latency_us; |
| 191 | uint32_t max_inst_count; |
| 192 | uint32_t max_secure_inst_count; |
| 193 | }; |
| 194 | |
| 195 | static inline bool is_iommu_present(struct msm_vidc_platform_resources *res) |
| 196 | { |
| 197 | return !list_empty(&res->context_banks); |
| 198 | } |
| 199 | |
| 200 | extern uint32_t msm_vidc_pwr_collapse_delay; |
| 201 | |
| 202 | #endif |
| 203 | |