Srinu Gorle | cf8c675 | 2018-01-19 18:36:13 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef __VIDC_HFI_API_H__ |
| 15 | #define __VIDC_HFI_API_H__ |
| 16 | |
| 17 | #include <linux/log2.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/types.h> |
| 20 | #include <media/msm_vidc.h> |
| 21 | #include "msm_vidc_resources.h" |
| 22 | |
| 23 | #define CONTAINS(__a, __sz, __t) ({\ |
| 24 | int __rc = __t >= __a && \ |
| 25 | __t < __a + __sz; \ |
| 26 | __rc; \ |
| 27 | }) |
| 28 | |
| 29 | #define OVERLAPS(__t, __tsz, __a, __asz) ({\ |
| 30 | int __rc = __t <= __a && \ |
| 31 | __t + __tsz >= __a + __asz; \ |
| 32 | __rc; \ |
| 33 | }) |
| 34 | |
| 35 | #define HAL_BUFFERFLAG_EOS 0x00000001 |
| 36 | #define HAL_BUFFERFLAG_STARTTIME 0x00000002 |
| 37 | #define HAL_BUFFERFLAG_DECODEONLY 0x00000004 |
| 38 | #define HAL_BUFFERFLAG_DATACORRUPT 0x00000008 |
| 39 | #define HAL_BUFFERFLAG_ENDOFFRAME 0x00000010 |
| 40 | #define HAL_BUFFERFLAG_SYNCFRAME 0x00000020 |
| 41 | #define HAL_BUFFERFLAG_EXTRADATA 0x00000040 |
| 42 | #define HAL_BUFFERFLAG_CODECCONFIG 0x00000080 |
| 43 | #define HAL_BUFFERFLAG_TIMESTAMPINVALID 0x00000100 |
| 44 | #define HAL_BUFFERFLAG_READONLY 0x00000200 |
| 45 | #define HAL_BUFFERFLAG_ENDOFSUBFRAME 0x00000400 |
| 46 | #define HAL_BUFFERFLAG_EOSEQ 0x00200000 |
| 47 | #define HAL_BUFFERFLAG_MBAFF 0x08000000 |
| 48 | #define HAL_BUFFERFLAG_YUV_601_709_CSC_CLAMP 0x10000000 |
| 49 | #define HAL_BUFFERFLAG_DROP_FRAME 0x20000000 |
| 50 | #define HAL_BUFFERFLAG_TS_DISCONTINUITY 0x40000000 |
| 51 | #define HAL_BUFFERFLAG_TS_ERROR 0x80000000 |
| 52 | |
| 53 | |
| 54 | |
| 55 | #define HAL_DEBUG_MSG_LOW 0x00000001 |
| 56 | #define HAL_DEBUG_MSG_MEDIUM 0x00000002 |
| 57 | #define HAL_DEBUG_MSG_HIGH 0x00000004 |
| 58 | #define HAL_DEBUG_MSG_ERROR 0x00000008 |
| 59 | #define HAL_DEBUG_MSG_FATAL 0x00000010 |
| 60 | #define MAX_PROFILE_COUNT 16 |
| 61 | |
| 62 | #define HAL_MAX_MATRIX_COEFFS 9 |
| 63 | #define HAL_MAX_BIAS_COEFFS 3 |
| 64 | #define HAL_MAX_LIMIT_COEFFS 6 |
| 65 | #define VENUS_VERSION_LENGTH 128 |
| 66 | |
| 67 | /* 16 encoder and 16 decoder sessions */ |
| 68 | #define VIDC_MAX_SESSIONS 32 |
| 69 | |
| 70 | enum vidc_status { |
| 71 | VIDC_ERR_NONE = 0x0, |
| 72 | VIDC_ERR_FAIL = 0x80000000, |
| 73 | VIDC_ERR_ALLOC_FAIL, |
| 74 | VIDC_ERR_ILLEGAL_OP, |
| 75 | VIDC_ERR_BAD_PARAM, |
| 76 | VIDC_ERR_BAD_HANDLE, |
| 77 | VIDC_ERR_NOT_SUPPORTED, |
| 78 | VIDC_ERR_BAD_STATE, |
| 79 | VIDC_ERR_MAX_CLIENTS, |
| 80 | VIDC_ERR_IFRAME_EXPECTED, |
| 81 | VIDC_ERR_HW_FATAL, |
| 82 | VIDC_ERR_BITSTREAM_ERR, |
| 83 | VIDC_ERR_INDEX_NOMORE, |
| 84 | VIDC_ERR_SEQHDR_PARSE_FAIL, |
| 85 | VIDC_ERR_INSUFFICIENT_BUFFER, |
| 86 | VIDC_ERR_BAD_POWER_STATE, |
| 87 | VIDC_ERR_NO_VALID_SESSION, |
| 88 | VIDC_ERR_TIMEOUT, |
| 89 | VIDC_ERR_CMDQFULL, |
| 90 | VIDC_ERR_START_CODE_NOT_FOUND, |
| 91 | VIDC_ERR_CLIENT_PRESENT = 0x90000001, |
| 92 | VIDC_ERR_CLIENT_FATAL, |
| 93 | VIDC_ERR_CMD_QUEUE_FULL, |
| 94 | VIDC_ERR_UNUSED = 0x10000000 |
| 95 | }; |
| 96 | |
| 97 | enum hal_extradata_id { |
| 98 | HAL_EXTRADATA_NONE, |
| 99 | HAL_EXTRADATA_MB_QUANTIZATION, |
| 100 | HAL_EXTRADATA_INTERLACE_VIDEO, |
| 101 | HAL_EXTRADATA_VC1_FRAMEDISP, |
| 102 | HAL_EXTRADATA_VC1_SEQDISP, |
| 103 | HAL_EXTRADATA_TIMESTAMP, |
| 104 | HAL_EXTRADATA_S3D_FRAME_PACKING, |
| 105 | HAL_EXTRADATA_FRAME_RATE, |
| 106 | HAL_EXTRADATA_PANSCAN_WINDOW, |
| 107 | HAL_EXTRADATA_RECOVERY_POINT_SEI, |
| 108 | HAL_EXTRADATA_MULTISLICE_INFO, |
| 109 | HAL_EXTRADATA_INDEX, |
| 110 | HAL_EXTRADATA_NUM_CONCEALED_MB, |
| 111 | HAL_EXTRADATA_METADATA_FILLER, |
| 112 | HAL_EXTRADATA_ASPECT_RATIO, |
| 113 | HAL_EXTRADATA_MPEG2_SEQDISP, |
| 114 | HAL_EXTRADATA_STREAM_USERDATA, |
| 115 | HAL_EXTRADATA_FRAME_QP, |
| 116 | HAL_EXTRADATA_FRAME_BITS_INFO, |
| 117 | HAL_EXTRADATA_INPUT_CROP, |
| 118 | HAL_EXTRADATA_DIGITAL_ZOOM, |
| 119 | HAL_EXTRADATA_LTR_INFO, |
| 120 | HAL_EXTRADATA_METADATA_MBI, |
| 121 | HAL_EXTRADATA_VQZIP_SEI, |
| 122 | HAL_EXTRADATA_YUV_STATS, |
| 123 | HAL_EXTRADATA_ROI_QP, |
| 124 | HAL_EXTRADATA_OUTPUT_CROP, |
| 125 | HAL_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI, |
| 126 | HAL_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI, |
| 127 | HAL_EXTRADATA_VUI_DISPLAY_INFO, |
| 128 | HAL_EXTRADATA_VPX_COLORSPACE, |
| 129 | HAL_EXTRADATA_PQ_INFO, |
| 130 | }; |
| 131 | |
| 132 | enum hal_property { |
| 133 | HAL_CONFIG_FRAME_RATE = 0x04000001, |
| 134 | HAL_PARAM_UNCOMPRESSED_FORMAT_SELECT, |
| 135 | HAL_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO, |
| 136 | HAL_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO, |
| 137 | HAL_PARAM_EXTRA_DATA_HEADER_CONFIG, |
| 138 | HAL_PARAM_INDEX_EXTRADATA, |
| 139 | HAL_PARAM_FRAME_SIZE, |
| 140 | HAL_CONFIG_REALTIME, |
| 141 | HAL_PARAM_BUFFER_COUNT_ACTUAL, |
| 142 | HAL_PARAM_BUFFER_SIZE_MINIMUM, |
| 143 | HAL_PARAM_NAL_STREAM_FORMAT_SELECT, |
| 144 | HAL_PARAM_VDEC_OUTPUT_ORDER, |
| 145 | HAL_PARAM_VDEC_PICTURE_TYPE_DECODE, |
| 146 | HAL_PARAM_VDEC_OUTPUT2_KEEP_ASPECT_RATIO, |
| 147 | HAL_CONFIG_VDEC_POST_LOOP_DEBLOCKER, |
| 148 | HAL_PARAM_VDEC_MULTI_STREAM, |
| 149 | HAL_PARAM_VDEC_DISPLAY_PICTURE_BUFFER_COUNT, |
| 150 | HAL_PARAM_DIVX_FORMAT, |
| 151 | HAL_CONFIG_VDEC_MB_ERROR_MAP_REPORTING, |
| 152 | HAL_PARAM_VDEC_CONTINUE_DATA_TRANSFER, |
| 153 | HAL_CONFIG_VDEC_MB_ERROR_MAP, |
| 154 | HAL_CONFIG_VENC_REQUEST_IFRAME, |
| 155 | HAL_PARAM_VENC_MPEG4_SHORT_HEADER, |
| 156 | HAL_PARAM_VENC_MPEG4_AC_PREDICTION, |
| 157 | HAL_CONFIG_VENC_TARGET_BITRATE, |
| 158 | HAL_PARAM_PROFILE_LEVEL_CURRENT, |
| 159 | HAL_PARAM_VENC_H264_ENTROPY_CONTROL, |
| 160 | HAL_PARAM_VENC_RATE_CONTROL, |
| 161 | HAL_PARAM_VENC_MPEG4_TIME_RESOLUTION, |
| 162 | HAL_PARAM_VENC_MPEG4_HEADER_EXTENSION, |
| 163 | HAL_PARAM_VENC_H264_DEBLOCK_CONTROL, |
| 164 | HAL_PARAM_VENC_TEMPORAL_SPATIAL_TRADEOFF, |
| 165 | HAL_PARAM_VENC_SESSION_QP, |
| 166 | HAL_PARAM_VENC_SESSION_QP_RANGE, |
| 167 | HAL_CONFIG_VENC_INTRA_PERIOD, |
| 168 | HAL_CONFIG_VENC_IDR_PERIOD, |
| 169 | HAL_CONFIG_VPE_OPERATIONS, |
| 170 | HAL_PARAM_VENC_INTRA_REFRESH, |
| 171 | HAL_PARAM_VENC_MULTI_SLICE_CONTROL, |
| 172 | HAL_CONFIG_VPE_DEINTERLACE, |
| 173 | HAL_SYS_DEBUG_CONFIG, |
| 174 | HAL_CONFIG_BUFFER_REQUIREMENTS, |
| 175 | HAL_CONFIG_PRIORITY, |
| 176 | HAL_CONFIG_BATCH_INFO, |
| 177 | HAL_PARAM_METADATA_PASS_THROUGH, |
| 178 | HAL_SYS_IDLE_INDICATOR, |
| 179 | HAL_PARAM_UNCOMPRESSED_FORMAT_SUPPORTED, |
| 180 | HAL_PARAM_INTERLACE_FORMAT_SUPPORTED, |
| 181 | HAL_PARAM_CHROMA_SITE, |
| 182 | HAL_PARAM_PROPERTIES_SUPPORTED, |
| 183 | HAL_PARAM_PROFILE_LEVEL_SUPPORTED, |
| 184 | HAL_PARAM_CAPABILITY_SUPPORTED, |
| 185 | HAL_PARAM_NAL_STREAM_FORMAT_SUPPORTED, |
| 186 | HAL_PARAM_MULTI_VIEW_FORMAT, |
| 187 | HAL_PARAM_MAX_SEQUENCE_HEADER_SIZE, |
| 188 | HAL_PARAM_CODEC_SUPPORTED, |
| 189 | HAL_PARAM_VDEC_MULTI_VIEW_SELECT, |
| 190 | HAL_PARAM_VDEC_MB_QUANTIZATION, |
| 191 | HAL_PARAM_VDEC_NUM_CONCEALED_MB, |
| 192 | HAL_PARAM_VDEC_H264_ENTROPY_SWITCHING, |
| 193 | HAL_PARAM_VENC_SLICE_DELIVERY_MODE, |
| 194 | HAL_PARAM_VENC_MPEG4_DATA_PARTITIONING, |
| 195 | HAL_CONFIG_BUFFER_COUNT_ACTUAL, |
| 196 | HAL_CONFIG_VDEC_MULTI_STREAM, |
| 197 | HAL_PARAM_VENC_MULTI_SLICE_INFO, |
| 198 | HAL_CONFIG_VENC_TIMESTAMP_SCALE, |
| 199 | HAL_PARAM_VENC_SYNC_FRAME_SEQUENCE_HEADER, |
| 200 | HAL_PARAM_VDEC_SYNC_FRAME_DECODE, |
| 201 | HAL_PARAM_VENC_H264_ENTROPY_CABAC_MODEL, |
| 202 | HAL_CONFIG_VENC_MAX_BITRATE, |
| 203 | HAL_PARAM_VENC_H264_VUI_TIMING_INFO, |
| 204 | HAL_PARAM_VENC_GENERATE_AUDNAL, |
| 205 | HAL_PARAM_VENC_MAX_NUM_B_FRAMES, |
| 206 | HAL_PARAM_BUFFER_ALLOC_MODE, |
| 207 | HAL_PARAM_VDEC_FRAME_ASSEMBLY, |
| 208 | HAL_PARAM_VENC_H264_VUI_BITSTREAM_RESTRC, |
| 209 | HAL_PARAM_VENC_PRESERVE_TEXT_QUALITY, |
| 210 | HAL_PARAM_VDEC_CONCEAL_COLOR, |
| 211 | HAL_PARAM_VDEC_SCS_THRESHOLD, |
| 212 | HAL_PARAM_GET_BUFFER_REQUIREMENTS, |
| 213 | HAL_PARAM_MVC_BUFFER_LAYOUT, |
| 214 | HAL_PARAM_VENC_LTRMODE, |
| 215 | HAL_CONFIG_VENC_MARKLTRFRAME, |
| 216 | HAL_CONFIG_VENC_USELTRFRAME, |
| 217 | HAL_CONFIG_VENC_LTRPERIOD, |
| 218 | HAL_CONFIG_VENC_HIER_P_NUM_FRAMES, |
| 219 | HAL_PARAM_VENC_HIER_P_MAX_ENH_LAYERS, |
| 220 | HAL_PARAM_VENC_DISABLE_RC_TIMESTAMP, |
| 221 | HAL_PARAM_VENC_ENABLE_INITIAL_QP, |
| 222 | HAL_PARAM_VENC_SEARCH_RANGE, |
| 223 | HAL_PARAM_VPE_COLOR_SPACE_CONVERSION, |
| 224 | HAL_PARAM_VENC_VPX_ERROR_RESILIENCE_MODE, |
| 225 | HAL_PARAM_VENC_H264_NAL_SVC_EXT, |
| 226 | HAL_CONFIG_VENC_PERF_MODE, |
| 227 | HAL_PARAM_VENC_HIER_B_MAX_ENH_LAYERS, |
| 228 | HAL_PARAM_VDEC_NON_SECURE_OUTPUT2, |
| 229 | HAL_PARAM_VENC_HIER_P_HYBRID_MODE, |
| 230 | HAL_PARAM_VENC_MBI_STATISTICS_MODE, |
| 231 | HAL_PARAM_SYNC_BASED_INTERRUPT, |
| 232 | HAL_CONFIG_VENC_FRAME_QP, |
| 233 | HAL_CONFIG_VENC_BASELAYER_PRIORITYID, |
| 234 | HAL_PARAM_VENC_VQZIP_SEI, |
| 235 | HAL_PROPERTY_PARAM_VENC_ASPECT_RATIO, |
| 236 | HAL_CONFIG_VDEC_ENTROPY, |
| 237 | HAL_PARAM_VENC_BITRATE_TYPE, |
| 238 | HAL_PARAM_VENC_H264_PIC_ORDER_CNT, |
| 239 | HAL_PARAM_VENC_LOW_LATENCY, |
| 240 | HAL_PARAM_VENC_CONSTRAINED_INTRA_PRED, |
| 241 | HAL_CONFIG_VENC_BLUR_RESOLUTION, |
| 242 | HAL_PARAM_VENC_VIDEO_SIGNAL_INFO, |
| 243 | HAL_PARAM_VENC_SESSION_QP_RANGE_PACKED, |
| 244 | HAL_PARAM_VENC_H264_TRANSFORM_8x8, |
| 245 | HAL_PARAM_VENC_IFRAMESIZE_TYPE, |
| 246 | }; |
| 247 | |
| 248 | enum hal_domain { |
| 249 | HAL_VIDEO_DOMAIN_VPE, |
| 250 | HAL_VIDEO_DOMAIN_ENCODER, |
| 251 | HAL_VIDEO_DOMAIN_DECODER, |
| 252 | HAL_UNUSED_DOMAIN = 0x10000000, |
| 253 | }; |
| 254 | |
| 255 | enum multi_stream { |
| 256 | HAL_VIDEO_DECODER_NONE = 0x00000000, |
| 257 | HAL_VIDEO_DECODER_PRIMARY = 0x00000001, |
| 258 | HAL_VIDEO_DECODER_SECONDARY = 0x00000002, |
| 259 | HAL_VIDEO_DECODER_BOTH_OUTPUTS = 0x00000004, |
| 260 | HAL_VIDEO_UNUSED_OUTPUTS = 0x10000000, |
| 261 | }; |
| 262 | |
| 263 | enum hal_core_capabilities { |
| 264 | HAL_VIDEO_ENCODER_ROTATION_CAPABILITY = 0x00000001, |
| 265 | HAL_VIDEO_ENCODER_SCALING_CAPABILITY = 0x00000002, |
| 266 | HAL_VIDEO_ENCODER_DEINTERLACE_CAPABILITY = 0x00000004, |
| 267 | HAL_VIDEO_DECODER_MULTI_STREAM_CAPABILITY = 0x00000008, |
| 268 | HAL_VIDEO_UNUSED_CAPABILITY = 0x10000000, |
| 269 | }; |
| 270 | |
| 271 | enum hal_default_properties { |
| 272 | HAL_VIDEO_DYNAMIC_BUF_MODE = 0x00000001, |
| 273 | HAL_VIDEO_CONTINUE_DATA_TRANSFER = 0x00000002, |
| 274 | }; |
| 275 | |
| 276 | enum hal_video_codec { |
| 277 | HAL_VIDEO_CODEC_UNKNOWN = 0x00000000, |
| 278 | HAL_VIDEO_CODEC_MVC = 0x00000001, |
| 279 | HAL_VIDEO_CODEC_H264 = 0x00000002, |
| 280 | HAL_VIDEO_CODEC_H263 = 0x00000004, |
| 281 | HAL_VIDEO_CODEC_MPEG1 = 0x00000008, |
| 282 | HAL_VIDEO_CODEC_MPEG2 = 0x00000010, |
| 283 | HAL_VIDEO_CODEC_MPEG4 = 0x00000020, |
| 284 | HAL_VIDEO_CODEC_DIVX_311 = 0x00000040, |
| 285 | HAL_VIDEO_CODEC_DIVX = 0x00000080, |
| 286 | HAL_VIDEO_CODEC_VC1 = 0x00000100, |
| 287 | HAL_VIDEO_CODEC_SPARK = 0x00000200, |
| 288 | HAL_VIDEO_CODEC_VP6 = 0x00000400, |
| 289 | HAL_VIDEO_CODEC_VP7 = 0x00000800, |
| 290 | HAL_VIDEO_CODEC_VP8 = 0x00001000, |
| 291 | HAL_VIDEO_CODEC_HEVC = 0x00002000, |
| 292 | HAL_VIDEO_CODEC_VP9 = 0x00004000, |
| 293 | HAL_VIDEO_CODEC_HEVC_HYBRID = 0x80000000, |
| 294 | HAL_UNUSED_CODEC = 0x10000000, |
| 295 | }; |
| 296 | |
| 297 | enum hal_h263_profile { |
| 298 | HAL_H263_PROFILE_BASELINE = 0x00000001, |
| 299 | HAL_H263_PROFILE_H320CODING = 0x00000002, |
| 300 | HAL_H263_PROFILE_BACKWARDCOMPATIBLE = 0x00000004, |
| 301 | HAL_H263_PROFILE_ISWV2 = 0x00000008, |
| 302 | HAL_H263_PROFILE_ISWV3 = 0x00000010, |
| 303 | HAL_H263_PROFILE_HIGHCOMPRESSION = 0x00000020, |
| 304 | HAL_H263_PROFILE_INTERNET = 0x00000040, |
| 305 | HAL_H263_PROFILE_INTERLACE = 0x00000080, |
| 306 | HAL_H263_PROFILE_HIGHLATENCY = 0x00000100, |
| 307 | HAL_UNUSED_H263_PROFILE = 0x10000000, |
| 308 | }; |
| 309 | |
| 310 | enum hal_h263_level { |
| 311 | HAL_H263_LEVEL_10 = 0x00000001, |
| 312 | HAL_H263_LEVEL_20 = 0x00000002, |
| 313 | HAL_H263_LEVEL_30 = 0x00000004, |
| 314 | HAL_H263_LEVEL_40 = 0x00000008, |
| 315 | HAL_H263_LEVEL_45 = 0x00000010, |
| 316 | HAL_H263_LEVEL_50 = 0x00000020, |
| 317 | HAL_H263_LEVEL_60 = 0x00000040, |
| 318 | HAL_H263_LEVEL_70 = 0x00000080, |
| 319 | HAL_UNUSED_H263_LEVEL = 0x10000000, |
| 320 | }; |
| 321 | |
| 322 | enum hal_mpeg2_profile { |
| 323 | HAL_MPEG2_PROFILE_SIMPLE = 0x00000001, |
| 324 | HAL_MPEG2_PROFILE_MAIN = 0x00000002, |
| 325 | HAL_MPEG2_PROFILE_422 = 0x00000004, |
| 326 | HAL_MPEG2_PROFILE_SNR = 0x00000008, |
| 327 | HAL_MPEG2_PROFILE_SPATIAL = 0x00000010, |
| 328 | HAL_MPEG2_PROFILE_HIGH = 0x00000020, |
| 329 | HAL_UNUSED_MPEG2_PROFILE = 0x10000000, |
| 330 | }; |
| 331 | |
| 332 | enum hal_mpeg2_level { |
| 333 | HAL_MPEG2_LEVEL_LL = 0x00000001, |
| 334 | HAL_MPEG2_LEVEL_ML = 0x00000002, |
| 335 | HAL_MPEG2_LEVEL_H14 = 0x00000004, |
| 336 | HAL_MPEG2_LEVEL_HL = 0x00000008, |
| 337 | HAL_UNUSED_MEPG2_LEVEL = 0x10000000, |
| 338 | }; |
| 339 | |
| 340 | enum hal_mpeg4_profile { |
| 341 | HAL_MPEG4_PROFILE_SIMPLE = 0x00000001, |
| 342 | HAL_MPEG4_PROFILE_ADVANCEDSIMPLE = 0x00000002, |
| 343 | HAL_MPEG4_PROFILE_CORE = 0x00000004, |
| 344 | HAL_MPEG4_PROFILE_MAIN = 0x00000008, |
| 345 | HAL_MPEG4_PROFILE_NBIT = 0x00000010, |
| 346 | HAL_MPEG4_PROFILE_SCALABLETEXTURE = 0x00000020, |
| 347 | HAL_MPEG4_PROFILE_SIMPLEFACE = 0x00000040, |
| 348 | HAL_MPEG4_PROFILE_SIMPLEFBA = 0x00000080, |
| 349 | HAL_MPEG4_PROFILE_BASICANIMATED = 0x00000100, |
| 350 | HAL_MPEG4_PROFILE_HYBRID = 0x00000200, |
| 351 | HAL_MPEG4_PROFILE_ADVANCEDREALTIME = 0x00000400, |
| 352 | HAL_MPEG4_PROFILE_CORESCALABLE = 0x00000800, |
| 353 | HAL_MPEG4_PROFILE_ADVANCEDCODING = 0x00001000, |
| 354 | HAL_MPEG4_PROFILE_ADVANCEDCORE = 0x00002000, |
| 355 | HAL_MPEG4_PROFILE_ADVANCEDSCALABLE = 0x00004000, |
| 356 | HAL_MPEG4_PROFILE_SIMPLESCALABLE = 0x00008000, |
| 357 | HAL_UNUSED_MPEG4_PROFILE = 0x10000000, |
| 358 | }; |
| 359 | |
| 360 | enum hal_mpeg4_level { |
| 361 | HAL_MPEG4_LEVEL_0 = 0x00000001, |
| 362 | HAL_MPEG4_LEVEL_0b = 0x00000002, |
| 363 | HAL_MPEG4_LEVEL_1 = 0x00000004, |
| 364 | HAL_MPEG4_LEVEL_2 = 0x00000008, |
| 365 | HAL_MPEG4_LEVEL_3 = 0x00000010, |
| 366 | HAL_MPEG4_LEVEL_4 = 0x00000020, |
| 367 | HAL_MPEG4_LEVEL_4a = 0x00000040, |
| 368 | HAL_MPEG4_LEVEL_5 = 0x00000080, |
| 369 | HAL_MPEG4_LEVEL_VENDOR_START_UNUSED = 0x7F000000, |
| 370 | HAL_MPEG4_LEVEL_6 = 0x7F000001, |
| 371 | HAL_MPEG4_LEVEL_7 = 0x7F000002, |
| 372 | HAL_MPEG4_LEVEL_8 = 0x7F000003, |
| 373 | HAL_MPEG4_LEVEL_9 = 0x7F000004, |
| 374 | HAL_MPEG4_LEVEL_3b = 0x7F000005, |
| 375 | HAL_UNUSED_MPEG4_LEVEL = 0x10000000, |
| 376 | }; |
| 377 | |
| 378 | enum hal_h264_profile { |
| 379 | HAL_H264_PROFILE_BASELINE = 0x00000001, |
| 380 | HAL_H264_PROFILE_MAIN = 0x00000002, |
| 381 | HAL_H264_PROFILE_HIGH = 0x00000004, |
| 382 | HAL_H264_PROFILE_EXTENDED = 0x00000008, |
| 383 | HAL_H264_PROFILE_HIGH10 = 0x00000010, |
| 384 | HAL_H264_PROFILE_HIGH422 = 0x00000020, |
| 385 | HAL_H264_PROFILE_HIGH444 = 0x00000040, |
| 386 | HAL_H264_PROFILE_CONSTRAINED_BASE = 0x00000080, |
| 387 | HAL_H264_PROFILE_CONSTRAINED_HIGH = 0x00000100, |
| 388 | HAL_UNUSED_H264_PROFILE = 0x10000000, |
| 389 | }; |
| 390 | |
| 391 | enum hal_h264_level { |
| 392 | HAL_H264_LEVEL_1 = 0x00000001, |
| 393 | HAL_H264_LEVEL_1b = 0x00000002, |
| 394 | HAL_H264_LEVEL_11 = 0x00000004, |
| 395 | HAL_H264_LEVEL_12 = 0x00000008, |
| 396 | HAL_H264_LEVEL_13 = 0x00000010, |
| 397 | HAL_H264_LEVEL_2 = 0x00000020, |
| 398 | HAL_H264_LEVEL_21 = 0x00000040, |
| 399 | HAL_H264_LEVEL_22 = 0x00000080, |
| 400 | HAL_H264_LEVEL_3 = 0x00000100, |
| 401 | HAL_H264_LEVEL_31 = 0x00000200, |
| 402 | HAL_H264_LEVEL_32 = 0x00000400, |
| 403 | HAL_H264_LEVEL_4 = 0x00000800, |
| 404 | HAL_H264_LEVEL_41 = 0x00001000, |
| 405 | HAL_H264_LEVEL_42 = 0x00002000, |
| 406 | HAL_H264_LEVEL_5 = 0x00004000, |
| 407 | HAL_H264_LEVEL_51 = 0x00008000, |
| 408 | HAL_H264_LEVEL_52 = 0x00010000, |
| 409 | HAL_UNUSED_H264_LEVEL = 0x10000000, |
| 410 | }; |
| 411 | |
| 412 | enum hal_hevc_profile { |
| 413 | HAL_HEVC_PROFILE_MAIN = 0x00000001, |
| 414 | HAL_HEVC_PROFILE_MAIN10 = 0x00000002, |
| 415 | HAL_HEVC_PROFILE_MAIN_STILL_PIC = 0x00000004, |
| 416 | HAL_UNUSED_HEVC_PROFILE = 0x10000000, |
| 417 | }; |
| 418 | |
| 419 | enum hal_hevc_level { |
| 420 | HAL_HEVC_MAIN_TIER_LEVEL_1 = 0x10000001, |
| 421 | HAL_HEVC_MAIN_TIER_LEVEL_2 = 0x10000002, |
| 422 | HAL_HEVC_MAIN_TIER_LEVEL_2_1 = 0x10000004, |
| 423 | HAL_HEVC_MAIN_TIER_LEVEL_3 = 0x10000008, |
| 424 | HAL_HEVC_MAIN_TIER_LEVEL_3_1 = 0x10000010, |
| 425 | HAL_HEVC_MAIN_TIER_LEVEL_4 = 0x10000020, |
| 426 | HAL_HEVC_MAIN_TIER_LEVEL_4_1 = 0x10000040, |
| 427 | HAL_HEVC_MAIN_TIER_LEVEL_5 = 0x10000080, |
| 428 | HAL_HEVC_MAIN_TIER_LEVEL_5_1 = 0x10000100, |
| 429 | HAL_HEVC_MAIN_TIER_LEVEL_5_2 = 0x10000200, |
| 430 | HAL_HEVC_MAIN_TIER_LEVEL_6 = 0x10000400, |
| 431 | HAL_HEVC_MAIN_TIER_LEVEL_6_1 = 0x10000800, |
| 432 | HAL_HEVC_MAIN_TIER_LEVEL_6_2 = 0x10001000, |
| 433 | HAL_HEVC_HIGH_TIER_LEVEL_1 = 0x20000001, |
| 434 | HAL_HEVC_HIGH_TIER_LEVEL_2 = 0x20000002, |
| 435 | HAL_HEVC_HIGH_TIER_LEVEL_2_1 = 0x20000004, |
| 436 | HAL_HEVC_HIGH_TIER_LEVEL_3 = 0x20000008, |
| 437 | HAL_HEVC_HIGH_TIER_LEVEL_3_1 = 0x20000010, |
| 438 | HAL_HEVC_HIGH_TIER_LEVEL_4 = 0x20000020, |
| 439 | HAL_HEVC_HIGH_TIER_LEVEL_4_1 = 0x20000040, |
| 440 | HAL_HEVC_HIGH_TIER_LEVEL_5 = 0x20000080, |
| 441 | HAL_HEVC_HIGH_TIER_LEVEL_5_1 = 0x20000100, |
| 442 | HAL_HEVC_HIGH_TIER_LEVEL_5_2 = 0x20000200, |
| 443 | HAL_HEVC_HIGH_TIER_LEVEL_6 = 0x20000400, |
| 444 | HAL_HEVC_HIGH_TIER_LEVEL_6_1 = 0x20000800, |
| 445 | HAL_HEVC_HIGH_TIER_LEVEL_6_2 = 0x20001000, |
| 446 | HAL_UNUSED_HEVC_TIER_LEVEL = 0x80000000, |
| 447 | }; |
| 448 | |
| 449 | enum hal_hevc_tier { |
| 450 | HAL_HEVC_TIER_MAIN = 0x00000001, |
| 451 | HAL_HEVC_TIER_HIGH = 0x00000002, |
| 452 | HAL_UNUSED_HEVC_TIER = 0x10000000, |
| 453 | }; |
| 454 | |
| 455 | enum hal_vpx_profile { |
| 456 | HAL_VPX_PROFILE_SIMPLE = 0x00000001, |
| 457 | HAL_VPX_PROFILE_ADVANCED = 0x00000002, |
| 458 | HAL_VPX_PROFILE_VERSION_0 = 0x00000004, |
| 459 | HAL_VPX_PROFILE_VERSION_1 = 0x00000008, |
| 460 | HAL_VPX_PROFILE_VERSION_2 = 0x00000010, |
| 461 | HAL_VPX_PROFILE_VERSION_3 = 0x00000020, |
| 462 | HAL_VPX_PROFILE_UNUSED = 0x10000000, |
| 463 | }; |
| 464 | |
| 465 | enum hal_vc1_profile { |
| 466 | HAL_VC1_PROFILE_SIMPLE = 0x00000001, |
| 467 | HAL_VC1_PROFILE_MAIN = 0x00000002, |
| 468 | HAL_VC1_PROFILE_ADVANCED = 0x00000004, |
| 469 | HAL_UNUSED_VC1_PROFILE = 0x10000000, |
| 470 | }; |
| 471 | |
| 472 | enum hal_vc1_level { |
| 473 | HAL_VC1_LEVEL_LOW = 0x00000001, |
| 474 | HAL_VC1_LEVEL_MEDIUM = 0x00000002, |
| 475 | HAL_VC1_LEVEL_HIGH = 0x00000004, |
| 476 | HAL_VC1_LEVEL_0 = 0x00000008, |
| 477 | HAL_VC1_LEVEL_1 = 0x00000010, |
| 478 | HAL_VC1_LEVEL_2 = 0x00000020, |
| 479 | HAL_VC1_LEVEL_3 = 0x00000040, |
| 480 | HAL_VC1_LEVEL_4 = 0x00000080, |
| 481 | HAL_UNUSED_VC1_LEVEL = 0x10000000, |
| 482 | }; |
| 483 | |
| 484 | enum hal_divx_format { |
| 485 | HAL_DIVX_FORMAT_4, |
| 486 | HAL_DIVX_FORMAT_5, |
| 487 | HAL_DIVX_FORMAT_6, |
| 488 | HAL_UNUSED_DIVX_FORMAT = 0x10000000, |
| 489 | }; |
| 490 | |
| 491 | enum hal_divx_profile { |
| 492 | HAL_DIVX_PROFILE_QMOBILE = 0x00000001, |
| 493 | HAL_DIVX_PROFILE_MOBILE = 0x00000002, |
| 494 | HAL_DIVX_PROFILE_MT = 0x00000004, |
| 495 | HAL_DIVX_PROFILE_HT = 0x00000008, |
| 496 | HAL_DIVX_PROFILE_HD = 0x00000010, |
| 497 | HAL_UNUSED_DIVX_PROFILE = 0x10000000, |
| 498 | }; |
| 499 | |
| 500 | enum hal_mvc_profile { |
| 501 | HAL_MVC_PROFILE_STEREO_HIGH = 0x00001000, |
| 502 | HAL_UNUSED_MVC_PROFILE = 0x10000000, |
| 503 | }; |
| 504 | |
| 505 | enum hal_mvc_level { |
| 506 | HAL_MVC_LEVEL_1 = 0x00000001, |
| 507 | HAL_MVC_LEVEL_1b = 0x00000002, |
| 508 | HAL_MVC_LEVEL_11 = 0x00000004, |
| 509 | HAL_MVC_LEVEL_12 = 0x00000008, |
| 510 | HAL_MVC_LEVEL_13 = 0x00000010, |
| 511 | HAL_MVC_LEVEL_2 = 0x00000020, |
| 512 | HAL_MVC_LEVEL_21 = 0x00000040, |
| 513 | HAL_MVC_LEVEL_22 = 0x00000080, |
| 514 | HAL_MVC_LEVEL_3 = 0x00000100, |
| 515 | HAL_MVC_LEVEL_31 = 0x00000200, |
| 516 | HAL_MVC_LEVEL_32 = 0x00000400, |
| 517 | HAL_MVC_LEVEL_4 = 0x00000800, |
| 518 | HAL_MVC_LEVEL_41 = 0x00001000, |
| 519 | HAL_MVC_LEVEL_42 = 0x00002000, |
| 520 | HAL_MVC_LEVEL_5 = 0x00004000, |
| 521 | HAL_MVC_LEVEL_51 = 0x00008000, |
| 522 | HAL_UNUSED_MVC_LEVEL = 0x10000000, |
| 523 | }; |
| 524 | |
| 525 | struct hal_frame_rate { |
| 526 | enum hal_buffer buffer_type; |
| 527 | u32 frame_rate; |
| 528 | }; |
| 529 | |
| 530 | enum hal_uncompressed_format { |
| 531 | HAL_COLOR_FORMAT_MONOCHROME = 0x00000001, |
| 532 | HAL_COLOR_FORMAT_NV12 = 0x00000002, |
| 533 | HAL_COLOR_FORMAT_NV21 = 0x00000004, |
| 534 | HAL_COLOR_FORMAT_NV12_4x4TILE = 0x00000008, |
| 535 | HAL_COLOR_FORMAT_NV21_4x4TILE = 0x00000010, |
| 536 | HAL_COLOR_FORMAT_YUYV = 0x00000020, |
| 537 | HAL_COLOR_FORMAT_YVYU = 0x00000040, |
| 538 | HAL_COLOR_FORMAT_UYVY = 0x00000080, |
| 539 | HAL_COLOR_FORMAT_VYUY = 0x00000100, |
| 540 | HAL_COLOR_FORMAT_RGB565 = 0x00000200, |
| 541 | HAL_COLOR_FORMAT_BGR565 = 0x00000400, |
| 542 | HAL_COLOR_FORMAT_RGB888 = 0x00000800, |
| 543 | HAL_COLOR_FORMAT_BGR888 = 0x00001000, |
| 544 | HAL_COLOR_FORMAT_NV12_UBWC = 0x00002000, |
| 545 | HAL_COLOR_FORMAT_NV12_TP10_UBWC = 0x00004000, |
| 546 | HAL_COLOR_FORMAT_RGBA8888 = 0x00008000, |
| 547 | HAL_COLOR_FORMAT_RGBA8888_UBWC = 0x00010000, |
| 548 | HAL_UNUSED_COLOR = 0x10000000, |
| 549 | }; |
| 550 | |
| 551 | enum hal_statistics_mode_type { |
| 552 | HAL_STATISTICS_MODE_DEFAULT = 0x00000001, |
| 553 | HAL_STATISTICS_MODE_1 = 0x00000002, |
| 554 | HAL_STATISTICS_MODE_2 = 0x00000004, |
| 555 | HAL_STATISTICS_MODE_3 = 0x00000008, |
| 556 | }; |
| 557 | |
| 558 | enum hal_ssr_trigger_type { |
| 559 | SSR_ERR_FATAL = 1, |
| 560 | SSR_SW_DIV_BY_ZERO, |
| 561 | SSR_HW_WDOG_IRQ, |
| 562 | }; |
| 563 | |
| 564 | struct hal_uncompressed_format_select { |
| 565 | enum hal_buffer buffer_type; |
| 566 | enum hal_uncompressed_format format; |
| 567 | }; |
| 568 | |
| 569 | struct hal_uncompressed_plane_actual { |
| 570 | int actual_stride; |
| 571 | u32 actual_plane_buffer_height; |
| 572 | }; |
| 573 | |
| 574 | struct hal_uncompressed_plane_actual_info { |
| 575 | enum hal_buffer buffer_type; |
| 576 | u32 num_planes; |
| 577 | struct hal_uncompressed_plane_actual rg_plane_format[1]; |
| 578 | }; |
| 579 | |
| 580 | struct hal_uncompressed_plane_constraints { |
| 581 | u32 stride_multiples; |
| 582 | u32 max_stride; |
| 583 | u32 min_plane_buffer_height_multiple; |
| 584 | u32 buffer_alignment; |
| 585 | }; |
| 586 | |
| 587 | struct hal_uncompressed_plane_actual_constraints_info { |
| 588 | enum hal_buffer buffer_type; |
| 589 | u32 num_planes; |
| 590 | struct hal_uncompressed_plane_constraints rg_plane_format[1]; |
| 591 | }; |
| 592 | |
| 593 | struct hal_extra_data_header_config { |
| 594 | u32 type; |
| 595 | enum hal_buffer buffer_type; |
| 596 | u32 version; |
| 597 | u32 port_index; |
| 598 | u32 client_extradata_id; |
| 599 | }; |
| 600 | |
| 601 | struct hal_frame_size { |
| 602 | enum hal_buffer buffer_type; |
| 603 | u32 width; |
| 604 | u32 height; |
| 605 | }; |
| 606 | |
| 607 | struct hal_enable { |
| 608 | bool enable; |
| 609 | }; |
| 610 | |
| 611 | struct hal_buffer_count_actual { |
| 612 | enum hal_buffer buffer_type; |
| 613 | u32 buffer_count_actual; |
| 614 | }; |
| 615 | |
| 616 | struct hal_buffer_size_minimum { |
| 617 | enum hal_buffer buffer_type; |
| 618 | u32 buffer_size; |
| 619 | }; |
| 620 | |
| 621 | struct hal_buffer_display_hold_count_actual { |
| 622 | enum hal_buffer buffer_type; |
| 623 | u32 hold_count; |
| 624 | }; |
| 625 | |
| 626 | enum hal_nal_stream_format { |
| 627 | HAL_NAL_FORMAT_STARTCODES = 0x00000001, |
| 628 | HAL_NAL_FORMAT_ONE_NAL_PER_BUFFER = 0x00000002, |
| 629 | HAL_NAL_FORMAT_ONE_BYTE_LENGTH = 0x00000004, |
| 630 | HAL_NAL_FORMAT_TWO_BYTE_LENGTH = 0x00000008, |
| 631 | HAL_NAL_FORMAT_FOUR_BYTE_LENGTH = 0x00000010, |
| 632 | }; |
| 633 | |
| 634 | enum hal_output_order { |
| 635 | HAL_OUTPUT_ORDER_DISPLAY, |
| 636 | HAL_OUTPUT_ORDER_DECODE, |
| 637 | HAL_UNUSED_OUTPUT = 0x10000000, |
| 638 | }; |
| 639 | |
| 640 | enum hal_picture { |
| 641 | HAL_PICTURE_I = 0x01, |
| 642 | HAL_PICTURE_P = 0x02, |
| 643 | HAL_PICTURE_B = 0x04, |
| 644 | HAL_PICTURE_IDR = 0x08, |
| 645 | HAL_PICTURE_CRA = 0x10, |
| 646 | HAL_FRAME_NOTCODED = 0x7F002000, |
| 647 | HAL_FRAME_YUV = 0x7F004000, |
| 648 | HAL_UNUSED_PICT = 0x10000000, |
| 649 | }; |
| 650 | |
| 651 | struct hal_extradata_enable { |
| 652 | u32 enable; |
| 653 | enum hal_extradata_id index; |
| 654 | }; |
| 655 | |
| 656 | struct hal_enable_picture { |
| 657 | u32 picture_type; |
| 658 | }; |
| 659 | |
| 660 | struct hal_multi_stream { |
| 661 | enum hal_buffer buffer_type; |
| 662 | u32 enable; |
| 663 | u32 width; |
| 664 | u32 height; |
| 665 | }; |
| 666 | |
| 667 | struct hal_display_picture_buffer_count { |
| 668 | u32 enable; |
| 669 | u32 count; |
| 670 | }; |
| 671 | |
| 672 | struct hal_mb_error_map { |
| 673 | u32 error_map_size; |
| 674 | u8 rg_error_map[1]; |
| 675 | }; |
| 676 | |
| 677 | struct hal_request_iframe { |
| 678 | u32 enable; |
| 679 | }; |
| 680 | |
| 681 | struct hal_bitrate { |
| 682 | u32 bit_rate; |
| 683 | u32 layer_id; |
| 684 | }; |
| 685 | |
| 686 | struct hal_profile_level { |
| 687 | u32 profile; |
| 688 | u32 level; |
| 689 | }; |
| 690 | |
| 691 | struct hal_profile_level_supported { |
| 692 | u32 profile_count; |
| 693 | struct hal_profile_level profile_level[MAX_PROFILE_COUNT]; |
| 694 | }; |
| 695 | |
| 696 | enum hal_h264_entropy { |
| 697 | HAL_H264_ENTROPY_CAVLC = 1, |
| 698 | HAL_H264_ENTROPY_CABAC = 2, |
| 699 | HAL_UNUSED_ENTROPY = 0x10000000, |
| 700 | }; |
| 701 | |
| 702 | enum hal_h264_cabac_model { |
| 703 | HAL_H264_CABAC_MODEL_0 = 1, |
| 704 | HAL_H264_CABAC_MODEL_1 = 2, |
| 705 | HAL_H264_CABAC_MODEL_2 = 4, |
| 706 | HAL_UNUSED_CABAC = 0x10000000, |
| 707 | }; |
| 708 | |
| 709 | struct hal_h264_entropy_control { |
| 710 | enum hal_h264_entropy entropy_mode; |
| 711 | enum hal_h264_cabac_model cabac_model; |
| 712 | }; |
| 713 | |
| 714 | enum hal_rate_control { |
| 715 | HAL_RATE_CONTROL_OFF, |
| 716 | HAL_RATE_CONTROL_VBR_VFR, |
| 717 | HAL_RATE_CONTROL_VBR_CFR, |
| 718 | HAL_RATE_CONTROL_CBR_VFR, |
| 719 | HAL_RATE_CONTROL_CBR_CFR, |
| 720 | HAL_RATE_CONTROL_MBR_CFR, |
| 721 | HAL_RATE_CONTROL_MBR_VFR, |
| 722 | HAL_UNUSED_RC = 0x10000000, |
| 723 | }; |
| 724 | |
| 725 | struct hal_mpeg4_time_resolution { |
| 726 | u32 time_increment_resolution; |
| 727 | }; |
| 728 | |
| 729 | struct hal_mpeg4_header_extension { |
| 730 | u32 header_extension; |
| 731 | }; |
| 732 | |
| 733 | enum hal_h264_db_mode { |
| 734 | HAL_H264_DB_MODE_DISABLE, |
| 735 | HAL_H264_DB_MODE_SKIP_SLICE_BOUNDARY, |
| 736 | HAL_H264_DB_MODE_ALL_BOUNDARY, |
| 737 | HAL_UNUSED_H264_DB = 0x10000000, |
| 738 | }; |
| 739 | |
| 740 | struct hal_h264_db_control { |
| 741 | enum hal_h264_db_mode mode; |
| 742 | int slice_alpha_offset; |
| 743 | int slice_beta_offset; |
| 744 | }; |
| 745 | |
| 746 | struct hal_temporal_spatial_tradeoff { |
| 747 | u32 ts_factor; |
| 748 | }; |
| 749 | |
| 750 | struct hal_quantization { |
| 751 | u32 qpi; |
| 752 | u32 qpp; |
| 753 | u32 qpb; |
| 754 | u32 layer_id; |
| 755 | }; |
| 756 | |
| 757 | struct hal_initial_quantization { |
| 758 | u32 qpi; |
| 759 | u32 qpp; |
| 760 | u32 qpb; |
| 761 | u32 init_qp_enable; |
| 762 | }; |
| 763 | |
| 764 | struct hal_quantization_range { |
| 765 | u32 min_qp; |
| 766 | u32 max_qp; |
| 767 | u32 layer_id; |
| 768 | }; |
| 769 | |
| 770 | struct hal_intra_period { |
| 771 | u32 pframes; |
| 772 | u32 bframes; |
| 773 | }; |
| 774 | |
| 775 | struct hal_idr_period { |
| 776 | u32 idr_period; |
| 777 | }; |
| 778 | |
| 779 | enum hal_rotate { |
| 780 | HAL_ROTATE_NONE, |
| 781 | HAL_ROTATE_90, |
| 782 | HAL_ROTATE_180, |
| 783 | HAL_ROTATE_270, |
| 784 | HAL_UNUSED_ROTATE = 0x10000000, |
| 785 | }; |
| 786 | |
| 787 | enum hal_flip { |
| 788 | HAL_FLIP_NONE, |
| 789 | HAL_FLIP_HORIZONTAL, |
| 790 | HAL_FLIP_VERTICAL, |
| 791 | HAL_UNUSED_FLIP = 0x10000000, |
| 792 | }; |
| 793 | |
| 794 | struct hal_operations { |
| 795 | enum hal_rotate rotate; |
| 796 | enum hal_flip flip; |
| 797 | }; |
| 798 | |
| 799 | enum hal_intra_refresh_mode { |
| 800 | HAL_INTRA_REFRESH_NONE, |
| 801 | HAL_INTRA_REFRESH_CYCLIC, |
| 802 | HAL_INTRA_REFRESH_ADAPTIVE, |
| 803 | HAL_INTRA_REFRESH_CYCLIC_ADAPTIVE, |
| 804 | HAL_INTRA_REFRESH_RANDOM, |
| 805 | HAL_UNUSED_INTRA = 0x10000000, |
| 806 | }; |
| 807 | |
| 808 | struct hal_intra_refresh { |
| 809 | enum hal_intra_refresh_mode mode; |
| 810 | u32 air_mbs; |
| 811 | u32 air_ref; |
| 812 | u32 cir_mbs; |
| 813 | }; |
| 814 | |
| 815 | enum hal_multi_slice { |
| 816 | HAL_MULTI_SLICE_OFF, |
| 817 | HAL_MULTI_SLICE_BY_MB_COUNT, |
| 818 | HAL_MULTI_SLICE_BY_BYTE_COUNT, |
| 819 | HAL_MULTI_SLICE_GOB, |
| 820 | HAL_UNUSED_SLICE = 0x10000000, |
| 821 | }; |
| 822 | |
| 823 | struct hal_multi_slice_control { |
| 824 | enum hal_multi_slice multi_slice; |
| 825 | u32 slice_size; |
| 826 | }; |
| 827 | |
| 828 | struct hal_debug_config { |
| 829 | u32 debug_config; |
| 830 | }; |
| 831 | |
| 832 | struct hal_buffer_requirements { |
| 833 | enum hal_buffer buffer_type; |
| 834 | u32 buffer_size; |
| 835 | u32 buffer_region_size; |
| 836 | u32 buffer_hold_count; |
| 837 | u32 buffer_count_min; |
| 838 | u32 buffer_count_actual; |
| 839 | u32 contiguous; |
| 840 | u32 buffer_alignment; |
| 841 | }; |
| 842 | |
| 843 | enum hal_priority {/* Priority increases with number */ |
| 844 | HAL_PRIORITY_LOW = 10, |
| 845 | HAL_PRIOIRTY_MEDIUM = 20, |
| 846 | HAL_PRIORITY_HIGH = 30, |
| 847 | HAL_UNUSED_PRIORITY = 0x10000000, |
| 848 | }; |
| 849 | |
| 850 | struct hal_batch_info { |
| 851 | u32 input_batch_count; |
| 852 | u32 output_batch_count; |
| 853 | }; |
| 854 | |
| 855 | struct hal_metadata_pass_through { |
| 856 | u32 enable; |
| 857 | u32 size; |
| 858 | }; |
| 859 | |
| 860 | struct hal_uncompressed_format_supported { |
| 861 | enum hal_buffer buffer_type; |
| 862 | u32 format_entries; |
| 863 | u32 rg_format_info[1]; |
| 864 | }; |
| 865 | |
| 866 | enum hal_interlace_format { |
| 867 | HAL_INTERLACE_FRAME_PROGRESSIVE = 0x01, |
| 868 | HAL_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02, |
| 869 | HAL_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04, |
| 870 | HAL_INTERLACE_FRAME_TOPFIELDFIRST = 0x08, |
| 871 | HAL_INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10, |
| 872 | HAL_UNUSED_INTERLACE = 0x10000000, |
| 873 | }; |
| 874 | |
| 875 | struct hal_interlace_format_supported { |
| 876 | enum hal_buffer buffer_type; |
| 877 | enum hal_interlace_format format; |
| 878 | }; |
| 879 | |
| 880 | enum hal_chroma_site { |
| 881 | HAL_CHROMA_SITE_0, |
| 882 | HAL_CHROMA_SITE_1, |
| 883 | HAL_UNUSED_CHROMA = 0x10000000, |
| 884 | }; |
| 885 | |
| 886 | struct hal_properties_supported { |
| 887 | u32 num_properties; |
| 888 | u32 rg_properties[1]; |
| 889 | }; |
| 890 | |
| 891 | enum hal_capability { |
| 892 | HAL_CAPABILITY_FRAME_WIDTH = 0x1, |
| 893 | HAL_CAPABILITY_FRAME_HEIGHT, |
| 894 | HAL_CAPABILITY_MBS_PER_FRAME, |
| 895 | HAL_CAPABILITY_MBS_PER_SECOND, |
| 896 | HAL_CAPABILITY_FRAMERATE, |
| 897 | HAL_CAPABILITY_SCALE_X, |
| 898 | HAL_CAPABILITY_SCALE_Y, |
| 899 | HAL_CAPABILITY_BITRATE, |
| 900 | HAL_CAPABILITY_BFRAME, |
| 901 | HAL_CAPABILITY_PEAKBITRATE, |
| 902 | HAL_CAPABILITY_HIER_P_NUM_ENH_LAYERS, |
| 903 | HAL_CAPABILITY_ENC_LTR_COUNT, |
| 904 | HAL_CAPABILITY_SECURE_OUTPUT2_THRESHOLD, |
| 905 | HAL_CAPABILITY_HIER_B_NUM_ENH_LAYERS, |
| 906 | HAL_CAPABILITY_LCU_SIZE, |
| 907 | HAL_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS, |
| 908 | HAL_CAPABILITY_MBS_PER_SECOND_POWER_SAVE, |
| 909 | HAL_UNUSED_CAPABILITY = 0x10000000, |
| 910 | }; |
| 911 | |
| 912 | struct hal_capability_supported { |
| 913 | enum hal_capability capability_type; |
| 914 | u32 min; |
| 915 | u32 max; |
| 916 | u32 step_size; |
| 917 | }; |
| 918 | |
| 919 | struct hal_capability_supported_info { |
| 920 | u32 num_capabilities; |
| 921 | struct hal_capability_supported rg_data[1]; |
| 922 | }; |
| 923 | |
| 924 | struct hal_nal_stream_format_supported { |
| 925 | u32 nal_stream_format_supported; |
| 926 | }; |
| 927 | |
| 928 | struct hal_nal_stream_format_select { |
| 929 | u32 nal_stream_format_select; |
| 930 | }; |
| 931 | |
| 932 | struct hal_multi_view_format { |
| 933 | u32 views; |
| 934 | u32 rg_view_order[1]; |
| 935 | }; |
| 936 | |
| 937 | enum hal_buffer_layout_type { |
| 938 | HAL_BUFFER_LAYOUT_TOP_BOTTOM, |
| 939 | HAL_BUFFER_LAYOUT_SEQ, |
| 940 | HAL_UNUSED_BUFFER_LAYOUT = 0x10000000, |
| 941 | }; |
| 942 | |
| 943 | struct hal_mvc_buffer_layout { |
| 944 | enum hal_buffer_layout_type layout_type; |
| 945 | u32 bright_view_first; |
| 946 | u32 ngap; |
| 947 | }; |
| 948 | |
| 949 | struct hal_seq_header_info { |
| 950 | u32 nax_header_len; |
| 951 | }; |
| 952 | |
| 953 | struct hal_aspect_ratio { |
| 954 | u32 aspect_width; |
| 955 | u32 aspect_height; |
| 956 | }; |
| 957 | |
| 958 | struct hal_codec_supported { |
| 959 | u32 decoder_codec_supported; |
| 960 | u32 encoder_codec_supported; |
| 961 | }; |
| 962 | |
| 963 | struct hal_multi_view_select { |
| 964 | u32 view_index; |
| 965 | }; |
| 966 | |
| 967 | struct hal_timestamp_scale { |
| 968 | u32 time_stamp_scale; |
| 969 | }; |
| 970 | |
| 971 | |
| 972 | struct hal_h264_vui_timing_info { |
| 973 | u32 enable; |
| 974 | u32 fixed_frame_rate; |
| 975 | u32 time_scale; |
| 976 | }; |
| 977 | |
| 978 | struct hal_h264_vui_bitstream_restrc { |
| 979 | u32 enable; |
| 980 | }; |
| 981 | |
| 982 | struct hal_preserve_text_quality { |
| 983 | u32 enable; |
| 984 | }; |
| 985 | |
| 986 | struct hal_vc1e_perf_cfg_type { |
| 987 | struct { |
| 988 | u32 x_subsampled; |
| 989 | u32 y_subsampled; |
| 990 | } i_frame, p_frame, b_frame; |
| 991 | }; |
| 992 | |
| 993 | struct hal_vpe_color_space_conversion { |
| 994 | u32 csc_matrix[HAL_MAX_MATRIX_COEFFS]; |
| 995 | u32 csc_bias[HAL_MAX_BIAS_COEFFS]; |
| 996 | u32 csc_limit[HAL_MAX_LIMIT_COEFFS]; |
| 997 | }; |
| 998 | |
| 999 | struct hal_video_signal_info { |
| 1000 | u32 color_space; |
| 1001 | u32 transfer_chars; |
| 1002 | u32 matrix_coeffs; |
| 1003 | bool full_range; |
| 1004 | }; |
| 1005 | |
| 1006 | enum hal_iframesize_type { |
| 1007 | HAL_IFRAMESIZE_TYPE_DEFAULT, |
| 1008 | HAL_IFRAMESIZE_TYPE_MEDIUM, |
| 1009 | HAL_IFRAMESIZE_TYPE_HUGE, |
| 1010 | HAL_IFRAMESIZE_TYPE_UNLIMITED, |
| 1011 | }; |
| 1012 | |
| 1013 | enum vidc_resource_id { |
| 1014 | VIDC_RESOURCE_NONE, |
| 1015 | VIDC_RESOURCE_OCMEM, |
| 1016 | VIDC_RESOURCE_VMEM, |
| 1017 | VIDC_UNUSED_RESOURCE = 0x10000000, |
| 1018 | }; |
| 1019 | |
| 1020 | struct vidc_resource_hdr { |
| 1021 | enum vidc_resource_id resource_id; |
| 1022 | void *resource_handle; |
| 1023 | u32 size; |
| 1024 | }; |
| 1025 | |
| 1026 | struct vidc_buffer_addr_info { |
| 1027 | enum hal_buffer buffer_type; |
| 1028 | u32 buffer_size; |
| 1029 | u32 num_buffers; |
| 1030 | ion_phys_addr_t align_device_addr; |
| 1031 | ion_phys_addr_t extradata_addr; |
| 1032 | u32 extradata_size; |
| 1033 | u32 response_required; |
| 1034 | }; |
| 1035 | |
| 1036 | /* Needs to be exactly the same as hfi_buffer_info */ |
| 1037 | struct hal_buffer_info { |
| 1038 | u32 buffer_addr; |
| 1039 | u32 extra_data_addr; |
| 1040 | }; |
| 1041 | |
| 1042 | struct vidc_frame_plane_config { |
| 1043 | u32 left; |
| 1044 | u32 top; |
| 1045 | u32 width; |
| 1046 | u32 height; |
| 1047 | u32 stride; |
| 1048 | u32 scan_lines; |
| 1049 | }; |
| 1050 | |
| 1051 | struct vidc_uncompressed_frame_config { |
| 1052 | struct vidc_frame_plane_config luma_plane; |
| 1053 | struct vidc_frame_plane_config chroma_plane; |
| 1054 | }; |
| 1055 | |
| 1056 | struct vidc_frame_data { |
| 1057 | enum hal_buffer buffer_type; |
| 1058 | ion_phys_addr_t device_addr; |
| 1059 | ion_phys_addr_t extradata_addr; |
| 1060 | int64_t timestamp; |
| 1061 | u32 flags; |
| 1062 | u32 offset; |
| 1063 | u32 alloc_len; |
| 1064 | u32 filled_len; |
| 1065 | u32 mark_target; |
| 1066 | u32 mark_data; |
| 1067 | u32 clnt_data; |
| 1068 | u32 extradata_size; |
| 1069 | }; |
| 1070 | |
| 1071 | struct vidc_seq_hdr { |
| 1072 | ion_phys_addr_t seq_hdr; |
| 1073 | u32 seq_hdr_len; |
| 1074 | }; |
| 1075 | |
| 1076 | struct hal_fw_info { |
| 1077 | char version[VENUS_VERSION_LENGTH]; |
| 1078 | phys_addr_t base_addr; |
| 1079 | int register_base; |
| 1080 | int register_size; |
| 1081 | int irq; |
| 1082 | }; |
| 1083 | |
| 1084 | enum hal_flush { |
| 1085 | HAL_FLUSH_INPUT, |
| 1086 | HAL_FLUSH_OUTPUT, |
| 1087 | HAL_FLUSH_ALL, |
| 1088 | HAL_UNUSED_FLUSH = 0x10000000, |
| 1089 | }; |
| 1090 | |
| 1091 | enum hal_event_type { |
| 1092 | HAL_EVENT_SEQ_CHANGED_SUFFICIENT_RESOURCES, |
| 1093 | HAL_EVENT_SEQ_CHANGED_INSUFFICIENT_RESOURCES, |
| 1094 | HAL_EVENT_RELEASE_BUFFER_REFERENCE, |
| 1095 | HAL_UNUSED_SEQCHG = 0x10000000, |
| 1096 | }; |
| 1097 | |
| 1098 | enum buffer_mode_type { |
| 1099 | HAL_BUFFER_MODE_STATIC = 0x001, |
| 1100 | HAL_BUFFER_MODE_RING = 0x010, |
| 1101 | HAL_BUFFER_MODE_DYNAMIC = 0x100, |
| 1102 | }; |
| 1103 | |
| 1104 | struct hal_buffer_alloc_mode { |
| 1105 | enum hal_buffer buffer_type; |
| 1106 | enum buffer_mode_type buffer_mode; |
| 1107 | }; |
| 1108 | |
| 1109 | enum ltr_mode { |
| 1110 | HAL_LTR_MODE_DISABLE, |
| 1111 | HAL_LTR_MODE_MANUAL, |
| 1112 | HAL_LTR_MODE_PERIODIC, |
| 1113 | }; |
| 1114 | |
| 1115 | struct hal_ltr_mode { |
| 1116 | enum ltr_mode mode; |
| 1117 | u32 count; |
| 1118 | u32 trust_mode; |
| 1119 | }; |
| 1120 | |
| 1121 | struct hal_ltr_use { |
| 1122 | u32 ref_ltr; |
| 1123 | u32 use_constraint; |
| 1124 | u32 frames; |
| 1125 | }; |
| 1126 | |
| 1127 | struct hal_ltr_mark { |
| 1128 | u32 mark_frame; |
| 1129 | }; |
| 1130 | |
| 1131 | enum hal_perf_mode { |
| 1132 | HAL_PERF_MODE_POWER_SAVE, |
| 1133 | HAL_PERF_MODE_POWER_MAX_QUALITY, |
| 1134 | }; |
| 1135 | |
| 1136 | struct hal_hybrid_hierp { |
| 1137 | u32 layers; |
| 1138 | }; |
| 1139 | |
| 1140 | struct hal_scs_threshold { |
| 1141 | u32 threshold_value; |
| 1142 | }; |
| 1143 | |
| 1144 | struct buffer_requirements { |
| 1145 | struct hal_buffer_requirements buffer[HAL_BUFFER_MAX]; |
| 1146 | }; |
| 1147 | |
| 1148 | union hal_get_property { |
| 1149 | struct hal_frame_rate frame_rate; |
| 1150 | struct hal_uncompressed_format_select format_select; |
| 1151 | struct hal_uncompressed_plane_actual plane_actual; |
| 1152 | struct hal_uncompressed_plane_actual_info plane_actual_info; |
| 1153 | struct hal_uncompressed_plane_constraints plane_constraints; |
| 1154 | struct hal_uncompressed_plane_actual_constraints_info |
| 1155 | plane_constraints_info; |
| 1156 | struct hal_extra_data_header_config extra_data_header_config; |
| 1157 | struct hal_frame_size frame_size; |
| 1158 | struct hal_enable enable; |
| 1159 | struct hal_buffer_count_actual buffer_count_actual; |
| 1160 | struct hal_extradata_enable extradata_enable; |
| 1161 | struct hal_enable_picture enable_picture; |
| 1162 | struct hal_multi_stream multi_stream; |
| 1163 | struct hal_display_picture_buffer_count display_picture_buffer_count; |
| 1164 | struct hal_mb_error_map mb_error_map; |
| 1165 | struct hal_request_iframe request_iframe; |
| 1166 | struct hal_bitrate bitrate; |
| 1167 | struct hal_profile_level profile_level; |
| 1168 | struct hal_profile_level_supported profile_level_supported; |
| 1169 | struct hal_mpeg4_time_resolution mpeg4_time_resolution; |
| 1170 | struct hal_mpeg4_header_extension mpeg4_header_extension; |
| 1171 | struct hal_h264_db_control h264_db_control; |
| 1172 | struct hal_temporal_spatial_tradeoff temporal_spatial_tradeoff; |
| 1173 | struct hal_quantization quantization; |
| 1174 | struct hal_quantization_range quantization_range; |
| 1175 | struct hal_intra_period intra_period; |
| 1176 | struct hal_idr_period idr_period; |
| 1177 | struct hal_operations operations; |
| 1178 | struct hal_intra_refresh intra_refresh; |
| 1179 | struct hal_multi_slice_control multi_slice_control; |
| 1180 | struct hal_debug_config debug_config; |
| 1181 | struct hal_batch_info batch_info; |
| 1182 | struct hal_metadata_pass_through metadata_pass_through; |
| 1183 | struct hal_uncompressed_format_supported uncompressed_format_supported; |
| 1184 | struct hal_interlace_format_supported interlace_format_supported; |
| 1185 | struct hal_properties_supported properties_supported; |
| 1186 | struct hal_capability_supported capability_supported; |
| 1187 | struct hal_capability_supported_info capability_supported_info; |
| 1188 | struct hal_nal_stream_format_supported nal_stream_format_supported; |
| 1189 | struct hal_nal_stream_format_select nal_stream_format_select; |
| 1190 | struct hal_multi_view_format multi_view_format; |
| 1191 | struct hal_seq_header_info seq_header_info; |
| 1192 | struct hal_codec_supported codec_supported; |
| 1193 | struct hal_multi_view_select multi_view_select; |
| 1194 | struct hal_timestamp_scale timestamp_scale; |
| 1195 | struct hal_h264_vui_timing_info h264_vui_timing_info; |
| 1196 | struct hal_h264_vui_bitstream_restrc h264_vui_bitstream_restrc; |
| 1197 | struct hal_preserve_text_quality preserve_text_quality; |
| 1198 | struct hal_buffer_info buffer_info; |
| 1199 | struct hal_buffer_alloc_mode buffer_alloc_mode; |
| 1200 | struct buffer_requirements buf_req; |
| 1201 | enum hal_h264_entropy h264_entropy; |
| 1202 | }; |
| 1203 | |
| 1204 | /* HAL Response */ |
| 1205 | #define IS_HAL_SYS_CMD(cmd) ((cmd) >= HAL_SYS_INIT_DONE && \ |
| 1206 | (cmd) <= HAL_SYS_ERROR) |
| 1207 | #define IS_HAL_SESSION_CMD(cmd) ((cmd) >= HAL_SESSION_EVENT_CHANGE && \ |
| 1208 | (cmd) <= HAL_SESSION_ERROR) |
| 1209 | enum hal_command_response { |
| 1210 | /* SYSTEM COMMANDS_DONE*/ |
| 1211 | HAL_SYS_INIT_DONE, |
| 1212 | HAL_SYS_SET_RESOURCE_DONE, |
| 1213 | HAL_SYS_RELEASE_RESOURCE_DONE, |
| 1214 | HAL_SYS_PING_ACK_DONE, |
| 1215 | HAL_SYS_PC_PREP_DONE, |
| 1216 | HAL_SYS_IDLE, |
| 1217 | HAL_SYS_DEBUG, |
| 1218 | HAL_SYS_WATCHDOG_TIMEOUT, |
| 1219 | HAL_SYS_ERROR, |
| 1220 | /* SESSION COMMANDS_DONE */ |
| 1221 | HAL_SESSION_EVENT_CHANGE, |
| 1222 | HAL_SESSION_LOAD_RESOURCE_DONE, |
| 1223 | HAL_SESSION_INIT_DONE, |
| 1224 | HAL_SESSION_END_DONE, |
| 1225 | HAL_SESSION_ABORT_DONE, |
| 1226 | HAL_SESSION_START_DONE, |
| 1227 | HAL_SESSION_STOP_DONE, |
| 1228 | HAL_SESSION_ETB_DONE, |
| 1229 | HAL_SESSION_FTB_DONE, |
| 1230 | HAL_SESSION_FLUSH_DONE, |
| 1231 | HAL_SESSION_SUSPEND_DONE, |
| 1232 | HAL_SESSION_RESUME_DONE, |
| 1233 | HAL_SESSION_SET_PROP_DONE, |
| 1234 | HAL_SESSION_GET_PROP_DONE, |
| 1235 | HAL_SESSION_PARSE_SEQ_HDR_DONE, |
| 1236 | HAL_SESSION_GET_SEQ_HDR_DONE, |
| 1237 | HAL_SESSION_RELEASE_BUFFER_DONE, |
| 1238 | HAL_SESSION_RELEASE_RESOURCE_DONE, |
| 1239 | HAL_SESSION_PROPERTY_INFO, |
| 1240 | HAL_SESSION_ERROR, |
| 1241 | HAL_RESPONSE_UNUSED = 0x10000000, |
| 1242 | }; |
| 1243 | |
| 1244 | struct vidc_hal_ebd { |
| 1245 | u32 timestamp_hi; |
| 1246 | u32 timestamp_lo; |
| 1247 | u32 flags; |
| 1248 | enum vidc_status status; |
| 1249 | u32 mark_target; |
| 1250 | u32 mark_data; |
| 1251 | u32 stats; |
| 1252 | u32 offset; |
| 1253 | u32 alloc_len; |
| 1254 | u32 filled_len; |
| 1255 | enum hal_picture picture_type; |
| 1256 | ion_phys_addr_t packet_buffer; |
| 1257 | ion_phys_addr_t extra_data_buffer; |
| 1258 | }; |
| 1259 | |
| 1260 | struct vidc_hal_fbd { |
| 1261 | u32 stream_id; |
| 1262 | u32 view_id; |
| 1263 | u32 timestamp_hi; |
| 1264 | u32 timestamp_lo; |
| 1265 | u32 flags1; |
| 1266 | u32 mark_target; |
| 1267 | u32 mark_data; |
| 1268 | u32 stats; |
| 1269 | u32 alloc_len1; |
| 1270 | u32 filled_len1; |
| 1271 | u32 offset1; |
| 1272 | u32 frame_width; |
| 1273 | u32 frame_height; |
| 1274 | u32 start_x_coord; |
| 1275 | u32 start_y_coord; |
| 1276 | u32 input_tag; |
| 1277 | u32 input_tag1; |
| 1278 | enum hal_picture picture_type; |
| 1279 | ion_phys_addr_t packet_buffer1; |
| 1280 | ion_phys_addr_t extra_data_buffer; |
| 1281 | u32 flags2; |
| 1282 | u32 alloc_len2; |
| 1283 | u32 filled_len2; |
| 1284 | u32 offset2; |
| 1285 | ion_phys_addr_t packet_buffer2; |
| 1286 | u32 flags3; |
| 1287 | u32 alloc_len3; |
| 1288 | u32 filled_len3; |
| 1289 | u32 offset3; |
| 1290 | ion_phys_addr_t packet_buffer3; |
| 1291 | enum hal_buffer buffer_type; |
| 1292 | }; |
| 1293 | |
| 1294 | struct msm_vidc_capability { |
| 1295 | enum hal_domain domain; |
| 1296 | enum hal_video_codec codec; |
| 1297 | struct hal_capability_supported width; |
| 1298 | struct hal_capability_supported height; |
| 1299 | struct hal_capability_supported mbs_per_frame; |
| 1300 | struct hal_capability_supported mbs_per_sec; |
| 1301 | struct hal_capability_supported frame_rate; |
| 1302 | struct hal_capability_supported scale_x; |
| 1303 | struct hal_capability_supported scale_y; |
| 1304 | struct hal_capability_supported bitrate; |
| 1305 | struct hal_capability_supported bframe; |
| 1306 | struct hal_capability_supported peakbitrate; |
| 1307 | struct hal_capability_supported hier_p; |
| 1308 | struct hal_capability_supported ltr_count; |
| 1309 | struct hal_capability_supported secure_output2_threshold; |
| 1310 | struct hal_capability_supported hier_b; |
| 1311 | struct hal_capability_supported lcu_size; |
| 1312 | struct hal_capability_supported hier_p_hybrid; |
| 1313 | struct hal_capability_supported mbs_per_sec_power_save; |
| 1314 | struct hal_profile_level_supported profile_level; |
| 1315 | struct hal_uncompressed_format_supported uncomp_format; |
| 1316 | struct hal_interlace_format_supported HAL_format; |
| 1317 | struct hal_nal_stream_format_supported nal_stream_format; |
| 1318 | struct hal_intra_refresh intra_refresh; |
| 1319 | enum buffer_mode_type alloc_mode_out; |
| 1320 | enum buffer_mode_type alloc_mode_in; |
| 1321 | u32 pixelprocess_capabilities; |
| 1322 | }; |
| 1323 | |
| 1324 | struct vidc_hal_sys_init_done { |
| 1325 | u32 dec_codec_supported; |
| 1326 | u32 enc_codec_supported; |
| 1327 | u32 codec_count; |
| 1328 | struct msm_vidc_capability *capabilities; |
| 1329 | u32 max_sessions_supported; |
| 1330 | }; |
| 1331 | |
| 1332 | struct vidc_hal_session_init_done { |
| 1333 | struct msm_vidc_capability capability; |
| 1334 | }; |
| 1335 | |
| 1336 | struct msm_vidc_cb_cmd_done { |
| 1337 | u32 device_id; |
| 1338 | void *session_id; |
| 1339 | enum vidc_status status; |
| 1340 | u32 size; |
| 1341 | union { |
| 1342 | struct vidc_resource_hdr resource_hdr; |
| 1343 | struct vidc_buffer_addr_info buffer_addr_info; |
| 1344 | struct vidc_frame_plane_config frame_plane_config; |
| 1345 | struct vidc_uncompressed_frame_config uncompressed_frame_config; |
| 1346 | struct vidc_frame_data frame_data; |
| 1347 | struct vidc_seq_hdr seq_hdr; |
| 1348 | struct vidc_hal_ebd ebd; |
| 1349 | struct vidc_hal_fbd fbd; |
| 1350 | struct vidc_hal_sys_init_done sys_init_done; |
| 1351 | struct vidc_hal_session_init_done session_init_done; |
| 1352 | struct hal_buffer_info buffer_info; |
| 1353 | union hal_get_property property; |
| 1354 | enum hal_flush flush_type; |
| 1355 | } data; |
| 1356 | }; |
| 1357 | |
| 1358 | struct msm_vidc_cb_event { |
| 1359 | u32 device_id; |
| 1360 | void *session_id; |
| 1361 | enum vidc_status status; |
| 1362 | u32 height; |
| 1363 | u32 width; |
| 1364 | enum msm_vidc_pixel_depth bit_depth; |
| 1365 | u32 hal_event_type; |
| 1366 | ion_phys_addr_t packet_buffer; |
| 1367 | ion_phys_addr_t extra_data_buffer; |
| 1368 | u32 pic_struct; |
| 1369 | u32 colour_space; |
| 1370 | }; |
| 1371 | |
| 1372 | struct msm_vidc_cb_data_done { |
| 1373 | u32 device_id; |
| 1374 | void *session_id; |
| 1375 | enum vidc_status status; |
| 1376 | u32 size; |
| 1377 | u32 clnt_data; |
| 1378 | union { |
| 1379 | struct vidc_hal_ebd input_done; |
| 1380 | struct vidc_hal_fbd output_done; |
| 1381 | }; |
| 1382 | }; |
| 1383 | |
| 1384 | struct msm_vidc_cb_info { |
| 1385 | enum hal_command_response response_type; |
| 1386 | union { |
| 1387 | struct msm_vidc_cb_cmd_done cmd; |
| 1388 | struct msm_vidc_cb_event event; |
| 1389 | struct msm_vidc_cb_data_done data; |
| 1390 | } response; |
| 1391 | }; |
| 1392 | |
| 1393 | enum msm_vidc_hfi_type { |
| 1394 | VIDC_HFI_VENUS, |
| 1395 | }; |
| 1396 | |
| 1397 | enum msm_vidc_thermal_level { |
| 1398 | VIDC_THERMAL_NORMAL = 0, |
| 1399 | VIDC_THERMAL_LOW, |
| 1400 | VIDC_THERMAL_HIGH, |
| 1401 | VIDC_THERMAL_CRITICAL |
| 1402 | }; |
| 1403 | |
| 1404 | enum vidc_vote_data_session { |
| 1405 | VIDC_BUS_VOTE_DATA_SESSION_INVALID = 0, |
| 1406 | /* No declarations exist. Values generated by VIDC_VOTE_DATA_SESSION_VAL |
| 1407 | * describe the enumerations e.g.: |
| 1408 | * |
| 1409 | * enum vidc_bus_vote_data_session_type h264_decoder_session = |
| 1410 | * VIDC_VOTE_DATA_SESSION_VAL(HAL_VIDEO_CODEC_H264, |
| 1411 | * HAL_VIDEO_DOMAIN_DECODER); |
| 1412 | */ |
| 1413 | }; |
| 1414 | |
| 1415 | /* Careful modifying VIDC_VOTE_DATA_SESSION_VAL(). |
| 1416 | * |
| 1417 | * This macro assigns two bits to each codec: the lower bit denoting the codec |
| 1418 | * type, and the higher bit denoting session type. |
| 1419 | */ |
| 1420 | static inline enum vidc_vote_data_session VIDC_VOTE_DATA_SESSION_VAL( |
| 1421 | enum hal_video_codec c, enum hal_domain d) { |
| 1422 | if (d != HAL_VIDEO_DOMAIN_ENCODER && d != HAL_VIDEO_DOMAIN_DECODER) |
| 1423 | return VIDC_BUS_VOTE_DATA_SESSION_INVALID; |
| 1424 | |
| 1425 | return (1 << ilog2(c) * 2) | ((d - 1) << (ilog2(c) * 2 + 1)); |
| 1426 | } |
| 1427 | |
| 1428 | struct msm_vidc_gov_data { |
| 1429 | struct vidc_bus_vote_data *data; |
| 1430 | u32 data_count; |
| 1431 | int imem_size; |
| 1432 | }; |
| 1433 | |
| 1434 | enum msm_vidc_power_mode { |
| 1435 | VIDC_POWER_NORMAL = 0, |
| 1436 | VIDC_POWER_LOW, |
| 1437 | VIDC_POWER_TURBO |
| 1438 | }; |
| 1439 | |
| 1440 | |
| 1441 | struct vidc_bus_vote_data { |
| 1442 | enum hal_domain domain; |
| 1443 | enum hal_video_codec codec; |
| 1444 | enum hal_uncompressed_format color_formats[2]; |
| 1445 | int num_formats; /* 1 = DPB-OPB unified; 2 = split */ |
| 1446 | int height, width, fps; |
| 1447 | enum msm_vidc_power_mode power_mode; |
| 1448 | struct imem_ab_table *imem_ab_tbl; |
| 1449 | u32 imem_ab_tbl_size; |
| 1450 | unsigned long core_freq; |
| 1451 | }; |
| 1452 | |
| 1453 | |
| 1454 | struct vidc_clk_scale_data { |
| 1455 | enum vidc_vote_data_session session[VIDC_MAX_SESSIONS]; |
| 1456 | enum msm_vidc_power_mode power_mode[VIDC_MAX_SESSIONS]; |
| 1457 | u32 load[VIDC_MAX_SESSIONS]; |
| 1458 | int num_sessions; |
| 1459 | }; |
| 1460 | |
| 1461 | struct hal_index_extradata_input_crop_payload { |
| 1462 | u32 size; |
| 1463 | u32 version; |
| 1464 | u32 port_index; |
| 1465 | u32 left; |
| 1466 | u32 top; |
| 1467 | u32 width; |
| 1468 | u32 height; |
| 1469 | }; |
| 1470 | |
| 1471 | struct hal_cmd_sys_get_property_packet { |
| 1472 | u32 size; |
| 1473 | u32 packet_type; |
| 1474 | u32 num_properties; |
| 1475 | u32 rg_property_data[1]; |
| 1476 | }; |
| 1477 | |
| 1478 | #define call_hfi_op(q, op, args...) \ |
| 1479 | (((q) && (q)->op) ? ((q)->op(args)) : 0) |
| 1480 | |
| 1481 | struct hfi_device { |
| 1482 | void *hfi_device_data; |
| 1483 | |
| 1484 | /*Add function pointers for all the hfi functions below*/ |
| 1485 | int (*core_init)(void *device); |
| 1486 | int (*core_release)(void *device); |
| 1487 | int (*core_ping)(void *device); |
| 1488 | int (*core_trigger_ssr)(void *device, enum hal_ssr_trigger_type); |
| 1489 | int (*session_init)(void *device, void *session_id, |
| 1490 | enum hal_domain session_type, enum hal_video_codec codec_type, |
| 1491 | void **new_session); |
| 1492 | int (*session_end)(void *session); |
| 1493 | int (*session_abort)(void *session); |
| 1494 | int (*session_set_buffers)(void *sess, |
| 1495 | struct vidc_buffer_addr_info *buffer_info); |
| 1496 | int (*session_release_buffers)(void *sess, |
| 1497 | struct vidc_buffer_addr_info *buffer_info); |
| 1498 | int (*session_load_res)(void *sess); |
| 1499 | int (*session_release_res)(void *sess); |
| 1500 | int (*session_start)(void *sess); |
| 1501 | int (*session_continue)(void *sess); |
| 1502 | int (*session_stop)(void *sess); |
| 1503 | int (*session_etb)(void *sess, struct vidc_frame_data *input_frame); |
| 1504 | int (*session_ftb)(void *sess, struct vidc_frame_data *output_frame); |
| 1505 | int (*session_process_batch)(void *sess, |
| 1506 | int num_etbs, struct vidc_frame_data etbs[], |
| 1507 | int num_ftbs, struct vidc_frame_data ftbs[]); |
| 1508 | int (*session_parse_seq_hdr)(void *sess, |
| 1509 | struct vidc_seq_hdr *seq_hdr); |
| 1510 | int (*session_get_seq_hdr)(void *sess, |
| 1511 | struct vidc_seq_hdr *seq_hdr); |
| 1512 | int (*session_get_buf_req)(void *sess); |
| 1513 | int (*session_flush)(void *sess, enum hal_flush flush_mode); |
| 1514 | int (*session_set_property)(void *sess, enum hal_property ptype, |
| 1515 | void *pdata); |
| 1516 | int (*session_get_property)(void *sess, enum hal_property ptype); |
| 1517 | int (*scale_clocks)(void *dev, int load, |
| 1518 | struct vidc_clk_scale_data *data, |
| 1519 | unsigned long instant_bitrate); |
| 1520 | int (*vote_bus)(void *dev, struct vidc_bus_vote_data *data, |
| 1521 | int num_data); |
| 1522 | int (*get_fw_info)(void *dev, struct hal_fw_info *fw_info); |
| 1523 | int (*session_clean)(void *sess); |
| 1524 | int (*get_core_capabilities)(void *dev); |
| 1525 | int (*suspend)(void *dev); |
| 1526 | unsigned long (*get_core_clock_rate)(void *dev, bool actual_rate); |
| 1527 | enum hal_default_properties (*get_default_properties)(void *dev); |
| 1528 | }; |
| 1529 | |
| 1530 | typedef void (*hfi_cmd_response_callback) (enum hal_command_response cmd, |
| 1531 | void *data); |
| 1532 | typedef void (*msm_vidc_callback) (u32 response, void *callback); |
| 1533 | |
| 1534 | struct hfi_device *vidc_hfi_initialize(enum msm_vidc_hfi_type hfi_type, |
| 1535 | u32 device_id, struct msm_vidc_platform_resources *res, |
| 1536 | hfi_cmd_response_callback callback); |
| 1537 | void vidc_hfi_deinitialize(enum msm_vidc_hfi_type hfi_type, |
| 1538 | struct hfi_device *hdev); |
| 1539 | u32 vidc_get_hfi_domain(enum hal_domain hal_domain); |
| 1540 | u32 vidc_get_hfi_codec(enum hal_video_codec hal_codec); |
| 1541 | enum hal_domain vidc_get_hal_domain(u32 hfi_domain); |
| 1542 | enum hal_video_codec vidc_get_hal_codec(u32 hfi_codec); |
| 1543 | |
| 1544 | #endif /*__VIDC_HFI_API_H__ */ |