| Srinu Gorle | cf8c675 | 2018-01-19 18:36:13 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2016, 2018 The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef __VIDC_HFI_IO_H__ |
| 15 | #define __VIDC_HFI_IO_H__ |
| 16 | |
| 17 | #include <linux/io.h> |
| 18 | |
| 19 | #define VENUS_VCODEC_SS_CLOCK_HALT 0x0000000C |
| 20 | #define VENUS_VPP_CORE_SW_RESET 0x00042004 |
| 21 | #define VENUS_VPP_CTRL_CTRL_RESET 0x00041008 |
| 22 | |
| 23 | #define VIDC_VBIF_BASE_OFFS 0x00080000 |
| 24 | #define VIDC_VBIF_VERSION (VIDC_VBIF_BASE_OFFS + 0x00) |
| 25 | #define VIDC_VENUS_VBIF_DDR_OUT_MAX_BURST \ |
| 26 | (VIDC_VBIF_BASE_OFFS + 0xD8) |
| 27 | #define VIDC_VENUS_VBIF_OCMEM_OUT_MAX_BURST \ |
| 28 | (VIDC_VBIF_BASE_OFFS + 0xDC) |
| 29 | #define VIDC_VENUS_VBIF_ROUND_ROBIN_QOS_ARB \ |
| 30 | (VIDC_VBIF_BASE_OFFS + 0x124) |
| 31 | |
| 32 | #define VIDC_CPU_BASE_OFFS 0x000C0000 |
| 33 | #define VIDC_CPU_CS_BASE_OFFS (VIDC_CPU_BASE_OFFS + 0x00012000) |
| 34 | #define VIDC_CPU_IC_BASE_OFFS (VIDC_CPU_BASE_OFFS + 0x0001F000) |
| 35 | |
| 36 | #define VIDC_CPU_CS_REMAP_OFFS (VIDC_CPU_CS_BASE_OFFS + 0x00) |
| 37 | #define VIDC_CPU_CS_TIMER_CONTROL (VIDC_CPU_CS_BASE_OFFS + 0x04) |
| 38 | #define VIDC_CPU_CS_A2HSOFTINTEN (VIDC_CPU_CS_BASE_OFFS + 0x10) |
| 39 | #define VIDC_CPU_CS_A2HSOFTINTENCLR (VIDC_CPU_CS_BASE_OFFS + 0x14) |
| 40 | #define VIDC_CPU_CS_A2HSOFTINT (VIDC_CPU_CS_BASE_OFFS + 0x18) |
| 41 | #define VIDC_CPU_CS_A2HSOFTINTCLR (VIDC_CPU_CS_BASE_OFFS + 0x1C) |
| 42 | #define VIDC_CPU_CS_SCIACMD (VIDC_CPU_CS_BASE_OFFS + 0x48) |
| 43 | |
| 44 | /* HFI_CTRL_STATUS */ |
| 45 | #define VIDC_CPU_CS_SCIACMDARG0 (VIDC_CPU_CS_BASE_OFFS + 0x4C) |
| 46 | #define VIDC_CPU_CS_SCIACMDARG0_BMSK 0xff |
| 47 | #define VIDC_CPU_CS_SCIACMDARG0_SHFT 0x0 |
| 48 | #define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK 0xfe |
| 49 | #define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_SHFT 0x1 |
| 50 | #define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_BMSK 0x1 |
| 51 | #define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_STATUS_SHFT 0x0 |
| 52 | #define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY 0x100 |
| 53 | #define VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK 0x40000000 |
| 54 | |
| 55 | /* HFI_QTBL_INFO */ |
| 56 | #define VIDC_CPU_CS_SCIACMDARG1 (VIDC_CPU_CS_BASE_OFFS + 0x50) |
| 57 | |
| 58 | /* HFI_QTBL_ADDR */ |
| 59 | #define VIDC_CPU_CS_SCIACMDARG2 (VIDC_CPU_CS_BASE_OFFS + 0x54) |
| 60 | |
| 61 | /* HFI_VERSION_INFO */ |
| 62 | #define VIDC_CPU_CS_SCIACMDARG3 (VIDC_CPU_CS_BASE_OFFS + 0x58) |
| 63 | #define VIDC_CPU_IC_IRQSTATUS (VIDC_CPU_IC_BASE_OFFS + 0x00) |
| 64 | #define VIDC_CPU_IC_FIQSTATUS (VIDC_CPU_IC_BASE_OFFS + 0x04) |
| 65 | #define VIDC_CPU_IC_RAWINTR (VIDC_CPU_IC_BASE_OFFS + 0x08) |
| 66 | #define VIDC_CPU_IC_INTSELECT (VIDC_CPU_IC_BASE_OFFS + 0x0C) |
| 67 | #define VIDC_CPU_IC_INTENABLE (VIDC_CPU_IC_BASE_OFFS + 0x10) |
| 68 | #define VIDC_CPU_IC_INTENACLEAR (VIDC_CPU_IC_BASE_OFFS + 0x14) |
| 69 | #define VIDC_CPU_IC_SOFTINT (VIDC_CPU_IC_BASE_OFFS + 0x18) |
| 70 | #define VIDC_CPU_IC_SOFTINT_H2A_BMSK 0x8000 |
| 71 | #define VIDC_CPU_IC_SOFTINT_H2A_SHFT 0xF |
| 72 | #define VIDC_CPU_IC_SOFTINTCLEAR (VIDC_CPU_IC_BASE_OFFS + 0x1C) |
| 73 | |
| 74 | /*--------------------------------------------------------------------------- |
| 75 | * MODULE: vidc_wrapper |
| 76 | *-------------------------------------------------------------------------- |
| 77 | */ |
| 78 | #define VIDC_WRAPPER_BASE_OFFS 0x000E0000 |
| 79 | |
| 80 | #define VIDC_WRAPPER_HW_VERSION (VIDC_WRAPPER_BASE_OFFS + 0x00) |
| 81 | #define VIDC_WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x78000000 |
| 82 | #define VIDC_WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 28 |
| 83 | #define VIDC_WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xFFF0000 |
| 84 | #define VIDC_WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 16 |
| 85 | #define VIDC_WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xFFFF |
| 86 | #define VIDC_WRAPPER_CLOCK_CONFIG (VIDC_WRAPPER_BASE_OFFS + 0x04) |
| 87 | |
| 88 | #define VIDC_WRAPPER_INTR_STATUS (VIDC_WRAPPER_BASE_OFFS + 0x0C) |
| 89 | #define VIDC_WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10 |
| 90 | #define VIDC_WRAPPER_INTR_STATUS_A2HWD_SHFT 0x4 |
| 91 | #define VIDC_WRAPPER_INTR_STATUS_A2H_BMSK 0x4 |
| 92 | #define VIDC_WRAPPER_INTR_STATUS_A2H_SHFT 0x2 |
| 93 | |
| 94 | #define VIDC_WRAPPER_INTR_MASK (VIDC_WRAPPER_BASE_OFFS + 0x10) |
| 95 | #define VIDC_WRAPPER_INTR_MASK_A2HWD_BMSK 0x10 |
| 96 | #define VIDC_WRAPPER_INTR_MASK_A2HWD_SHFT 0x4 |
| 97 | #define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK 0x8 |
| 98 | #define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_SHFT 0x3 |
| 99 | #define VIDC_WRAPPER_INTR_MASK_A2HCPU_BMSK 0x4 |
| 100 | #define VIDC_WRAPPER_INTR_MASK_A2HCPU_SHFT 0x2 |
| 101 | |
| 102 | #define VIDC_WRAPPER_INTR_CLEAR (VIDC_WRAPPER_BASE_OFFS + 0x14) |
| 103 | #define VIDC_WRAPPER_INTR_CLEAR_A2HWD_BMSK 0x10 |
| 104 | #define VIDC_WRAPPER_INTR_CLEAR_A2HWD_SHFT 0x4 |
| 105 | #define VIDC_WRAPPER_INTR_CLEAR_A2H_BMSK 0x4 |
| 106 | #define VIDC_WRAPPER_INTR_CLEAR_A2H_SHFT 0x2 |
| 107 | |
| 108 | #define VIDC_WRAPPER_VBIF_XIN_SW_RESET (VIDC_WRAPPER_BASE_OFFS + 0x18) |
| 109 | #define VIDC_WRAPPER_VBIF_XIN_STATUS (VIDC_WRAPPER_BASE_OFFS + 0x1C) |
| 110 | #define VIDC_WRAPPER_CPU_CLOCK_CONFIG (VIDC_WRAPPER_BASE_OFFS + 0x2000) |
| 111 | #define VIDC_WRAPPER_VBIF_XIN_CPU_SW_RESET \ |
| 112 | (VIDC_WRAPPER_BASE_OFFS + 0x2004) |
| 113 | #define VIDC_WRAPPER_AXI_HALT (VIDC_WRAPPER_BASE_OFFS + 0x2008) |
| 114 | #define VIDC_WRAPPER_AXI_HALT_STATUS (VIDC_WRAPPER_BASE_OFFS + 0x200C) |
| 115 | #define VIDC_WRAPPER_CPU_CGC_DIS (VIDC_WRAPPER_BASE_OFFS + 0x2010) |
| 116 | #define VIDC_WRAPPER_CPU_STATUS (VIDC_WRAPPER_BASE_OFFS + 0x2014) |
| 117 | #define VIDC_VENUS_VBIF_CLK_ON (VIDC_VBIF_BASE_OFFS + 0x4) |
| 118 | #define VIDC_VBIF_IN_RD_LIM_CONF0 (VIDC_VBIF_BASE_OFFS + 0xB0) |
| 119 | #define VIDC_VBIF_IN_RD_LIM_CONF1 (VIDC_VBIF_BASE_OFFS + 0xB4) |
| 120 | #define VIDC_VBIF_IN_RD_LIM_CONF2 (VIDC_VBIF_BASE_OFFS + 0xB8) |
| 121 | #define VIDC_VBIF_IN_RD_LIM_CONF3 (VIDC_VBIF_BASE_OFFS + 0xBC) |
| 122 | #define VIDC_VBIF_IN_WR_LIM_CONF0 (VIDC_VBIF_BASE_OFFS + 0xC0) |
| 123 | #define VIDC_VBIF_IN_WR_LIM_CONF1 (VIDC_VBIF_BASE_OFFS + 0xC4) |
| 124 | #define VIDC_VBIF_IN_WR_LIM_CONF2 (VIDC_VBIF_BASE_OFFS + 0xC8) |
| 125 | #define VIDC_VBIF_IN_WR_LIM_CONF3 (VIDC_VBIF_BASE_OFFS + 0xCC) |
| 126 | #define VIDC_VBIF_OUT_RD_LIM_CONF0 (VIDC_VBIF_BASE_OFFS + 0xD0) |
| 127 | #define VIDC_VBIF_OUT_WR_LIM_CONF0 (VIDC_VBIF_BASE_OFFS + 0xD4) |
| 128 | #define VIDC_VBIF_DDR_OUT_MAX_BURST (VIDC_VBIF_BASE_OFFS + 0xD8) |
| 129 | #define VIDC_VBIF_OCMEM_OUT_MAX_BURST (VIDC_VBIF_BASE_OFFS + 0xDC) |
| 130 | #define VIDC_VBIF_DDR_ARB_CONF0 (VIDC_VBIF_BASE_OFFS + 0xF4) |
| 131 | #define VIDC_VBIF_DDR_ARB_CONF1 (VIDC_VBIF_BASE_OFFS + 0xF8) |
| 132 | #define VIDC_VBIF_ROUND_ROBIN_QOS_ARB (VIDC_VBIF_BASE_OFFS + 0x124) |
| 133 | #define VIDC_VBIF_OUT_AXI_AOOO_EN (VIDC_VBIF_BASE_OFFS + 0x178) |
| 134 | #define VIDC_VBIF_OUT_AXI_AOOO (VIDC_VBIF_BASE_OFFS + 0x17C) |
| 135 | #define VIDC_VBIF_ARB_CTL (VIDC_VBIF_BASE_OFFS + 0xF0) |
| 136 | #define VIDC_VBIF_OUT_AXI_AMEMTYPE_CONF0 (VIDC_VBIF_BASE_OFFS + 0x160) |
| 137 | #define VIDC_VBIF_OUT_AXI_AMEMTYPE_CONF1 (VIDC_VBIF_BASE_OFFS + 0x164) |
| 138 | #define VIDC_VBIF_ADDR_TRANS_EN (VIDC_VBIF_BASE_OFFS + 0xC00) |
| 139 | #define VIDC_VBIF_AT_OLD_BASE (VIDC_VBIF_BASE_OFFS + 0xC04) |
| 140 | #define VIDC_VBIF_AT_OLD_HIGH (VIDC_VBIF_BASE_OFFS + 0xC08) |
| 141 | #define VIDC_VBIF_AT_NEW_BASE (VIDC_VBIF_BASE_OFFS + 0xC10) |
| 142 | #define VIDC_VBIF_AT_NEW_HIGH (VIDC_VBIF_BASE_OFFS + 0xC18) |
| 143 | #define VENUS_VBIF_XIN_HALT_CTRL1 (VIDC_VBIF_BASE_OFFS + 0x204) |
| 144 | #define VENUS_VBIF_AXI_HALT_CTRL0 (VIDC_VBIF_BASE_OFFS + 0x208) |
| 145 | #define VENUS_VBIF_AXI_HALT_CTRL1 (VIDC_VBIF_BASE_OFFS + 0x20C) |
| 146 | |
| 147 | #define VENUS_VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0) |
| 148 | #define VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0) |
| 149 | #define VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US 500000 |
| 150 | |
| 151 | #define VIDC_VENUS0_WRAPPER_VBIF_REQ_PRIORITY \ |
| 152 | (VIDC_WRAPPER_BASE_OFFS + 0x20) |
| 153 | #define VIDC_VENUS0_WRAPPER_VBIF_PRIORITY_LEVEL \ |
| 154 | (VIDC_WRAPPER_BASE_OFFS + 0x24) |
| 155 | #define VIDC_VENUS_WRAPPER_MMCC_VENUS0_POWER_STATUS \ |
| 156 | (VIDC_WRAPPER_BASE_OFFS + 0x44) |
| 157 | |
| 158 | #define VIDC_CTRL_INIT 0x000D2048 |
| 159 | #define VIDC_CTRL_INIT_RESERVED_BITS31_1__M 0xFFFFFFFE |
| 160 | #define VIDC_CTRL_INIT_RESERVED_BITS31_1__S 1 |
| 161 | #define VIDC_CTRL_INIT_CTRL__M 0x00000001 |
| 162 | #define VIDC_CTRL_INIT_CTRL__S 0 |
| 163 | |
| 164 | #define VIDC_CTRL_STATUS 0x000D204C |
| 165 | #define VIDC_CTRL_STATUS_RESERVED_BITS31_8__M 0xFFFFFF00 |
| 166 | #define VIDC_CTRL_STATUS_RESERVED_BITS31_8__S 8 |
| 167 | #define VIDC_CTRL_ERROR_STATUS__M 0x000000FE |
| 168 | #define VIDC_CTRL_ERROR_STATUS__S 1 |
| 169 | #define VIDC_CTRL_INIT_STATUS__M 0x00000001 |
| 170 | #define VIDC_CTRL_INIT_STATUS__S 0 |
| 171 | |
| 172 | #define VIDC_QTBL_INFO 0x000D2050 |
| 173 | #define VIDC_QTBL_HOSTID__M 0xFF000000 |
| 174 | #define VIDC_QTBL_HOSTID__S 24 |
| 175 | #define VIDC_QTBL_INFO_RESERVED_BITS23_8__M 0x00FFFF00 |
| 176 | #define VIDC_QTBL_INFO_RESERVED_BITS23_8__S 8 |
| 177 | #define VIDC_QTBL_STATUS__M 0x000000FF |
| 178 | #define VIDC_QTBL_STATUS__S 0 |
| 179 | |
| 180 | #define VIDC_QTBL_ADDR 0x000D2054 |
| 181 | |
| 182 | #define VIDC_VERSION_INFO 0x000D2058 |
| 183 | #define VIDC_VERSION_INFO_MAJOR__M 0xF0000000 |
| 184 | #define VIDC_VERSION_INFO_MAJOR__S 28 |
| 185 | #define VIDC_VERSION_INFO_MINOR__M 0x0FFFFFE0 |
| 186 | #define VIDC_VERSION_INFO_MINOR__S 5 |
| 187 | #define VIDC_VERSION_INFO_BRANCH__M 0x0000001F |
| 188 | #define VIDC_VERSION_INFO_BRANCH__S 0 |
| 189 | |
| 190 | #define VIDC_SFR_ADDR 0x000D205C |
| 191 | #define VIDC_MMAP_ADDR 0x000D2060 |
| 192 | #define VIDC_UC_REGION_ADDR 0x000D2064 |
| 193 | #define VIDC_UC_REGION_SIZE 0x000D2068 |
| 194 | |
| 195 | #endif |