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gerrit-public.fairphone.software / kernel / msm-4.9 / 140a23e0dfec6ddf09d3426b288e2653251f666d / . / drivers / platform / msm / ep_pcie / ep_pcie_com.h
blob: 00ca8dc477c5b980227ee4edeb9cf0f6635b097b [file] [log] [blame]
Yan He1bac7d92017-12-05 17:18:44 -0800[diff] [blame]1/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __EP_PCIE_COM_H
14#define __EP_PCIE_COM_H
15
16#include <linux/io.h>
17#include <linux/clk.h>
18#include <linux/compiler.h>
19#include <linux/ipc_logging.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
22#include <linux/types.h>
23#include <linux/uaccess.h>
24#include <linux/delay.h>
25#include <linux/msm_ep_pcie.h>
26
27#define PCIE20_PARF_SYS_CTRL 0x00
28#define PCIE20_PARF_DB_CTRL 0x10
29#define PCIE20_PARF_PM_CTRL 0x20
30#define PCIE20_PARF_PM_STTS 0x24
31#define PCIE20_PARF_PHY_CTRL 0x40
32#define PCIE20_PARF_PHY_REFCLK 0x4C
33#define PCIE20_PARF_CONFIG_BITS 0x50
34#define PCIE20_PARF_TEST_BUS 0xE4
35#define PCIE20_PARF_MHI_BASE_ADDR_LOWER 0x178
36#define PCIE20_PARF_MHI_BASE_ADDR_UPPER 0x17c
37#define PCIE20_PARF_MSI_GEN 0x188
38#define PCIE20_PARF_DEBUG_INT_EN 0x190
39#define PCIE20_PARF_MHI_IPA_DBS 0x198
40#define PCIE20_PARF_MHI_IPA_CDB_TARGET_LOWER 0x19C
41#define PCIE20_PARF_MHI_IPA_EDB_TARGET_LOWER 0x1A0
42#define PCIE20_PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1A4
43#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x1A8
44#define PCIE20_PARF_Q2A_FLUSH 0x1AC
45#define PCIE20_PARF_LTSSM 0x1B0
46#define PCIE20_PARF_CFG_BITS 0x210
47#define PCIE20_PARF_LTR_MSI_EXIT_L1SS 0x214
48#define PCIE20_PARF_INT_ALL_STATUS 0x224
49#define PCIE20_PARF_INT_ALL_CLEAR 0x228
50#define PCIE20_PARF_INT_ALL_MASK 0x22C
51#define PCIE20_PARF_SLV_ADDR_MSB_CTRL 0x2C0
52#define PCIE20_PARF_DBI_BASE_ADDR 0x350
53#define PCIE20_PARF_DBI_BASE_ADDR_HI 0x354
54#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358
55#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI 0x35C
Yan He759abe92017-12-20 10:58:33 -0800[diff] [blame]56#define PCIE20_PARF_ATU_BASE_ADDR 0x634
57#define PCIE20_PARF_ATU_BASE_ADDR_HI 0x638
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]58#define PCIE20_PARF_DEVICE_TYPE 0x1000
59
60#define PCIE20_ELBI_VERSION 0x00
61#define PCIE20_ELBI_SYS_CTRL 0x04
62#define PCIE20_ELBI_SYS_STTS 0x08
63#define PCIE20_ELBI_CS2_ENABLE 0xA4
64
65#define PCIE20_DEVICE_ID_VENDOR_ID 0x00
66#define PCIE20_COMMAND_STATUS 0x04
67#define PCIE20_CLASS_CODE_REVISION_ID 0x08
68#define PCIE20_BIST_HDR_TYPE 0x0C
69#define PCIE20_BAR0 0x10
70#define PCIE20_SUBSYSTEM 0x2c
71#define PCIE20_CAP_ID_NXT_PTR 0x40
72#define PCIE20_CON_STATUS 0x44
73#define PCIE20_MSI_CAP_ID_NEXT_CTRL 0x50
74#define PCIE20_MSI_LOWER 0x54
75#define PCIE20_MSI_UPPER 0x58
76#define PCIE20_MSI_DATA 0x5C
77#define PCIE20_MSI_MASK 0x60
78#define PCIE20_DEVICE_CAPABILITIES 0x74
79#define PCIE20_MASK_EP_L1_ACCPT_LATENCY 0xE00
80#define PCIE20_MASK_EP_L0S_ACCPT_LATENCY 0x1C0
81#define PCIE20_LINK_CAPABILITIES 0x7C
82#define PCIE20_MASK_CLOCK_POWER_MAN 0x40000
83#define PCIE20_MASK_L1_EXIT_LATENCY 0x38000
84#define PCIE20_MASK_L0S_EXIT_LATENCY 0x7000
85#define PCIE20_CAP_LINKCTRLSTATUS 0x80
86#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
87#define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0
88#define PCIE20_L1SUB_CAPABILITY 0x154
89#define PCIE20_L1SUB_CONTROL1 0x158
90#define PCIE20_ACK_F_ASPM_CTRL_REG 0x70C
91#define PCIE20_MASK_ACK_N_FTS 0xff00
92#define PCIE20_MISC_CONTROL_1 0x8BC
93
94#define PCIE20_PLR_IATU_VIEWPORT 0x900
95#define PCIE20_PLR_IATU_CTRL1 0x904
96#define PCIE20_PLR_IATU_CTRL2 0x908
97#define PCIE20_PLR_IATU_LBAR 0x90C
98#define PCIE20_PLR_IATU_UBAR 0x910
99#define PCIE20_PLR_IATU_LAR 0x914
100#define PCIE20_PLR_IATU_LTAR 0x918
101#define PCIE20_PLR_IATU_UTAR 0x91c
102
Yan He1bac7d92017-12-05 17:18:44 -0800[diff] [blame]103#define PCIE20_IATU_BASE(n) (n * 0x200)
104
105#define PCIE20_IATU_O_CTRL1(n) (PCIE20_IATU_BASE(n) + 0x00)
106#define PCIE20_IATU_O_CTRL2(n) (PCIE20_IATU_BASE(n) + 0x04)
107#define PCIE20_IATU_O_LBAR(n) (PCIE20_IATU_BASE(n) + 0x08)
108#define PCIE20_IATU_O_UBAR(n) (PCIE20_IATU_BASE(n) + 0x0c)
109#define PCIE20_IATU_O_LAR(n) (PCIE20_IATU_BASE(n) + 0x10)
110#define PCIE20_IATU_O_LTAR(n) (PCIE20_IATU_BASE(n) + 0x14)
111#define PCIE20_IATU_O_UTAR(n) (PCIE20_IATU_BASE(n) + 0x18)
112
113#define PCIE20_IATU_I_CTRL1(n) (PCIE20_IATU_BASE(n) + 0x100)
114#define PCIE20_IATU_I_CTRL2(n) (PCIE20_IATU_BASE(n) + 0x104)
115#define PCIE20_IATU_I_LBAR(n) (PCIE20_IATU_BASE(n) + 0x108)
116#define PCIE20_IATU_I_UBAR(n) (PCIE20_IATU_BASE(n) + 0x10c)
117#define PCIE20_IATU_I_LAR(n) (PCIE20_IATU_BASE(n) + 0x110)
118#define PCIE20_IATU_I_LTAR(n) (PCIE20_IATU_BASE(n) + 0x114)
119#define PCIE20_IATU_I_UTAR(n) (PCIE20_IATU_BASE(n) + 0x118)
120
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]121#define PCIE20_MHICFG 0x110
122#define PCIE20_BHI_EXECENV 0x228
123
124#define PCIE20_AUX_CLK_FREQ_REG 0xB40
125
126#define PERST_TIMEOUT_US_MIN 1000
127#define PERST_TIMEOUT_US_MAX 1000
128#define PERST_CHECK_MAX_COUNT 30000
129#define LINK_UP_TIMEOUT_US_MIN 1000
130#define LINK_UP_TIMEOUT_US_MAX 1000
131#define LINK_UP_CHECK_MAX_COUNT 30000
132#define BME_TIMEOUT_US_MIN 1000
133#define BME_TIMEOUT_US_MAX 1000
134#define BME_CHECK_MAX_COUNT 30000
135#define PHY_STABILIZATION_DELAY_US_MIN 1000
136#define PHY_STABILIZATION_DELAY_US_MAX 1000
137#define REFCLK_STABILIZATION_DELAY_US_MIN 1000
138#define REFCLK_STABILIZATION_DELAY_US_MAX 1000
139#define PHY_READY_TIMEOUT_COUNT 30000
140#define MSI_EXIT_L1SS_WAIT 10
141#define MSI_EXIT_L1SS_WAIT_MAX_COUNT 100
142#define XMLH_LINK_UP 0x400
143#define PARF_XMLH_LINK_UP 0x40000000
144
145#define MAX_PROP_SIZE 32
146#define MAX_MSG_LEN 80
147#define MAX_NAME_LEN 80
148#define MAX_IATU_ENTRY_NUM 2
149
150#define EP_PCIE_LOG_PAGES 50
151#define EP_PCIE_MAX_VREG 2
Yan He759abe92017-12-20 10:58:33 -0800[diff] [blame]152#define EP_PCIE_MAX_CLK 7
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]153#define EP_PCIE_MAX_PIPE_CLK 1
154#define EP_PCIE_MAX_RESET 2
155
156#define EP_PCIE_ERROR -30655
157#define EP_PCIE_LINK_DOWN 0xFFFFFFFF
158
159#define EP_PCIE_OATU_INDEX_MSI 1
160#define EP_PCIE_OATU_INDEX_CTRL 2
161#define EP_PCIE_OATU_INDEX_DATA 3
162
163#define EP_PCIE_OATU_UPPER 0x100
164
165#define EP_PCIE_GEN_DBG(x...) do { \
166 if (ep_pcie_get_debug_mask()) \
167 pr_alert(x); \
168 else \
169 pr_debug(x); \
170 } while (0)
171
172#define EP_PCIE_DBG(dev, fmt, arg...) do { \
173 if ((dev)->ipc_log_ful) \
174 ipc_log_string((dev)->ipc_log_ful, "%s: " fmt, __func__, arg); \
175 if (ep_pcie_get_debug_mask()) \
176 pr_alert("%s: " fmt, __func__, arg); \
177 } while (0)
178
179#define EP_PCIE_DBG2(dev, fmt, arg...) do { \
180 if ((dev)->ipc_log_sel) \
181 ipc_log_string((dev)->ipc_log_sel, \
182 "DBG1:%s: " fmt, __func__, arg); \
183 if ((dev)->ipc_log_ful) \
184 ipc_log_string((dev)->ipc_log_ful, \
185 "DBG2:%s: " fmt, __func__, arg); \
186 if (ep_pcie_get_debug_mask()) \
187 pr_alert("%s: " fmt, __func__, arg); \
188 } while (0)
189
190#define EP_PCIE_DBG_FS(fmt, arg...) pr_alert("%s: " fmt, __func__, arg)
191
192#define EP_PCIE_DUMP(dev, fmt, arg...) do { \
193 if ((dev)->ipc_log_dump) \
194 ipc_log_string((dev)->ipc_log_dump, \
195 "DUMP:%s: " fmt, __func__, arg); \
196 if (ep_pcie_get_debug_mask()) \
197 pr_alert("%s: " fmt, __func__, arg); \
198 } while (0)
199
200#define EP_PCIE_INFO(dev, fmt, arg...) do { \
201 if ((dev)->ipc_log_sel) \
202 ipc_log_string((dev)->ipc_log_sel, \
203 "INFO:%s: " fmt, __func__, arg); \
204 if ((dev)->ipc_log_ful) \
205 ipc_log_string((dev)->ipc_log_ful, "%s: " fmt, __func__, arg); \
206 pr_info("%s: " fmt, __func__, arg); \
207 } while (0)
208
209#define EP_PCIE_ERR(dev, fmt, arg...) do { \
210 if ((dev)->ipc_log_sel) \
211 ipc_log_string((dev)->ipc_log_sel, \
212 "ERR:%s: " fmt, __func__, arg); \
213 if ((dev)->ipc_log_ful) \
214 ipc_log_string((dev)->ipc_log_ful, "%s: " fmt, __func__, arg); \
215 pr_err("%s: " fmt, __func__, arg); \
216 } while (0)
217
218enum ep_pcie_res {
219 EP_PCIE_RES_PARF,
220 EP_PCIE_RES_PHY,
221 EP_PCIE_RES_MMIO,
222 EP_PCIE_RES_MSI,
223 EP_PCIE_RES_DM_CORE,
224 EP_PCIE_RES_ELBI,
Yan He1bac7d92017-12-05 17:18:44 -0800[diff] [blame]225 EP_PCIE_RES_IATU,
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]226 EP_PCIE_MAX_RES,
227};
228
229enum ep_pcie_irq {
230 EP_PCIE_INT_PM_TURNOFF,
231 EP_PCIE_INT_DSTATE_CHANGE,
232 EP_PCIE_INT_L1SUB_TIMEOUT,
233 EP_PCIE_INT_LINK_UP,
234 EP_PCIE_INT_LINK_DOWN,
235 EP_PCIE_INT_BRIDGE_FLUSH_N,
236 EP_PCIE_INT_BME,
237 EP_PCIE_INT_GLOBAL,
238 EP_PCIE_MAX_IRQ,
239};
240
241enum ep_pcie_gpio {
242 EP_PCIE_GPIO_PERST,
243 EP_PCIE_GPIO_WAKE,
244 EP_PCIE_GPIO_CLKREQ,
245 EP_PCIE_GPIO_MDM2AP,
246 EP_PCIE_MAX_GPIO,
247};
248
249struct ep_pcie_gpio_info_t {
250 char *name;
251 u32 num;
252 bool out;
253 u32 on;
254 u32 init;
255};
256
257struct ep_pcie_vreg_info_t {
258 struct regulator *hdl;
259 char *name;
260 u32 max_v;
261 u32 min_v;
262 u32 opt_mode;
263 bool required;
264};
265
266struct ep_pcie_clk_info_t {
267 struct clk *hdl;
268 char *name;
269 u32 freq;
270 bool required;
271};
272
273struct ep_pcie_reset_info_t {
274 struct reset_control *hdl;
275 char *name;
276 bool required;
277};
278
279struct ep_pcie_res_info_t {
280 char *name;
281 struct resource *resource;
282 void __iomem *base;
283};
284
285struct ep_pcie_irq_info_t {
286 char *name;
287 u32 num;
288};
289
290/* phy info structure */
291struct ep_pcie_phy_info_t {
292 u32 offset;
293 u32 val;
294 u32 delay;
295 u32 direction;
296};
297
298/* pcie endpoint device structure */
299struct ep_pcie_dev_t {
300 struct platform_device *pdev;
301 struct regulator *gdsc;
302 struct ep_pcie_vreg_info_t vreg[EP_PCIE_MAX_VREG];
303 struct ep_pcie_gpio_info_t gpio[EP_PCIE_MAX_GPIO];
304 struct ep_pcie_clk_info_t clk[EP_PCIE_MAX_CLK];
305 struct ep_pcie_clk_info_t pipeclk[EP_PCIE_MAX_PIPE_CLK];
306 struct ep_pcie_reset_info_t reset[EP_PCIE_MAX_RESET];
307 struct ep_pcie_irq_info_t irq[EP_PCIE_MAX_IRQ];
308 struct ep_pcie_res_info_t res[EP_PCIE_MAX_RES];
309
310 void __iomem *parf;
311 void __iomem *phy;
312 void __iomem *mmio;
313 void __iomem *msi;
314 void __iomem *dm_core;
315 void __iomem *elbi;
Yan He1bac7d92017-12-05 17:18:44 -0800[diff] [blame]316 void __iomem *iatu;
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]317
318 struct msm_bus_scale_pdata *bus_scale_table;
319 u32 bus_client;
320 u32 link_speed;
321 bool active_config;
322 bool aggregated_irq;
323 bool mhi_a7_irq;
324 u32 dbi_base_reg;
325 u32 slv_space_reg;
326 u32 phy_status_reg;
327 u32 phy_init_len;
328 struct ep_pcie_phy_info_t *phy_init;
329 bool perst_enum;
330
331 u32 rev;
332 u32 phy_rev;
333 void *ipc_log_sel;
334 void *ipc_log_ful;
335 void *ipc_log_dump;
336 struct mutex setup_mtx;
337 struct mutex ext_mtx;
338 spinlock_t ext_lock;
339 unsigned long ext_save_flags;
340
341 spinlock_t isr_lock;
342 unsigned long isr_save_flags;
343 ulong linkdown_counter;
344 ulong linkup_counter;
345 ulong bme_counter;
346 ulong pm_to_counter;
347 ulong d0_counter;
348 ulong d3_counter;
349 ulong perst_ast_counter;
350 ulong perst_deast_counter;
351 ulong wake_counter;
352 ulong msi_counter;
353 ulong global_irq_counter;
354
355 bool dump_conf;
356
357 bool enumerated;
358 enum ep_pcie_link_status link_status;
359 bool perst_deast;
360 bool power_on;
361 bool suspending;
362 bool l23_ready;
363 bool l1ss_enabled;
364 struct ep_pcie_msi_config msi_cfg;
Yan He08169892017-10-27 17:40:24 -0700[diff] [blame]365 bool no_notify;
366 bool client_ready;
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]367
368 struct ep_pcie_register_event *event_reg;
369 struct work_struct handle_perst_work;
370 struct work_struct handle_bme_work;
Yan He08169892017-10-27 17:40:24 -0700[diff] [blame]371 struct work_struct handle_d3cold_work;
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]372};
373
374extern struct ep_pcie_dev_t ep_pcie_dev;
375extern struct ep_pcie_hw hw_drv;
376
377static inline void ep_pcie_write_mask(void __iomem *addr,
378 u32 clear_mask, u32 set_mask)
379{
380 u32 val;
381
382 val = (readl_relaxed(addr) & ~clear_mask) | set_mask;
383 writel_relaxed(val, addr);
384 /* ensure register write goes through before next regiser operation */
385 wmb();
386}
387
388static inline void ep_pcie_write_reg(void __iomem *base, u32 offset, u32 value)
389{
390 writel_relaxed(value, base + offset);
391 /* ensure register write goes through before next regiser operation */
392 wmb();
393}
394
395static inline void ep_pcie_write_reg_field(void __iomem *base, u32 offset,
396 const u32 mask, u32 val)
397{
398 u32 shift = find_first_bit((void *)&mask, 32);
399 u32 tmp = readl_relaxed(base + offset);
400
401 tmp &= ~mask; /* clear written bits */
402 val = tmp | (val << shift);
403 writel_relaxed(val, base + offset);
404 /* ensure register write goes through before next regiser operation */
405 wmb();
406}
407
408extern int ep_pcie_core_register_event(struct ep_pcie_register_event *reg);
409extern int ep_pcie_get_debug_mask(void);
410extern void ep_pcie_phy_init(struct ep_pcie_dev_t *dev);
411extern bool ep_pcie_phy_is_ready(struct ep_pcie_dev_t *dev);
412extern void ep_pcie_reg_dump(struct ep_pcie_dev_t *dev, u32 sel, bool linkdown);
413extern void ep_pcie_debugfs_init(struct ep_pcie_dev_t *ep_dev);
414extern void ep_pcie_debugfs_exit(void);
415
416#endif