Harry Yang | 4b7db0f | 2017-11-27 10:50:44 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2018 The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __SMB5_CHARGER_REG_H |
| 14 | #define __SMB5_CHARGER_REG_H |
| 15 | |
| 16 | #include <linux/bitops.h> |
| 17 | |
| 18 | #define CHGR_BASE 0x1000 |
| 19 | #define DCDC_BASE 0x1100 |
| 20 | #define BATIF_BASE 0x1200 |
| 21 | #define USBIN_BASE 0x1300 |
| 22 | #define DCIN_BASE 0x1400 |
| 23 | #define TYPEC_BASE 0X1500 |
| 24 | #define MISC_BASE 0x1600 |
| 25 | |
| 26 | #define PERPH_TYPE_OFFSET 0x04 |
| 27 | #define TYPE_MASK GENMASK(7, 0) |
| 28 | #define PERPH_SUBTYPE_OFFSET 0x05 |
| 29 | #define SUBTYPE_MASK GENMASK(7, 0) |
| 30 | #define INT_RT_STS_OFFSET 0x10 |
| 31 | |
| 32 | /******************************** |
| 33 | * CHGR Peripheral Registers * |
| 34 | ********************************/ |
| 35 | #define BATTERY_CHARGER_STATUS_1_REG (CHGR_BASE + 0x06) |
| 36 | #define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0) |
| 37 | enum { |
| 38 | INHIBIT_CHARGE = 0, |
| 39 | TRICKLE_CHARGE, |
| 40 | PRE_CHARGE, |
| 41 | FULLON_CHARGE, |
| 42 | TAPER_CHARGE, |
| 43 | TERMINATE_CHARGE, |
| 44 | PAUSE_CHARGE, |
| 45 | DISABLE_CHARGE, |
| 46 | }; |
| 47 | |
| 48 | #define BATTERY_CHARGER_STATUS_2_REG (CHGR_BASE + 0x07) |
| 49 | #define CHARGER_ERROR_STATUS_BAT_OV_BIT BIT(1) |
| 50 | |
| 51 | #define BATTERY_CHARGER_STATUS_5_REG (CHGR_BASE + 0x0B) |
| 52 | #define ENABLE_TRICKLE_BIT BIT(2) |
| 53 | #define ENABLE_PRE_CHARGING_BIT BIT(1) |
| 54 | #define ENABLE_FULLON_MODE_BIT BIT(0) |
| 55 | |
| 56 | #define BATTERY_CHARGER_STATUS_7_REG (CHGR_BASE + 0x0D) |
| 57 | #define BAT_TEMP_STATUS_SOFT_LIMIT_MASK GENMASK(5, 4) |
| 58 | #define BAT_TEMP_STATUS_HOT_SOFT_BIT BIT(5) |
| 59 | #define BAT_TEMP_STATUS_COLD_SOFT_BIT BIT(4) |
| 60 | #define BAT_TEMP_STATUS_TOO_HOT_BIT BIT(3) |
| 61 | #define BAT_TEMP_STATUS_TOO_COLD_BIT BIT(2) |
| 62 | #define BAT_TEMP_STATUS_TOO_HOT_AFP_BIT BIT(1) |
| 63 | #define BAT_TEMP_STATUS_TOO_COLD_AFP_BIT BIT(0) |
| 64 | |
| 65 | #define CHARGING_ENABLE_CMD_REG (CHGR_BASE + 0x42) |
| 66 | #define CHARGING_ENABLE_CMD_BIT BIT(0) |
| 67 | |
| 68 | #define CHGR_CFG2_REG (CHGR_BASE + 0x51) |
| 69 | #define SOC_BASED_RECHG_BIT BIT(1) |
| 70 | #define CHARGER_INHIBIT_BIT BIT(0) |
| 71 | |
| 72 | #define CHGR_FAST_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x61) |
| 73 | |
| 74 | #define CHGR_FLOAT_VOLTAGE_CFG_REG (CHGR_BASE + 0x70) |
| 75 | |
| 76 | #define CHARGE_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x72) |
| 77 | #define CHARGE_INHIBIT_THRESHOLD_MASK GENMASK(1, 0) |
| 78 | #define INHIBIT_ANALOG_VFLT_MINUS_50MV 0 |
| 79 | #define INHIBIT_ANALOG_VFLT_MINUS_100MV 1 |
| 80 | #define INHIBIT_ANALOG_VFLT_MINUS_200MV 2 |
| 81 | #define INHIBIT_ANALOG_VFLT_MINUS_300MV 3 |
| 82 | |
| 83 | #define JEITA_EN_CFG_REG (CHGR_BASE + 0x90) |
| 84 | #define JEITA_EN_HOT_SL_FCV_BIT BIT(3) |
| 85 | #define JEITA_EN_COLD_SL_FCV_BIT BIT(2) |
| 86 | #define JEITA_EN_HOT_SL_CCC_BIT BIT(1) |
| 87 | #define JEITA_EN_COLD_SL_CCC_BIT BIT(0) |
| 88 | |
| 89 | #define JEITA_CCCOMP_CFG_HOT_REG (CHGR_BASE + 0x92) |
| 90 | #define JEITA_CCCOMP_CFG_COLD_REG (CHGR_BASE + 0x93) |
| 91 | |
| 92 | /******************************** |
| 93 | * DCDC Peripheral Registers * |
| 94 | ********************************/ |
| 95 | #define AICL_ICL_STATUS_REG (DCDC_BASE + 0x08) |
| 96 | |
| 97 | #define AICL_STATUS_REG (DCDC_BASE + 0x0A) |
| 98 | #define SOFT_ILIMIT_BIT BIT(6) |
| 99 | #define AICL_DONE_BIT BIT(0) |
| 100 | |
| 101 | #define POWER_PATH_STATUS_REG (DCDC_BASE + 0x0B) |
| 102 | #define USBIN_SUSPEND_STS_BIT BIT(6) |
| 103 | #define USE_USBIN_BIT BIT(4) |
| 104 | #define USE_DCIN_BIT BIT(3) |
| 105 | #define VALID_INPUT_POWER_SOURCE_STS_BIT BIT(0) |
| 106 | |
| 107 | #define DCDC_CMD_OTG_REG (DCDC_BASE + 0x40) |
| 108 | #define OTG_EN_BIT BIT(0) |
| 109 | |
| 110 | #define DCDC_FSW_SEL_REG (DCDC_BASE + 0x50) |
| 111 | |
| 112 | #define DCDC_OTG_CURRENT_LIMIT_CFG_REG (DCDC_BASE + 0x52) |
| 113 | |
| 114 | #define DCDC_OTG_CFG_REG (DCDC_BASE + 0x53) |
| 115 | #define OTG_EN_SRC_CFG_BIT BIT(1) |
| 116 | |
| 117 | /******************************** |
| 118 | * BATIF Peripheral Registers * |
| 119 | ********************************/ |
| 120 | |
| 121 | /* BATIF Interrupt Bits */ |
| 122 | #define VPH_OV_RT_STS_BIT BIT(7) |
| 123 | #define BUCK_OC_RT_STS_BIT BIT(6) |
| 124 | #define BAT_TERMINAL_MISSING_RT_STS_BIT BIT(5) |
| 125 | #define BAT_THERM_OR_ID_MISSING_RT_STS_BIT BIT(4) |
| 126 | #define BAT_LOW_RT_STS_BIT BIT(3) |
| 127 | #define BAT_OV_RT_STS_BIT BIT(2) |
| 128 | #define ALL_CHNL_CONV_DONE_RT_STS BIT(1) |
| 129 | #define BAT_TEMP_RT_STS_BIT BIT(0) |
| 130 | |
| 131 | #define SHIP_MODE_REG (BATIF_BASE + 0x40) |
| 132 | #define SHIP_MODE_EN_BIT BIT(0) |
| 133 | |
| 134 | /******************************** |
| 135 | * USBIN Peripheral Registers * |
| 136 | ********************************/ |
| 137 | #define APSD_STATUS_REG (USBIN_BASE + 0x07) |
| 138 | #define APSD_STATUS_7_BIT BIT(7) |
| 139 | #define HVDCP_CHECK_TIMEOUT_BIT BIT(6) |
| 140 | #define SLOW_PLUGIN_TIMEOUT_BIT BIT(5) |
| 141 | #define ENUMERATION_DONE_BIT BIT(4) |
| 142 | #define VADP_CHANGE_DONE_AFTER_AUTH_BIT BIT(3) |
| 143 | #define QC_AUTH_DONE_STATUS_BIT BIT(2) |
| 144 | #define QC_CHARGER_BIT BIT(1) |
| 145 | #define APSD_DTC_STATUS_DONE_BIT BIT(0) |
| 146 | |
| 147 | #define APSD_RESULT_STATUS_REG (USBIN_BASE + 0x08) |
| 148 | #define APSD_RESULT_STATUS_7_BIT BIT(7) |
| 149 | #define APSD_RESULT_STATUS_MASK GENMASK(6, 0) |
| 150 | #define QC_3P0_BIT BIT(6) |
| 151 | #define QC_2P0_BIT BIT(5) |
| 152 | #define FLOAT_CHARGER_BIT BIT(4) |
| 153 | #define DCP_CHARGER_BIT BIT(3) |
| 154 | #define CDP_CHARGER_BIT BIT(2) |
| 155 | #define OCP_CHARGER_BIT BIT(1) |
| 156 | #define SDP_CHARGER_BIT BIT(0) |
| 157 | |
| 158 | #define QC_CHANGE_STATUS_REG (USBIN_BASE + 0x09) |
| 159 | #define QC_12V_BIT BIT(2) |
| 160 | #define QC_9V_BIT BIT(1) |
| 161 | #define QC_5V_BIT BIT(0) |
| 162 | #define QC_2P0_STATUS_MASK GENMASK(2, 0) |
| 163 | |
| 164 | /* USBIN Interrupt Bits */ |
| 165 | #define USBIN_ICL_CHANGE_RT_STS_BIT BIT(7) |
| 166 | #define USBIN_SOURCE_CHANGE_RT_STS_BIT BIT(6) |
| 167 | #define USBIN_REVI_RT_STS_BIT BIT(5) |
| 168 | #define USBIN_PLUGIN_RT_STS_BIT BIT(4) |
| 169 | #define USBIN_OV_RT_STS_BIT BIT(3) |
| 170 | #define USBIN_UV_RT_STS_BIT BIT(2) |
| 171 | #define USBIN_VASHDN_RT_STS_BIT BIT(1) |
| 172 | #define USBIN_COLLAPSE_RT_STS_BIT BIT(0) |
| 173 | |
| 174 | #define USBIN_CMD_IL_REG (USBIN_BASE + 0x40) |
| 175 | #define USBIN_SUSPEND_BIT BIT(0) |
| 176 | |
| 177 | #define CMD_APSD_REG (USBIN_BASE + 0x41) |
| 178 | #define APSD_RERUN_BIT BIT(0) |
| 179 | |
| 180 | #define CMD_HVDCP_2_REG (USBIN_BASE + 0x43) |
| 181 | #define FORCE_5V_BIT BIT(3) |
| 182 | #define SINGLE_DECREMENT_BIT BIT(1) |
| 183 | #define SINGLE_INCREMENT_BIT BIT(0) |
| 184 | |
| 185 | #define USBIN_ADAPTER_ALLOW_CFG_REG (USBIN_BASE + 0x60) |
| 186 | enum { |
| 187 | USBIN_ADAPTER_ALLOW_5V = 0, |
| 188 | USBIN_ADAPTER_ALLOW_9V = 2, |
| 189 | USBIN_ADAPTER_ALLOW_5V_OR_9V = 3, |
| 190 | USBIN_ADAPTER_ALLOW_12V = 4, |
| 191 | USBIN_ADAPTER_ALLOW_5V_OR_12V = 5, |
| 192 | USBIN_ADAPTER_ALLOW_9V_TO_12V = 6, |
| 193 | USBIN_ADAPTER_ALLOW_5V_OR_9V_TO_12V = 7, |
| 194 | USBIN_ADAPTER_ALLOW_5V_TO_9V = 8, |
| 195 | USBIN_ADAPTER_ALLOW_5V_TO_12V = 12, |
| 196 | }; |
| 197 | |
| 198 | #define USBIN_OPTIONS_1_CFG_REG (USBIN_BASE + 0x62) |
| 199 | #define HVDCP_AUTONOMOUS_MODE_EN_CFG_BIT BIT(5) |
| 200 | #define BC1P2_SRC_DETECT_BIT BIT(3) |
| 201 | |
| 202 | #define USBIN_OPTIONS_2_CFG_REG (USBIN_BASE + 0x63) |
| 203 | #define FLOAT_OPTIONS_MASK GENMASK(2, 0) |
| 204 | #define FLOAT_DIS_CHGING_CFG_BIT BIT(2) |
| 205 | #define SUSPEND_FLOAT_CFG_BIT BIT(1) |
| 206 | #define FORCE_FLOAT_SDP_CFG_BIT BIT(0) |
| 207 | |
| 208 | #define USBIN_LOAD_CFG_REG (USBIN_BASE + 0x65) |
| 209 | #define ICL_OVERRIDE_AFTER_APSD_BIT BIT(4) |
| 210 | |
| 211 | #define USBIN_ICL_OPTIONS_REG (USBIN_BASE + 0x66) |
| 212 | #define CFG_USB3P0_SEL_BIT BIT(2) |
| 213 | #define USB51_MODE_BIT BIT(1) |
| 214 | #define USBIN_MODE_CHG_BIT BIT(0) |
| 215 | |
| 216 | #define USBIN_CURRENT_LIMIT_CFG_REG (USBIN_BASE + 0x70) |
| 217 | |
| 218 | #define USBIN_AICL_OPTIONS_CFG_REG (USBIN_BASE + 0x80) |
| 219 | #define USBIN_AICL_ADC_EN_BIT BIT(3) |
| 220 | |
| 221 | /******************************** |
| 222 | * DCIN Peripheral Registers * |
| 223 | ********************************/ |
| 224 | |
| 225 | /* DCIN Interrupt Bits */ |
| 226 | #define DCIN_PLUGIN_RT_STS_BIT BIT(4) |
| 227 | |
| 228 | #define DCIN_CMD_IL_REG (DCIN_BASE + 0x40) |
| 229 | #define DCIN_SUSPEND_BIT BIT(0) |
| 230 | |
| 231 | /******************************** |
| 232 | * TYPEC Peripheral Registers * |
| 233 | ********************************/ |
| 234 | #define TYPE_C_SNK_STATUS_REG (TYPEC_BASE + 0x06) |
| 235 | #define DETECTED_SRC_TYPE_MASK GENMASK(3, 1) |
| 236 | #define SNK_RP_STD_BIT BIT(3) |
| 237 | #define SNK_RP_1P5_BIT BIT(2) |
| 238 | #define SNK_RP_3P0_BIT BIT(1) |
| 239 | |
| 240 | #define TYPE_C_SRC_STATUS_REG (TYPEC_BASE + 0x08) |
| 241 | #define DETECTED_SNK_TYPE_MASK GENMASK(4, 0) |
| 242 | #define SRC_DEBUG_ACCESS_BIT BIT(4) |
| 243 | #define SRC_RD_OPEN_BIT BIT(3) |
| 244 | #define SRC_RD_RA_VCONN_BIT BIT(2) |
| 245 | #define SRC_RA_OPEN_BIT BIT(1) |
| 246 | #define AUDIO_ACCESS_RA_RA_BIT BIT(0) |
| 247 | |
| 248 | #define TYPE_C_MISC_STATUS_REG (TYPEC_BASE + 0x0B) |
| 249 | #define SNK_SRC_MODE_BIT BIT(6) |
| 250 | #define TYPEC_VBUS_ERROR_STATUS_BIT BIT(4) |
| 251 | #define CC_ORIENTATION_BIT BIT(1) |
| 252 | #define CC_ATTACHED_BIT BIT(0) |
| 253 | |
| 254 | #define LEGACY_CABLE_STATUS_REG (TYPEC_BASE + 0x0D) |
| 255 | #define TYPEC_NONCOMP_LEGACY_CABLE_STATUS_BIT BIT(0) |
| 256 | |
| 257 | #define TYPEC_U_USB_STATUS_REG (TYPEC_BASE + 0x0F) |
| 258 | #define U_USB_GROUND_NOVBUS_BIT BIT(6) |
| 259 | #define U_USB_GROUND_BIT BIT(4) |
| 260 | |
| 261 | #define TYPE_C_MODE_CFG_REG (TYPEC_BASE + 0x44) |
| 262 | #define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0) |
| 263 | #define EN_SRC_ONLY_BIT BIT(2) |
| 264 | #define EN_SNK_ONLY_BIT BIT(1) |
| 265 | #define TYPEC_DISABLE_CMD_BIT BIT(0) |
| 266 | |
| 267 | #define TYPE_C_VCONN_CONTROL_REG (TYPEC_BASE + 0x46) |
| 268 | #define VCONN_EN_VALUE_BIT BIT(1) |
| 269 | #define VCONN_EN_SRC_BIT BIT(0) |
| 270 | |
| 271 | #define TYPE_C_CCOUT_CONTROL_REG (TYPEC_BASE + 0x48) |
| 272 | #define TYPEC_CCOUT_SRC_BIT BIT(0) |
| 273 | |
| 274 | #define TYPE_C_EXIT_STATE_CFG_REG (TYPEC_BASE + 0x50) |
| 275 | #define EXIT_SNK_BASED_ON_CC_BIT BIT(0) |
| 276 | |
| 277 | #define TYPE_C_INTERRUPT_EN_CFG_1_REG (TYPEC_BASE + 0x5E) |
| 278 | #define TYPEC_LEGACY_CABLE_INT_EN_BIT BIT(7) |
| 279 | #define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_BIT BIT(6) |
| 280 | #define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT BIT(5) |
| 281 | #define TYPEC_TRYSINK_DETECT_INT_EN_BIT BIT(4) |
| 282 | #define TYPEC_CCOUT_DETACH_INT_EN_BIT BIT(3) |
| 283 | #define TYPEC_CCOUT_ATTACH_INT_EN_BIT BIT(2) |
| 284 | #define TYPEC_VBUS_DEASSERT_INT_EN_BIT BIT(1) |
| 285 | #define TYPEC_VBUS_ASSERT_INT_EN_BIT BIT(0) |
| 286 | |
| 287 | #define TYPE_C_INTERRUPT_EN_CFG_2_REG (TYPEC_BASE + 0x60) |
| 288 | #define TYPEC_SRC_BATT_HPWR_INT_EN_BIT BIT(6) |
| 289 | #define MICRO_USB_STATE_CHANGE_INT_EN_BIT BIT(5) |
| 290 | #define TYPEC_STATE_MACHINE_CHANGE_INT_EN_BIT BIT(4) |
| 291 | #define TYPEC_DEBUG_ACCESS_DETECT_INT_EN_BIT BIT(3) |
| 292 | #define TYPEC_WATER_DETECTION_INT_EN_BIT BIT(2) |
| 293 | #define TYPEC_VBUS_ERROR_INT_EN_BIT BIT(1) |
| 294 | #define TYPEC_DEBOUNCE_DONE_INT_EN_BIT BIT(0) |
| 295 | |
| 296 | #define TYPE_C_DEBOUNCE_OPTION_REG (TYPEC_BASE + 0x62) |
| 297 | #define REDUCE_TCCDEBOUNCE_TO_2MS_BIT BIT(2) |
| 298 | |
| 299 | #define TYPEC_U_USB_CFG_REG (TYPEC_BASE + 0x70) |
| 300 | #define EN_MICRO_USB_MODE_BIT BIT(0) |
| 301 | |
| 302 | /******************************** |
| 303 | * MISC Peripheral Registers * |
| 304 | ********************************/ |
| 305 | #define TEMP_RANGE_STATUS_REG (MISC_BASE + 0x06) |
| 306 | #define THERM_REG_ACTIVE_BIT BIT(6) |
| 307 | #define TLIM_BIT BIT(5) |
| 308 | #define TEMP_RANGE_MASK GENMASK(4, 1) |
| 309 | #define ALERT_LEVEL_BIT BIT(4) |
| 310 | #define TEMP_ABOVE_RANGE_BIT BIT(3) |
| 311 | #define TEMP_WITHIN_RANGE_BIT BIT(2) |
| 312 | #define TEMP_BELOW_RANGE_BIT BIT(1) |
| 313 | #define THERMREG_DISABLED_BIT BIT(0) |
| 314 | |
| 315 | #define BARK_BITE_WDOG_PET_REG (MISC_BASE + 0x43) |
| 316 | #define BARK_BITE_WDOG_PET_BIT BIT(0) |
| 317 | |
| 318 | #define AICL_CMD_REG (MISC_BASE + 0x44) |
| 319 | #define RERUN_AICL_BIT BIT(0) |
| 320 | |
| 321 | #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x43) |
| 322 | #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7) |
| 323 | #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) |
| 324 | #define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0) |
| 325 | |
| 326 | #define MISC_SMB_EN_CMD_REG (MISC_BASE + 0x48) |
| 327 | #define SMB_EN_OVERRIDE_VALUE_BIT BIT(4) |
| 328 | #define SMB_EN_OVERRIDE_BIT BIT(3) |
| 329 | #define EN_STAT_CMD_BIT BIT(2) |
| 330 | #define EN_CP_FPF_CMD_BIT BIT(1) |
| 331 | #define EN_CP_CMD_BIT BIT(0) |
| 332 | |
| 333 | #define WD_CFG_REG (MISC_BASE + 0x51) |
| 334 | #define WATCHDOG_TRIGGER_AFP_EN_BIT BIT(7) |
| 335 | #define BARK_WDOG_INT_EN_BIT BIT(6) |
| 336 | #define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1) |
| 337 | |
| 338 | #define MISC_SMB_CFG_REG (MISC_BASE + 0x90) |
| 339 | #define SMB_EN_SEL_BIT BIT(4) |
| 340 | #define CP_EN_POLARITY_CFG_BIT BIT(3) |
| 341 | #define STAT_POLARITY_CFG_BIT BIT(2) |
| 342 | #define STAT_FUNCTION_CFG_BIT BIT(1) |
| 343 | #define STAT_IRQ_PULSING_EN_BIT BIT(0) |
| 344 | |
| 345 | #endif /* __SMB5_CHARGER_REG_H */ |