Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1 | /* |
Pratham Pratap | 945af2a | 2018-01-24 18:29:33 +0530 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/clk.h> |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 19 | #include <linux/delay.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/power_supply.h> |
| 24 | #include <linux/regulator/consumer.h> |
| 25 | #include <linux/regulator/driver.h> |
| 26 | #include <linux/regulator/machine.h> |
| 27 | #include <linux/usb/phy.h> |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 28 | #include <linux/reset.h> |
Pratham Pratap | 945af2a | 2018-01-24 18:29:33 +0530 | [diff] [blame] | 29 | #include <linux/nvmem-consumer.h> |
Mayank Rana | 76a040f | 2017-11-20 14:10:37 -0800 | [diff] [blame] | 30 | #include <linux/debugfs.h> |
Hemant Kumar | 2bb3bdf | 2017-11-22 13:53:08 -0800 | [diff] [blame] | 31 | #include <linux/hrtimer.h> |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 32 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 33 | /* QUSB2PHY_PWR_CTRL1 register related bits */ |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 34 | #define PWR_CTRL1_POWR_DOWN BIT(0) |
| 35 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 36 | /* QUSB2PHY_PLL_COMMON_STATUS_ONE register related bits */ |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 37 | #define CORE_READY_STATUS BIT(0) |
| 38 | |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 39 | /* Get TUNE value from efuse bit-mask */ |
| 40 | #define TUNE_VAL_MASK(val, pos, mask) ((val >> pos) & mask) |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 41 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 42 | /* QUSB2PHY_INTR_CTRL register related bits */ |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 43 | #define DMSE_INTR_HIGH_SEL BIT(4) |
| 44 | #define DPSE_INTR_HIGH_SEL BIT(3) |
| 45 | #define CHG_DET_INTR_EN BIT(2) |
| 46 | #define DMSE_INTR_EN BIT(1) |
| 47 | #define DPSE_INTR_EN BIT(0) |
| 48 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 49 | /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register related bits */ |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 50 | #define CORE_PLL_RATE BIT(0) |
| 51 | #define CORE_PLL_RATE_MUX BIT(1) |
| 52 | #define CORE_PLL_EN BIT(2) |
| 53 | #define CORE_PLL_EN_MUX BIT(3) |
| 54 | #define CORE_PLL_EN_FROM_RESET BIT(4) |
| 55 | #define CORE_RESET BIT(5) |
| 56 | #define CORE_RESET_MUX BIT(6) |
| 57 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 58 | #define QUSB2PHY_1P8_VOL_MIN 1800000 /* uV */ |
| 59 | #define QUSB2PHY_1P8_VOL_MAX 1800000 /* uV */ |
| 60 | #define QUSB2PHY_1P8_HPM_LOAD 30000 /* uA */ |
| 61 | |
| 62 | #define QUSB2PHY_3P3_VOL_MIN 3075000 /* uV */ |
| 63 | #define QUSB2PHY_3P3_VOL_MAX 3200000 /* uV */ |
| 64 | #define QUSB2PHY_3P3_HPM_LOAD 30000 /* uA */ |
| 65 | |
| 66 | #define LINESTATE_DP BIT(0) |
| 67 | #define LINESTATE_DM BIT(1) |
| 68 | |
Mayank Rana | 547e24c | 2017-11-01 15:47:04 -0700 | [diff] [blame] | 69 | #define BIAS_CTRL_2_OVERRIDE_VAL 0x28 |
| 70 | |
Hemant Kumar | 91f5e54 | 2017-11-20 16:25:46 -0800 | [diff] [blame] | 71 | #define SQ_CTRL1_CHIRP_DISABLE 0x20 |
| 72 | #define SQ_CTRL2_CHIRP_DISABLE 0x80 |
| 73 | |
Mayank Rana | 547e24c | 2017-11-01 15:47:04 -0700 | [diff] [blame] | 74 | /* PERIPH_SS_PHY_REFGEN_NORTH_BG_CTRL register bits */ |
| 75 | #define BANDGAP_BYPASS BIT(0) |
| 76 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 77 | enum qusb_phy_reg { |
| 78 | PORT_TUNE1, |
| 79 | PLL_COMMON_STATUS_ONE, |
| 80 | PWR_CTRL1, |
| 81 | INTR_CTRL, |
| 82 | PLL_CORE_INPUT_OVERRIDE, |
| 83 | TEST1, |
Mayank Rana | 129111e | 2017-11-01 15:31:22 -0700 | [diff] [blame] | 84 | BIAS_CTRL_2, |
Hemant Kumar | 91f5e54 | 2017-11-20 16:25:46 -0800 | [diff] [blame] | 85 | SQ_CTRL1, |
| 86 | SQ_CTRL2, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 87 | USB2_PHY_REG_MAX, |
| 88 | }; |
| 89 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 90 | struct qusb_phy { |
| 91 | struct usb_phy phy; |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 92 | struct mutex lock; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 93 | void __iomem *base; |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 94 | void __iomem *efuse_reg; |
Mayank Rana | 547e24c | 2017-11-01 15:47:04 -0700 | [diff] [blame] | 95 | void __iomem *refgen_north_bg_reg; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 96 | |
| 97 | struct clk *ref_clk_src; |
| 98 | struct clk *ref_clk; |
| 99 | struct clk *cfg_ahb_clk; |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 100 | struct reset_control *phy_reset; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 101 | |
| 102 | struct regulator *vdd; |
| 103 | struct regulator *vdda33; |
| 104 | struct regulator *vdda18; |
| 105 | int vdd_levels[3]; /* none, low, high */ |
| 106 | int init_seq_len; |
| 107 | int *qusb_phy_init_seq; |
| 108 | int host_init_seq_len; |
| 109 | int *qusb_phy_host_init_seq; |
| 110 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 111 | unsigned int *phy_reg; |
| 112 | int qusb_phy_reg_offset_cnt; |
| 113 | |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 114 | u32 tune_val; |
| 115 | int efuse_bit_pos; |
| 116 | int efuse_num_of_bits; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 117 | |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 118 | int power_enabled_ref; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 119 | bool clocks_enabled; |
| 120 | bool cable_connected; |
| 121 | bool suspended; |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 122 | bool dpdm_enable; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 123 | |
| 124 | struct regulator_desc dpdm_rdesc; |
| 125 | struct regulator_dev *dpdm_rdev; |
| 126 | |
Hemant Kumar | 91f5e54 | 2017-11-20 16:25:46 -0800 | [diff] [blame] | 127 | u32 sq_ctrl1_default; |
| 128 | u32 sq_ctrl2_default; |
| 129 | bool chirp_disable; |
| 130 | |
Hemant Kumar | 2bb3bdf | 2017-11-22 13:53:08 -0800 | [diff] [blame] | 131 | struct pinctrl *pinctrl; |
| 132 | struct pinctrl_state *atest_usb13_suspend; |
| 133 | struct pinctrl_state *atest_usb13_active; |
| 134 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 135 | /* emulation targets specific */ |
| 136 | void __iomem *emu_phy_base; |
| 137 | bool emulation; |
| 138 | int *emu_init_seq; |
| 139 | int emu_init_seq_len; |
| 140 | int *phy_pll_reset_seq; |
| 141 | int phy_pll_reset_seq_len; |
| 142 | int *emu_dcm_reset_seq; |
| 143 | int emu_dcm_reset_seq_len; |
Mayank Rana | 76a040f | 2017-11-20 14:10:37 -0800 | [diff] [blame] | 144 | |
| 145 | /* override TUNEX registers value */ |
| 146 | struct dentry *root; |
| 147 | u8 tune[5]; |
Hemant Kumar | 2bb3bdf | 2017-11-22 13:53:08 -0800 | [diff] [blame] | 148 | |
| 149 | struct hrtimer timer; |
Pratham Pratap | 945af2a | 2018-01-24 18:29:33 +0530 | [diff] [blame] | 150 | int soc_min_rev; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 151 | }; |
| 152 | |
Pratham Pratap | 945af2a | 2018-01-24 18:29:33 +0530 | [diff] [blame] | 153 | #ifdef CONFIG_NVMEM |
| 154 | /* Parse qfprom data for deciding on errata work-arounds */ |
| 155 | static long qfprom_read(struct device *dev, const char *name) |
| 156 | { |
| 157 | struct nvmem_cell *cell; |
| 158 | ssize_t len = 0; |
| 159 | u32 *buf, val = 0; |
| 160 | long err = 0; |
| 161 | |
| 162 | cell = nvmem_cell_get(dev, name); |
| 163 | if (IS_ERR(cell)) { |
| 164 | err = PTR_ERR(cell); |
| 165 | dev_err(dev, "failed opening nvmem cell err : %ld\n", err); |
| 166 | /* If entry does not exist, then that is not an error */ |
| 167 | if (err == -ENOENT) |
| 168 | err = 0; |
| 169 | return err; |
| 170 | } |
| 171 | |
| 172 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 173 | if (IS_ERR(buf) || !len) { |
| 174 | dev_err(dev, "Failed reading nvmem cell, err: %u, bytes fetched: %zd\n", |
| 175 | *buf, len); |
| 176 | if (!IS_ERR(buf)) { |
| 177 | kfree(buf); |
| 178 | err = -EINVAL; |
| 179 | } else { |
| 180 | err = PTR_ERR(buf); |
| 181 | } |
| 182 | } else { |
| 183 | val = *buf; |
| 184 | kfree(buf); |
| 185 | } |
| 186 | |
| 187 | nvmem_cell_put(cell); |
| 188 | return err ? err : (long) val; |
| 189 | } |
| 190 | |
| 191 | /* Reads the SoC version */ |
| 192 | static int qusb_phy_get_socrev(struct device *dev, struct qusb_phy *qphy) |
| 193 | { |
| 194 | qphy->soc_min_rev = qfprom_read(dev, "minor_rev"); |
| 195 | if (qphy->soc_min_rev < 0) |
| 196 | dev_err(dev, "failed getting soc_min_rev, err : %d\n", |
| 197 | qphy->soc_min_rev); |
| 198 | |
| 199 | return qphy->soc_min_rev; |
| 200 | }; |
| 201 | #else |
| 202 | /* Reads the SoC version */ |
| 203 | static int qusb_phy_get_socrev(struct device *dev, struct qusb_phy *qphy) |
| 204 | { |
| 205 | return 0; |
| 206 | } |
| 207 | #endif |
| 208 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 209 | static void qusb_phy_enable_clocks(struct qusb_phy *qphy, bool on) |
| 210 | { |
| 211 | dev_dbg(qphy->phy.dev, "%s(): clocks_enabled:%d on:%d\n", |
| 212 | __func__, qphy->clocks_enabled, on); |
| 213 | |
| 214 | if (!qphy->clocks_enabled && on) { |
| 215 | clk_prepare_enable(qphy->ref_clk_src); |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 216 | if (qphy->ref_clk) |
| 217 | clk_prepare_enable(qphy->ref_clk); |
| 218 | |
| 219 | if (qphy->cfg_ahb_clk) |
| 220 | clk_prepare_enable(qphy->cfg_ahb_clk); |
| 221 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 222 | qphy->clocks_enabled = true; |
| 223 | } |
| 224 | |
| 225 | if (qphy->clocks_enabled && !on) { |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 226 | if (qphy->cfg_ahb_clk) |
| 227 | clk_disable_unprepare(qphy->cfg_ahb_clk); |
| 228 | |
| 229 | if (qphy->ref_clk) |
| 230 | clk_disable_unprepare(qphy->ref_clk); |
| 231 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 232 | clk_disable_unprepare(qphy->ref_clk_src); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 233 | qphy->clocks_enabled = false; |
| 234 | } |
| 235 | |
| 236 | dev_dbg(qphy->phy.dev, "%s(): clocks_enabled:%d\n", __func__, |
| 237 | qphy->clocks_enabled); |
| 238 | } |
| 239 | |
| 240 | static int qusb_phy_config_vdd(struct qusb_phy *qphy, int high) |
| 241 | { |
| 242 | int min, ret; |
| 243 | |
| 244 | min = high ? 1 : 0; /* low or none? */ |
| 245 | ret = regulator_set_voltage(qphy->vdd, qphy->vdd_levels[min], |
| 246 | qphy->vdd_levels[2]); |
| 247 | if (ret) { |
| 248 | dev_err(qphy->phy.dev, "unable to set voltage for qusb vdd\n"); |
| 249 | return ret; |
| 250 | } |
| 251 | |
| 252 | dev_dbg(qphy->phy.dev, "min_vol:%d max_vol:%d\n", |
| 253 | qphy->vdd_levels[min], qphy->vdd_levels[2]); |
| 254 | return ret; |
| 255 | } |
| 256 | |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 257 | static int qusb_phy_enable_power(struct qusb_phy *qphy, bool on) |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 258 | { |
| 259 | int ret = 0; |
| 260 | |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 261 | mutex_lock(&qphy->lock); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 262 | |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 263 | dev_dbg(qphy->phy.dev, |
| 264 | "%s:req to turn %s regulators. power_enabled_ref:%d\n", |
| 265 | __func__, on ? "on" : "off", qphy->power_enabled_ref); |
| 266 | |
| 267 | if (on && ++qphy->power_enabled_ref > 1) { |
| 268 | dev_dbg(qphy->phy.dev, "PHYs' regulators are already on\n"); |
| 269 | goto done; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 270 | } |
| 271 | |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 272 | if (!on) { |
| 273 | if (on == qphy->power_enabled_ref) { |
| 274 | dev_dbg(qphy->phy.dev, |
| 275 | "PHYs' regulators are already off\n"); |
| 276 | goto done; |
| 277 | } |
| 278 | |
| 279 | qphy->power_enabled_ref--; |
| 280 | if (!qphy->power_enabled_ref) |
| 281 | goto disable_vdda33; |
| 282 | |
| 283 | dev_dbg(qphy->phy.dev, "Skip turning off PHYs' regulators\n"); |
| 284 | goto done; |
| 285 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 286 | |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 287 | ret = qusb_phy_config_vdd(qphy, true); |
| 288 | if (ret) { |
| 289 | dev_err(qphy->phy.dev, "Unable to config VDD:%d\n", |
| 290 | ret); |
| 291 | goto err_vdd; |
| 292 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 293 | |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 294 | ret = regulator_enable(qphy->vdd); |
| 295 | if (ret) { |
| 296 | dev_err(qphy->phy.dev, "Unable to enable VDD\n"); |
| 297 | goto unconfig_vdd; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | ret = regulator_set_load(qphy->vdda18, QUSB2PHY_1P8_HPM_LOAD); |
| 301 | if (ret < 0) { |
| 302 | dev_err(qphy->phy.dev, "Unable to set HPM of vdda18:%d\n", ret); |
| 303 | goto disable_vdd; |
| 304 | } |
| 305 | |
| 306 | ret = regulator_set_voltage(qphy->vdda18, QUSB2PHY_1P8_VOL_MIN, |
| 307 | QUSB2PHY_1P8_VOL_MAX); |
| 308 | if (ret) { |
| 309 | dev_err(qphy->phy.dev, |
| 310 | "Unable to set voltage for vdda18:%d\n", ret); |
| 311 | goto put_vdda18_lpm; |
| 312 | } |
| 313 | |
| 314 | ret = regulator_enable(qphy->vdda18); |
| 315 | if (ret) { |
| 316 | dev_err(qphy->phy.dev, "Unable to enable vdda18:%d\n", ret); |
| 317 | goto unset_vdda18; |
| 318 | } |
| 319 | |
| 320 | ret = regulator_set_load(qphy->vdda33, QUSB2PHY_3P3_HPM_LOAD); |
| 321 | if (ret < 0) { |
| 322 | dev_err(qphy->phy.dev, "Unable to set HPM of vdda33:%d\n", ret); |
| 323 | goto disable_vdda18; |
| 324 | } |
| 325 | |
| 326 | ret = regulator_set_voltage(qphy->vdda33, QUSB2PHY_3P3_VOL_MIN, |
| 327 | QUSB2PHY_3P3_VOL_MAX); |
| 328 | if (ret) { |
| 329 | dev_err(qphy->phy.dev, |
| 330 | "Unable to set voltage for vdda33:%d\n", ret); |
| 331 | goto put_vdda33_lpm; |
| 332 | } |
| 333 | |
| 334 | ret = regulator_enable(qphy->vdda33); |
| 335 | if (ret) { |
| 336 | dev_err(qphy->phy.dev, "Unable to enable vdda33:%d\n", ret); |
| 337 | goto unset_vdd33; |
| 338 | } |
| 339 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 340 | pr_debug("%s(): QUSB PHY's regulators are turned ON.\n", __func__); |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 341 | |
| 342 | mutex_unlock(&qphy->lock); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 343 | return ret; |
| 344 | |
| 345 | disable_vdda33: |
| 346 | ret = regulator_disable(qphy->vdda33); |
| 347 | if (ret) |
| 348 | dev_err(qphy->phy.dev, "Unable to disable vdda33:%d\n", ret); |
| 349 | |
| 350 | unset_vdd33: |
| 351 | ret = regulator_set_voltage(qphy->vdda33, 0, QUSB2PHY_3P3_VOL_MAX); |
| 352 | if (ret) |
| 353 | dev_err(qphy->phy.dev, |
| 354 | "Unable to set (0) voltage for vdda33:%d\n", ret); |
| 355 | |
| 356 | put_vdda33_lpm: |
| 357 | ret = regulator_set_load(qphy->vdda33, 0); |
| 358 | if (ret < 0) |
| 359 | dev_err(qphy->phy.dev, "Unable to set (0) HPM of vdda33\n"); |
| 360 | |
| 361 | disable_vdda18: |
| 362 | ret = regulator_disable(qphy->vdda18); |
| 363 | if (ret) |
| 364 | dev_err(qphy->phy.dev, "Unable to disable vdda18:%d\n", ret); |
| 365 | |
| 366 | unset_vdda18: |
| 367 | ret = regulator_set_voltage(qphy->vdda18, 0, QUSB2PHY_1P8_VOL_MAX); |
| 368 | if (ret) |
| 369 | dev_err(qphy->phy.dev, |
| 370 | "Unable to set (0) voltage for vdda18:%d\n", ret); |
| 371 | |
| 372 | put_vdda18_lpm: |
| 373 | ret = regulator_set_load(qphy->vdda18, 0); |
| 374 | if (ret < 0) |
| 375 | dev_err(qphy->phy.dev, "Unable to set LPM of vdda18\n"); |
| 376 | |
| 377 | disable_vdd: |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 378 | ret = regulator_disable(qphy->vdd); |
| 379 | if (ret) |
| 380 | dev_err(qphy->phy.dev, "Unable to disable vdd:%d\n", |
| 381 | ret); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 382 | |
| 383 | unconfig_vdd: |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 384 | ret = qusb_phy_config_vdd(qphy, false); |
| 385 | if (ret) |
| 386 | dev_err(qphy->phy.dev, "Unable unconfig VDD:%d\n", |
| 387 | ret); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 388 | err_vdd: |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 389 | dev_dbg(qphy->phy.dev, "QUSB PHY's regulators are turned OFF.\n"); |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 390 | |
| 391 | /* in case of error in turning on regulators */ |
| 392 | if (qphy->power_enabled_ref) |
| 393 | qphy->power_enabled_ref--; |
| 394 | done: |
| 395 | mutex_unlock(&qphy->lock); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 396 | return ret; |
| 397 | } |
| 398 | |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 399 | static void qusb_phy_get_tune1_param(struct qusb_phy *qphy) |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 400 | { |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 401 | u8 reg; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 402 | u32 bit_mask = 1; |
| 403 | |
| 404 | pr_debug("%s(): num_of_bits:%d bit_pos:%d\n", __func__, |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 405 | qphy->efuse_num_of_bits, |
| 406 | qphy->efuse_bit_pos); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 407 | |
| 408 | /* get bit mask based on number of bits to use with efuse reg */ |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 409 | bit_mask = (bit_mask << qphy->efuse_num_of_bits) - 1; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 410 | |
| 411 | /* |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 412 | * if efuse reg is updated (i.e non-zero) then use it to program |
| 413 | * tune parameters |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 414 | */ |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 415 | qphy->tune_val = readl_relaxed(qphy->efuse_reg); |
| 416 | pr_debug("%s(): bit_mask:%d efuse based tune1 value:%d\n", |
| 417 | __func__, bit_mask, qphy->tune_val); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 418 | |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 419 | qphy->tune_val = TUNE_VAL_MASK(qphy->tune_val, |
| 420 | qphy->efuse_bit_pos, bit_mask); |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 421 | reg = readb_relaxed(qphy->base + qphy->phy_reg[PORT_TUNE1]); |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 422 | if (qphy->tune_val) { |
| 423 | reg = reg & 0x0f; |
| 424 | reg |= (qphy->tune_val << 4); |
| 425 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 426 | |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 427 | qphy->tune_val = reg; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | static void qusb_phy_write_seq(void __iomem *base, u32 *seq, int cnt, |
| 431 | unsigned long delay) |
| 432 | { |
| 433 | int i; |
| 434 | |
| 435 | pr_debug("Seq count:%d\n", cnt); |
| 436 | for (i = 0; i < cnt; i = i+2) { |
| 437 | pr_debug("write 0x%02x to 0x%02x\n", seq[i], seq[i+1]); |
| 438 | writel_relaxed(seq[i], base + seq[i+1]); |
| 439 | if (delay) |
| 440 | usleep_range(delay, (delay + 2000)); |
| 441 | } |
| 442 | } |
| 443 | |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 444 | static void qusb_phy_reset(struct qusb_phy *qphy) |
| 445 | { |
| 446 | int ret; |
| 447 | |
| 448 | ret = reset_control_assert(qphy->phy_reset); |
| 449 | if (ret) |
| 450 | dev_err(qphy->phy.dev, "%s: phy_reset assert failed\n", |
| 451 | __func__); |
| 452 | usleep_range(100, 150); |
| 453 | |
| 454 | ret = reset_control_deassert(qphy->phy_reset); |
| 455 | if (ret) |
| 456 | dev_err(qphy->phy.dev, "%s: phy_reset deassert failed\n", |
| 457 | __func__); |
| 458 | } |
| 459 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 460 | static void qusb_phy_host_init(struct usb_phy *phy) |
| 461 | { |
| 462 | u8 reg; |
| 463 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 464 | |
| 465 | dev_dbg(phy->dev, "%s\n", __func__); |
| 466 | |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 467 | qusb_phy_reset(qphy); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 468 | qusb_phy_write_seq(qphy->base, qphy->qusb_phy_host_init_seq, |
| 469 | qphy->host_init_seq_len, 0); |
| 470 | |
| 471 | /* Ensure above write is completed before turning ON ref clk */ |
| 472 | wmb(); |
| 473 | |
| 474 | /* Require to get phy pll lock successfully */ |
| 475 | usleep_range(150, 160); |
| 476 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 477 | reg = readb_relaxed(qphy->base + qphy->phy_reg[PLL_COMMON_STATUS_ONE]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 478 | dev_dbg(phy->dev, "QUSB2PHY_PLL_COMMON_STATUS_ONE:%x\n", reg); |
| 479 | if (!(reg & CORE_READY_STATUS)) { |
| 480 | dev_err(phy->dev, "QUSB PHY PLL LOCK fails:%x\n", reg); |
| 481 | WARN_ON(1); |
| 482 | } |
| 483 | } |
| 484 | |
| 485 | static int qusb_phy_init(struct usb_phy *phy) |
| 486 | { |
| 487 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
Mayank Rana | 76a040f | 2017-11-20 14:10:37 -0800 | [diff] [blame] | 488 | int ret, p_index; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 489 | u8 reg; |
| 490 | |
| 491 | dev_dbg(phy->dev, "%s\n", __func__); |
| 492 | |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 493 | ret = qusb_phy_enable_power(qphy, true); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 494 | if (ret) |
| 495 | return ret; |
| 496 | |
| 497 | qusb_phy_enable_clocks(qphy, true); |
| 498 | |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 499 | qusb_phy_reset(qphy); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 500 | if (qphy->emulation) { |
| 501 | if (qphy->emu_init_seq) |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 502 | qusb_phy_write_seq(qphy->emu_phy_base + 0x8000, |
| 503 | qphy->emu_init_seq, |
| 504 | qphy->emu_init_seq_len, 10000); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 505 | |
| 506 | if (qphy->qusb_phy_init_seq) |
| 507 | qusb_phy_write_seq(qphy->base, qphy->qusb_phy_init_seq, |
| 508 | qphy->init_seq_len, 0); |
| 509 | |
| 510 | /* Wait for 5ms as per QUSB2 RUMI sequence */ |
| 511 | usleep_range(5000, 7000); |
| 512 | |
| 513 | if (qphy->phy_pll_reset_seq) |
| 514 | qusb_phy_write_seq(qphy->base, qphy->phy_pll_reset_seq, |
| 515 | qphy->phy_pll_reset_seq_len, 10000); |
| 516 | |
| 517 | if (qphy->emu_dcm_reset_seq) |
| 518 | qusb_phy_write_seq(qphy->emu_phy_base, |
| 519 | qphy->emu_dcm_reset_seq, |
| 520 | qphy->emu_dcm_reset_seq_len, 10000); |
| 521 | |
| 522 | return 0; |
| 523 | } |
| 524 | |
| 525 | /* Disable the PHY */ |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 526 | writel_relaxed(readl_relaxed(qphy->base + qphy->phy_reg[PWR_CTRL1]) | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 527 | PWR_CTRL1_POWR_DOWN, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 528 | qphy->base + qphy->phy_reg[PWR_CTRL1]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 529 | |
| 530 | if (qphy->qusb_phy_init_seq) |
| 531 | qusb_phy_write_seq(qphy->base, qphy->qusb_phy_init_seq, |
| 532 | qphy->init_seq_len, 0); |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 533 | if (qphy->efuse_reg) { |
| 534 | if (!qphy->tune_val) |
| 535 | qusb_phy_get_tune1_param(qphy); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 536 | |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 537 | pr_debug("%s(): Programming TUNE1 parameter as:%x\n", __func__, |
| 538 | qphy->tune_val); |
| 539 | writel_relaxed(qphy->tune_val, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 540 | qphy->base + qphy->phy_reg[PORT_TUNE1]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 541 | } |
| 542 | |
Mayank Rana | 76a040f | 2017-11-20 14:10:37 -0800 | [diff] [blame] | 543 | /* if debugfs based tunex params are set, use that value. */ |
| 544 | for (p_index = 0; p_index < 5; p_index++) { |
| 545 | if (qphy->tune[p_index]) |
| 546 | writel_relaxed(qphy->tune[p_index], |
| 547 | qphy->base + qphy->phy_reg[PORT_TUNE1] + |
| 548 | (4 * p_index)); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 549 | } |
| 550 | |
Mayank Rana | 547e24c | 2017-11-01 15:47:04 -0700 | [diff] [blame] | 551 | if (qphy->refgen_north_bg_reg) |
| 552 | if (readl_relaxed(qphy->refgen_north_bg_reg) & BANDGAP_BYPASS) |
| 553 | writel_relaxed(BIAS_CTRL_2_OVERRIDE_VAL, |
| 554 | qphy->base + qphy->phy_reg[BIAS_CTRL_2]); |
| 555 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 556 | /* ensure above writes are completed before re-enabling PHY */ |
| 557 | wmb(); |
| 558 | |
| 559 | /* Enable the PHY */ |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 560 | writel_relaxed(readl_relaxed(qphy->base + qphy->phy_reg[PWR_CTRL1]) & |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 561 | ~PWR_CTRL1_POWR_DOWN, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 562 | qphy->base + qphy->phy_reg[PWR_CTRL1]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 563 | |
| 564 | /* Ensure above write is completed before turning ON ref clk */ |
| 565 | wmb(); |
| 566 | |
| 567 | /* Require to get phy pll lock successfully */ |
| 568 | usleep_range(150, 160); |
| 569 | |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 570 | reg = readb_relaxed(qphy->base + qphy->phy_reg[PLL_COMMON_STATUS_ONE]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 571 | dev_dbg(phy->dev, "QUSB2PHY_PLL_COMMON_STATUS_ONE:%x\n", reg); |
| 572 | if (!(reg & CORE_READY_STATUS)) { |
| 573 | dev_err(phy->dev, "QUSB PHY PLL LOCK fails:%x\n", reg); |
| 574 | WARN_ON(1); |
| 575 | } |
| 576 | return 0; |
| 577 | } |
| 578 | |
Hemant Kumar | 2bb3bdf | 2017-11-22 13:53:08 -0800 | [diff] [blame] | 579 | static enum hrtimer_restart qusb_dis_ext_pulldown_timer(struct hrtimer *timer) |
| 580 | { |
| 581 | struct qusb_phy *qphy = container_of(timer, struct qusb_phy, timer); |
| 582 | int ret = 0; |
| 583 | |
| 584 | if (qphy->pinctrl && qphy->atest_usb13_suspend) { |
| 585 | ret = pinctrl_select_state(qphy->pinctrl, |
| 586 | qphy->atest_usb13_suspend); |
| 587 | if (ret < 0) |
| 588 | dev_err(qphy->phy.dev, |
| 589 | "pinctrl state suspend select failed\n"); |
| 590 | } |
| 591 | |
| 592 | return HRTIMER_NORESTART; |
| 593 | } |
| 594 | |
| 595 | static void qusb_phy_enable_ext_pulldown(struct usb_phy *phy) |
| 596 | { |
| 597 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 598 | int ret = 0; |
| 599 | |
| 600 | dev_dbg(phy->dev, "%s\n", __func__); |
| 601 | |
| 602 | if (qphy->pinctrl && qphy->atest_usb13_active) { |
| 603 | ret = pinctrl_select_state(qphy->pinctrl, |
| 604 | qphy->atest_usb13_active); |
| 605 | if (ret < 0) { |
| 606 | dev_err(phy->dev, |
| 607 | "pinctrl state active select failed\n"); |
| 608 | return; |
| 609 | } |
| 610 | |
| 611 | hrtimer_start(&qphy->timer, ms_to_ktime(10), HRTIMER_MODE_REL); |
| 612 | } |
| 613 | } |
| 614 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 615 | static void qusb_phy_shutdown(struct usb_phy *phy) |
| 616 | { |
| 617 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 618 | |
| 619 | dev_dbg(phy->dev, "%s\n", __func__); |
| 620 | |
Vamsi Krishna Samavedam | 246d844 | 2017-10-17 21:15:55 -0700 | [diff] [blame] | 621 | qusb_phy_enable_power(qphy, false); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 622 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 623 | } |
| 624 | |
| 625 | static u32 qusb_phy_get_linestate(struct qusb_phy *qphy) |
| 626 | { |
| 627 | u32 linestate = 0; |
| 628 | |
| 629 | if (qphy->cable_connected) { |
| 630 | if (qphy->phy.flags & PHY_HSFS_MODE) |
| 631 | linestate |= LINESTATE_DP; |
| 632 | else if (qphy->phy.flags & PHY_LS_MODE) |
| 633 | linestate |= LINESTATE_DM; |
| 634 | } |
| 635 | return linestate; |
| 636 | } |
| 637 | |
| 638 | /** |
| 639 | * Performs QUSB2 PHY suspend/resume functionality. |
| 640 | * |
| 641 | * @uphy - usb phy pointer. |
| 642 | * @suspend - to enable suspend or not. 1 - suspend, 0 - resume |
| 643 | * |
| 644 | */ |
| 645 | static int qusb_phy_set_suspend(struct usb_phy *phy, int suspend) |
| 646 | { |
| 647 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 648 | u32 linestate = 0, intr_mask = 0; |
| 649 | |
| 650 | if (qphy->suspended && suspend) { |
| 651 | dev_dbg(phy->dev, "%s: USB PHY is already suspended\n", |
| 652 | __func__); |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | if (suspend) { |
| 657 | /* Bus suspend case */ |
| 658 | if (qphy->cable_connected || |
| 659 | (qphy->phy.flags & PHY_HOST_MODE)) { |
| 660 | /* Disable all interrupts */ |
| 661 | writel_relaxed(0x00, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 662 | qphy->base + qphy->phy_reg[INTR_CTRL]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 663 | |
| 664 | linestate = qusb_phy_get_linestate(qphy); |
| 665 | /* |
| 666 | * D+/D- interrupts are level-triggered, but we are |
| 667 | * only interested if the line state changes, so enable |
| 668 | * the high/low trigger based on current state. In |
| 669 | * other words, enable the triggers _opposite_ of what |
| 670 | * the current D+/D- levels are. |
| 671 | * e.g. if currently D+ high, D- low (HS 'J'/Suspend), |
| 672 | * configure the mask to trigger on D+ low OR D- high |
| 673 | */ |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 674 | intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 675 | if (!(linestate & LINESTATE_DP)) /* D+ low */ |
| 676 | intr_mask |= DPSE_INTR_HIGH_SEL; |
| 677 | if (!(linestate & LINESTATE_DM)) /* D- low */ |
| 678 | intr_mask |= DMSE_INTR_HIGH_SEL; |
| 679 | |
| 680 | writel_relaxed(intr_mask, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 681 | qphy->base + qphy->phy_reg[INTR_CTRL]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 682 | |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 683 | /* hold core PLL into reset */ |
| 684 | writel_relaxed(CORE_PLL_EN_FROM_RESET | |
| 685 | CORE_RESET | CORE_RESET_MUX, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 686 | qphy->base + |
| 687 | qphy->phy_reg[PLL_CORE_INPUT_OVERRIDE]); |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 688 | |
Vijayavardhan Vennapusa | 46a0144 | 2017-07-06 10:52:30 +0530 | [diff] [blame] | 689 | if (linestate & (LINESTATE_DP | LINESTATE_DM)) { |
| 690 | /* enable phy auto-resume */ |
| 691 | writel_relaxed(0x91, |
| 692 | qphy->base + qphy->phy_reg[TEST1]); |
| 693 | /* flush the previous write before next write */ |
| 694 | wmb(); |
| 695 | writel_relaxed(0x90, |
| 696 | qphy->base + qphy->phy_reg[TEST1]); |
| 697 | } |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 698 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 699 | dev_dbg(phy->dev, "%s: intr_mask = %x\n", |
| 700 | __func__, intr_mask); |
| 701 | |
| 702 | /* Makes sure that above write goes through */ |
| 703 | wmb(); |
| 704 | qusb_phy_enable_clocks(qphy, false); |
| 705 | } else { /* Cable disconnect case */ |
| 706 | /* Disable all interrupts */ |
| 707 | writel_relaxed(0x00, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 708 | qphy->base + qphy->phy_reg[INTR_CTRL]); |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 709 | qusb_phy_reset(qphy); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 710 | qusb_phy_enable_clocks(qphy, false); |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 711 | qusb_phy_enable_power(qphy, false); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 712 | } |
| 713 | qphy->suspended = true; |
| 714 | } else { |
| 715 | /* Bus resume case */ |
| 716 | if (qphy->cable_connected || |
| 717 | (qphy->phy.flags & PHY_HOST_MODE)) { |
| 718 | qusb_phy_enable_clocks(qphy, true); |
| 719 | /* Clear all interrupts on resume */ |
| 720 | writel_relaxed(0x00, |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 721 | qphy->base + qphy->phy_reg[INTR_CTRL]); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 722 | |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 723 | /* bring core PLL out of reset */ |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 724 | writel_relaxed(CORE_PLL_EN_FROM_RESET, qphy->base + |
| 725 | qphy->phy_reg[PLL_CORE_INPUT_OVERRIDE]); |
Mayank Rana | b7f212e | 2017-04-06 17:54:35 -0700 | [diff] [blame] | 726 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 727 | /* Makes sure that above write goes through */ |
| 728 | wmb(); |
| 729 | } else { /* Cable connect case */ |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 730 | qusb_phy_enable_clocks(qphy, true); |
| 731 | } |
| 732 | qphy->suspended = false; |
| 733 | } |
| 734 | |
| 735 | return 0; |
| 736 | } |
| 737 | |
| 738 | static int qusb_phy_notify_connect(struct usb_phy *phy, |
| 739 | enum usb_device_speed speed) |
| 740 | { |
| 741 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 742 | |
| 743 | qphy->cable_connected = true; |
| 744 | |
| 745 | if (qphy->qusb_phy_host_init_seq && qphy->phy.flags & PHY_HOST_MODE) |
| 746 | qusb_phy_host_init(phy); |
| 747 | |
| 748 | dev_dbg(phy->dev, "QUSB PHY: connect notification cable_connected=%d\n", |
| 749 | qphy->cable_connected); |
| 750 | return 0; |
| 751 | } |
| 752 | |
| 753 | static int qusb_phy_notify_disconnect(struct usb_phy *phy, |
| 754 | enum usb_device_speed speed) |
| 755 | { |
| 756 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 757 | |
| 758 | qphy->cable_connected = false; |
| 759 | |
| 760 | dev_dbg(phy->dev, "QUSB PHY: connect notification cable_connected=%d\n", |
| 761 | qphy->cable_connected); |
| 762 | return 0; |
| 763 | } |
| 764 | |
Hemant Kumar | 91f5e54 | 2017-11-20 16:25:46 -0800 | [diff] [blame] | 765 | static int qusb_phy_disable_chirp(struct usb_phy *phy, bool disable) |
| 766 | { |
| 767 | struct qusb_phy *qphy = container_of(phy, struct qusb_phy, phy); |
| 768 | int ret = 0; |
| 769 | |
| 770 | dev_dbg(phy->dev, "%s qphy chirp disable %d disable %d\n", __func__, |
| 771 | qphy->chirp_disable, disable); |
| 772 | |
| 773 | mutex_lock(&qphy->lock); |
| 774 | |
| 775 | if (qphy->chirp_disable == disable) { |
| 776 | ret = -EALREADY; |
| 777 | goto done; |
| 778 | } |
| 779 | |
| 780 | qphy->chirp_disable = disable; |
| 781 | |
| 782 | if (disable) { |
| 783 | qphy->sq_ctrl1_default = |
| 784 | readl_relaxed(qphy->base + qphy->phy_reg[SQ_CTRL1]); |
| 785 | qphy->sq_ctrl2_default = |
| 786 | readl_relaxed(qphy->base + qphy->phy_reg[SQ_CTRL2]); |
| 787 | |
| 788 | writel_relaxed(SQ_CTRL1_CHIRP_DISABLE, |
| 789 | qphy->base + qphy->phy_reg[SQ_CTRL1]); |
| 790 | readl_relaxed(qphy->base + qphy->phy_reg[SQ_CTRL1]); |
| 791 | |
| 792 | writel_relaxed(SQ_CTRL1_CHIRP_DISABLE, |
| 793 | qphy->base + qphy->phy_reg[SQ_CTRL2]); |
| 794 | readl_relaxed(qphy->base + qphy->phy_reg[SQ_CTRL2]); |
| 795 | |
| 796 | goto done; |
| 797 | } |
| 798 | |
| 799 | writel_relaxed(qphy->sq_ctrl1_default, |
| 800 | qphy->base + qphy->phy_reg[SQ_CTRL1]); |
| 801 | readl_relaxed(qphy->base + qphy->phy_reg[SQ_CTRL1]); |
| 802 | |
| 803 | writel_relaxed(qphy->sq_ctrl2_default, |
| 804 | qphy->base + qphy->phy_reg[SQ_CTRL2]); |
| 805 | readl_relaxed(qphy->base + qphy->phy_reg[SQ_CTRL2]); |
| 806 | done: |
| 807 | mutex_unlock(&qphy->lock); |
| 808 | return ret; |
| 809 | } |
| 810 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 811 | static int qusb_phy_dpdm_regulator_enable(struct regulator_dev *rdev) |
| 812 | { |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 813 | int ret = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 814 | struct qusb_phy *qphy = rdev_get_drvdata(rdev); |
| 815 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 816 | dev_dbg(qphy->phy.dev, "%s dpdm_enable:%d\n", |
| 817 | __func__, qphy->dpdm_enable); |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 818 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 819 | if (!qphy->dpdm_enable) { |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 820 | ret = qusb_phy_enable_power(qphy, true); |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 821 | if (ret < 0) { |
| 822 | dev_dbg(qphy->phy.dev, |
| 823 | "dpdm regulator enable failed:%d\n", ret); |
| 824 | return ret; |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 825 | } |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 826 | qphy->dpdm_enable = true; |
Vijayavardhan Vennapusa | 325577c1 | 2018-01-30 16:52:06 +0530 | [diff] [blame] | 827 | qusb_phy_reset(qphy); |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 828 | } |
| 829 | |
| 830 | return ret; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 831 | } |
| 832 | |
| 833 | static int qusb_phy_dpdm_regulator_disable(struct regulator_dev *rdev) |
| 834 | { |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 835 | int ret = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 836 | struct qusb_phy *qphy = rdev_get_drvdata(rdev); |
| 837 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 838 | dev_dbg(qphy->phy.dev, "%s dpdm_enable:%d\n", |
| 839 | __func__, qphy->dpdm_enable); |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 840 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 841 | if (qphy->dpdm_enable) { |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 842 | ret = qusb_phy_enable_power(qphy, false); |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 843 | if (ret < 0) { |
| 844 | dev_dbg(qphy->phy.dev, |
| 845 | "dpdm regulator disable failed:%d\n", ret); |
| 846 | return ret; |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 847 | } |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 848 | qphy->dpdm_enable = false; |
Mayank Rana | a69fe6c | 2016-08-09 18:04:58 -0700 | [diff] [blame] | 849 | } |
| 850 | |
| 851 | return ret; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | static int qusb_phy_dpdm_regulator_is_enabled(struct regulator_dev *rdev) |
| 855 | { |
| 856 | struct qusb_phy *qphy = rdev_get_drvdata(rdev); |
| 857 | |
Mayank Rana | dadae59 | 2017-07-21 09:03:32 -0700 | [diff] [blame] | 858 | dev_dbg(qphy->phy.dev, "%s qphy->dpdm_enable = %d\n", __func__, |
| 859 | qphy->dpdm_enable); |
| 860 | return qphy->dpdm_enable; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 861 | } |
| 862 | |
| 863 | static struct regulator_ops qusb_phy_dpdm_regulator_ops = { |
| 864 | .enable = qusb_phy_dpdm_regulator_enable, |
| 865 | .disable = qusb_phy_dpdm_regulator_disable, |
| 866 | .is_enabled = qusb_phy_dpdm_regulator_is_enabled, |
| 867 | }; |
| 868 | |
| 869 | static int qusb_phy_regulator_init(struct qusb_phy *qphy) |
| 870 | { |
| 871 | struct device *dev = qphy->phy.dev; |
| 872 | struct regulator_config cfg = {}; |
| 873 | struct regulator_init_data *init_data; |
| 874 | |
| 875 | init_data = devm_kzalloc(dev, sizeof(*init_data), GFP_KERNEL); |
| 876 | if (!init_data) |
| 877 | return -ENOMEM; |
| 878 | |
| 879 | init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_STATUS; |
| 880 | qphy->dpdm_rdesc.owner = THIS_MODULE; |
| 881 | qphy->dpdm_rdesc.type = REGULATOR_VOLTAGE; |
| 882 | qphy->dpdm_rdesc.ops = &qusb_phy_dpdm_regulator_ops; |
| 883 | qphy->dpdm_rdesc.name = kbasename(dev->of_node->full_name); |
| 884 | |
| 885 | cfg.dev = dev; |
| 886 | cfg.init_data = init_data; |
| 887 | cfg.driver_data = qphy; |
| 888 | cfg.of_node = dev->of_node; |
| 889 | |
| 890 | qphy->dpdm_rdev = devm_regulator_register(dev, &qphy->dpdm_rdesc, &cfg); |
| 891 | if (IS_ERR(qphy->dpdm_rdev)) |
| 892 | return PTR_ERR(qphy->dpdm_rdev); |
| 893 | |
| 894 | return 0; |
| 895 | } |
| 896 | |
Mayank Rana | 76a040f | 2017-11-20 14:10:37 -0800 | [diff] [blame] | 897 | static int qusb_phy_create_debugfs(struct qusb_phy *qphy) |
| 898 | { |
| 899 | struct dentry *file; |
| 900 | int ret = 0, i; |
| 901 | char name[6]; |
| 902 | |
| 903 | qphy->root = debugfs_create_dir(dev_name(qphy->phy.dev), NULL); |
| 904 | if (IS_ERR_OR_NULL(qphy->root)) { |
| 905 | dev_err(qphy->phy.dev, |
| 906 | "can't create debugfs root for %s\n", |
| 907 | dev_name(qphy->phy.dev)); |
| 908 | ret = -ENOMEM; |
| 909 | goto create_err; |
| 910 | } |
| 911 | |
| 912 | for (i = 0; i < 5; i++) { |
| 913 | snprintf(name, sizeof(name), "tune%d", (i + 1)); |
| 914 | file = debugfs_create_x8(name, 0644, qphy->root, |
| 915 | &qphy->tune[i]); |
| 916 | if (IS_ERR_OR_NULL(file)) { |
| 917 | dev_err(qphy->phy.dev, |
| 918 | "can't create debugfs entry for %s\n", name); |
| 919 | debugfs_remove_recursive(qphy->root); |
| 920 | ret = ENOMEM; |
| 921 | goto create_err; |
| 922 | } |
| 923 | } |
| 924 | |
| 925 | create_err: |
| 926 | return ret; |
| 927 | } |
| 928 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 929 | static int qusb_phy_probe(struct platform_device *pdev) |
| 930 | { |
| 931 | struct qusb_phy *qphy; |
| 932 | struct device *dev = &pdev->dev; |
| 933 | struct resource *res; |
| 934 | int ret = 0, size = 0; |
| 935 | |
| 936 | qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); |
| 937 | if (!qphy) |
| 938 | return -ENOMEM; |
| 939 | |
| 940 | qphy->phy.dev = dev; |
| 941 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 942 | "qusb_phy_base"); |
| 943 | qphy->base = devm_ioremap_resource(dev, res); |
| 944 | if (IS_ERR(qphy->base)) |
| 945 | return PTR_ERR(qphy->base); |
| 946 | |
| 947 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 948 | "emu_phy_base"); |
| 949 | if (res) { |
| 950 | qphy->emu_phy_base = devm_ioremap_resource(dev, res); |
| 951 | if (IS_ERR(qphy->emu_phy_base)) { |
| 952 | dev_dbg(dev, "couldn't ioremap emu_phy_base\n"); |
| 953 | qphy->emu_phy_base = NULL; |
| 954 | } |
| 955 | } |
| 956 | |
| 957 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 958 | "efuse_addr"); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 959 | if (res) { |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 960 | qphy->efuse_reg = devm_ioremap_nocache(dev, res->start, |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 961 | resource_size(res)); |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 962 | if (!IS_ERR_OR_NULL(qphy->efuse_reg)) { |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 963 | ret = of_property_read_u32(dev->of_node, |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 964 | "qcom,efuse-bit-pos", |
| 965 | &qphy->efuse_bit_pos); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 966 | if (!ret) { |
| 967 | ret = of_property_read_u32(dev->of_node, |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 968 | "qcom,efuse-num-bits", |
| 969 | &qphy->efuse_num_of_bits); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 970 | } |
| 971 | |
| 972 | if (ret) { |
| 973 | dev_err(dev, |
Vamsi Krishna Samavedam | f4da1dc | 2016-08-25 13:57:21 -0700 | [diff] [blame] | 974 | "DT Value for efuse is invalid.\n"); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 975 | return -EINVAL; |
| 976 | } |
| 977 | } |
| 978 | } |
| 979 | |
Mayank Rana | 547e24c | 2017-11-01 15:47:04 -0700 | [diff] [blame] | 980 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 981 | "refgen_north_bg_reg_addr"); |
| 982 | if (res) |
| 983 | qphy->refgen_north_bg_reg = devm_ioremap(dev, res->start, |
| 984 | resource_size(res)); |
| 985 | |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 986 | /* ref_clk_src is needed irrespective of SE_CLK or DIFF_CLK usage */ |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 987 | qphy->ref_clk_src = devm_clk_get(dev, "ref_clk_src"); |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 988 | if (IS_ERR(qphy->ref_clk_src)) { |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 989 | dev_dbg(dev, "clk get failed for ref_clk_src\n"); |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 990 | ret = PTR_ERR(qphy->ref_clk_src); |
| 991 | return ret; |
| 992 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 993 | |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 994 | /* ref_clk is needed only for DIFF_CLK case, hence make it optional. */ |
| 995 | if (of_property_match_string(pdev->dev.of_node, |
| 996 | "clock-names", "ref_clk") >= 0) { |
| 997 | qphy->ref_clk = devm_clk_get(dev, "ref_clk"); |
| 998 | if (IS_ERR(qphy->ref_clk)) { |
| 999 | ret = PTR_ERR(qphy->ref_clk); |
| 1000 | if (ret != -EPROBE_DEFER) |
| 1001 | dev_dbg(dev, |
| 1002 | "clk get failed for ref_clk\n"); |
| 1003 | return ret; |
| 1004 | } |
| 1005 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1006 | clk_set_rate(qphy->ref_clk, 19200000); |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 1007 | } |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1008 | |
| 1009 | if (of_property_match_string(pdev->dev.of_node, |
| 1010 | "clock-names", "cfg_ahb_clk") >= 0) { |
| 1011 | qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk"); |
| 1012 | if (IS_ERR(qphy->cfg_ahb_clk)) { |
| 1013 | ret = PTR_ERR(qphy->cfg_ahb_clk); |
| 1014 | if (ret != -EPROBE_DEFER) |
| 1015 | dev_err(dev, |
| 1016 | "clk get failed for cfg_ahb_clk ret %d\n", ret); |
| 1017 | return ret; |
| 1018 | } |
| 1019 | } |
| 1020 | |
Amit Nischal | 4d27821 | 2016-06-06 17:54:34 +0530 | [diff] [blame] | 1021 | qphy->phy_reset = devm_reset_control_get(dev, "phy_reset"); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1022 | if (IS_ERR(qphy->phy_reset)) |
| 1023 | return PTR_ERR(qphy->phy_reset); |
| 1024 | |
| 1025 | qphy->emulation = of_property_read_bool(dev->of_node, |
| 1026 | "qcom,emulation"); |
| 1027 | |
| 1028 | of_get_property(dev->of_node, "qcom,emu-init-seq", &size); |
| 1029 | if (size) { |
| 1030 | qphy->emu_init_seq = devm_kzalloc(dev, |
| 1031 | size, GFP_KERNEL); |
| 1032 | if (qphy->emu_init_seq) { |
| 1033 | qphy->emu_init_seq_len = |
| 1034 | (size / sizeof(*qphy->emu_init_seq)); |
| 1035 | if (qphy->emu_init_seq_len % 2) { |
| 1036 | dev_err(dev, "invalid emu_init_seq_len\n"); |
| 1037 | return -EINVAL; |
| 1038 | } |
| 1039 | |
| 1040 | of_property_read_u32_array(dev->of_node, |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1041 | "qcom,emu-init-seq", |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1042 | qphy->emu_init_seq, |
| 1043 | qphy->emu_init_seq_len); |
| 1044 | } else { |
| 1045 | dev_dbg(dev, |
| 1046 | "error allocating memory for emu_init_seq\n"); |
| 1047 | } |
| 1048 | } |
| 1049 | |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1050 | size = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1051 | of_get_property(dev->of_node, "qcom,phy-pll-reset-seq", &size); |
| 1052 | if (size) { |
| 1053 | qphy->phy_pll_reset_seq = devm_kzalloc(dev, |
| 1054 | size, GFP_KERNEL); |
| 1055 | if (qphy->phy_pll_reset_seq) { |
| 1056 | qphy->phy_pll_reset_seq_len = |
| 1057 | (size / sizeof(*qphy->phy_pll_reset_seq)); |
| 1058 | if (qphy->phy_pll_reset_seq_len % 2) { |
| 1059 | dev_err(dev, "invalid phy_pll_reset_seq_len\n"); |
| 1060 | return -EINVAL; |
| 1061 | } |
| 1062 | |
| 1063 | of_property_read_u32_array(dev->of_node, |
| 1064 | "qcom,phy-pll-reset-seq", |
| 1065 | qphy->phy_pll_reset_seq, |
| 1066 | qphy->phy_pll_reset_seq_len); |
| 1067 | } else { |
| 1068 | dev_dbg(dev, |
| 1069 | "error allocating memory for phy_pll_reset_seq\n"); |
| 1070 | } |
| 1071 | } |
| 1072 | |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1073 | size = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1074 | of_get_property(dev->of_node, "qcom,emu-dcm-reset-seq", &size); |
| 1075 | if (size) { |
| 1076 | qphy->emu_dcm_reset_seq = devm_kzalloc(dev, |
| 1077 | size, GFP_KERNEL); |
| 1078 | if (qphy->emu_dcm_reset_seq) { |
| 1079 | qphy->emu_dcm_reset_seq_len = |
| 1080 | (size / sizeof(*qphy->emu_dcm_reset_seq)); |
| 1081 | if (qphy->emu_dcm_reset_seq_len % 2) { |
| 1082 | dev_err(dev, "invalid emu_dcm_reset_seq_len\n"); |
| 1083 | return -EINVAL; |
| 1084 | } |
| 1085 | |
| 1086 | of_property_read_u32_array(dev->of_node, |
| 1087 | "qcom,emu-dcm-reset-seq", |
| 1088 | qphy->emu_dcm_reset_seq, |
| 1089 | qphy->emu_dcm_reset_seq_len); |
| 1090 | } else { |
| 1091 | dev_dbg(dev, |
| 1092 | "error allocating memory for emu_dcm_reset_seq\n"); |
| 1093 | } |
| 1094 | } |
| 1095 | |
Mayank Rana | 147f41d | 2016-08-12 10:07:45 -0700 | [diff] [blame] | 1096 | size = 0; |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 1097 | of_get_property(dev->of_node, "qcom,qusb-phy-reg-offset", &size); |
| 1098 | if (size) { |
| 1099 | qphy->phy_reg = devm_kzalloc(dev, size, GFP_KERNEL); |
| 1100 | if (qphy->phy_reg) { |
| 1101 | qphy->qusb_phy_reg_offset_cnt = |
| 1102 | size / sizeof(*qphy->phy_reg); |
Mayank Rana | 129111e | 2017-11-01 15:31:22 -0700 | [diff] [blame] | 1103 | if (qphy->qusb_phy_reg_offset_cnt != USB2_PHY_REG_MAX) { |
Mayank Rana | 9c6b12d | 2017-06-22 16:23:26 -0700 | [diff] [blame] | 1104 | dev_err(dev, "invalid reg offset count\n"); |
| 1105 | return -EINVAL; |
| 1106 | } |
| 1107 | |
| 1108 | of_property_read_u32_array(dev->of_node, |
| 1109 | "qcom,qusb-phy-reg-offset", |
| 1110 | qphy->phy_reg, |
| 1111 | qphy->qusb_phy_reg_offset_cnt); |
| 1112 | } else { |
| 1113 | dev_err(dev, "err mem alloc for qusb_phy_reg_offset\n"); |
| 1114 | return -ENOMEM; |
| 1115 | } |
| 1116 | } else { |
| 1117 | dev_err(dev, "err provide qcom,qmp-phy-reg-offset\n"); |
| 1118 | return -EINVAL; |
| 1119 | } |
| 1120 | |
| 1121 | size = 0; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1122 | of_get_property(dev->of_node, "qcom,qusb-phy-init-seq", &size); |
| 1123 | if (size) { |
| 1124 | qphy->qusb_phy_init_seq = devm_kzalloc(dev, |
| 1125 | size, GFP_KERNEL); |
| 1126 | if (qphy->qusb_phy_init_seq) { |
| 1127 | qphy->init_seq_len = |
| 1128 | (size / sizeof(*qphy->qusb_phy_init_seq)); |
| 1129 | if (qphy->init_seq_len % 2) { |
| 1130 | dev_err(dev, "invalid init_seq_len\n"); |
| 1131 | return -EINVAL; |
| 1132 | } |
| 1133 | |
| 1134 | of_property_read_u32_array(dev->of_node, |
| 1135 | "qcom,qusb-phy-init-seq", |
| 1136 | qphy->qusb_phy_init_seq, |
| 1137 | qphy->init_seq_len); |
| 1138 | } else { |
| 1139 | dev_err(dev, |
| 1140 | "error allocating memory for phy_init_seq\n"); |
| 1141 | } |
| 1142 | } |
| 1143 | |
| 1144 | qphy->host_init_seq_len = of_property_count_elems_of_size(dev->of_node, |
| 1145 | "qcom,qusb-phy-host-init-seq", |
| 1146 | sizeof(*qphy->qusb_phy_host_init_seq)); |
| 1147 | if (qphy->host_init_seq_len > 0) { |
| 1148 | qphy->qusb_phy_host_init_seq = devm_kcalloc(dev, |
| 1149 | qphy->host_init_seq_len, |
| 1150 | sizeof(*qphy->qusb_phy_host_init_seq), |
| 1151 | GFP_KERNEL); |
| 1152 | if (qphy->qusb_phy_host_init_seq) |
| 1153 | of_property_read_u32_array(dev->of_node, |
| 1154 | "qcom,qusb-phy-host-init-seq", |
| 1155 | qphy->qusb_phy_host_init_seq, |
| 1156 | qphy->host_init_seq_len); |
| 1157 | else |
| 1158 | return -ENOMEM; |
| 1159 | } |
| 1160 | |
| 1161 | ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level", |
| 1162 | (u32 *) qphy->vdd_levels, |
| 1163 | ARRAY_SIZE(qphy->vdd_levels)); |
| 1164 | if (ret) { |
| 1165 | dev_err(dev, "error reading qcom,vdd-voltage-level property\n"); |
| 1166 | return ret; |
| 1167 | } |
| 1168 | |
| 1169 | qphy->vdd = devm_regulator_get(dev, "vdd"); |
| 1170 | if (IS_ERR(qphy->vdd)) { |
| 1171 | dev_err(dev, "unable to get vdd supply\n"); |
| 1172 | return PTR_ERR(qphy->vdd); |
| 1173 | } |
| 1174 | |
| 1175 | qphy->vdda33 = devm_regulator_get(dev, "vdda33"); |
| 1176 | if (IS_ERR(qphy->vdda33)) { |
| 1177 | dev_err(dev, "unable to get vdda33 supply\n"); |
| 1178 | return PTR_ERR(qphy->vdda33); |
| 1179 | } |
| 1180 | |
| 1181 | qphy->vdda18 = devm_regulator_get(dev, "vdda18"); |
| 1182 | if (IS_ERR(qphy->vdda18)) { |
| 1183 | dev_err(dev, "unable to get vdda18 supply\n"); |
| 1184 | return PTR_ERR(qphy->vdda18); |
| 1185 | } |
| 1186 | |
Pratham Pratap | 945af2a | 2018-01-24 18:29:33 +0530 | [diff] [blame] | 1187 | ret = qusb_phy_get_socrev(&pdev->dev, qphy); |
| 1188 | if (ret == -EPROBE_DEFER) { |
| 1189 | dev_err(&pdev->dev, "SoC version rd: fail: defer for now\n"); |
| 1190 | return ret; |
| 1191 | } |
Hemant Kumar | 2bb3bdf | 2017-11-22 13:53:08 -0800 | [diff] [blame] | 1192 | qphy->pinctrl = devm_pinctrl_get(dev); |
| 1193 | if (IS_ERR(qphy->pinctrl)) { |
| 1194 | ret = PTR_ERR(qphy->pinctrl); |
| 1195 | if (ret == -EPROBE_DEFER) |
| 1196 | return ret; |
| 1197 | dev_err(dev, "pinctrl not available\n"); |
| 1198 | goto skip_pinctrl_config; |
| 1199 | } |
| 1200 | qphy->atest_usb13_suspend = pinctrl_lookup_state(qphy->pinctrl, |
| 1201 | "atest_usb13_suspend"); |
| 1202 | if (IS_ERR(qphy->atest_usb13_suspend)) { |
| 1203 | dev_err(dev, "pinctrl lookup atest_usb13_suspend failed\n"); |
| 1204 | goto skip_pinctrl_config; |
| 1205 | } |
| 1206 | |
| 1207 | qphy->atest_usb13_active = pinctrl_lookup_state(qphy->pinctrl, |
| 1208 | "atest_usb13_active"); |
| 1209 | if (IS_ERR(qphy->atest_usb13_active)) |
| 1210 | dev_err(dev, "pinctrl lookup atest_usb13_active failed\n"); |
| 1211 | |
| 1212 | hrtimer_init(&qphy->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
| 1213 | qphy->timer.function = qusb_dis_ext_pulldown_timer; |
| 1214 | |
| 1215 | skip_pinctrl_config: |
Hemant Kumar | 164cc1b | 2017-04-27 19:39:58 -0700 | [diff] [blame] | 1216 | mutex_init(&qphy->lock); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1217 | platform_set_drvdata(pdev, qphy); |
| 1218 | |
| 1219 | qphy->phy.label = "msm-qusb-phy-v2"; |
| 1220 | qphy->phy.init = qusb_phy_init; |
| 1221 | qphy->phy.set_suspend = qusb_phy_set_suspend; |
| 1222 | qphy->phy.shutdown = qusb_phy_shutdown; |
| 1223 | qphy->phy.type = USB_PHY_TYPE_USB2; |
| 1224 | qphy->phy.notify_connect = qusb_phy_notify_connect; |
| 1225 | qphy->phy.notify_disconnect = qusb_phy_notify_disconnect; |
Pratham Pratap | 945af2a | 2018-01-24 18:29:33 +0530 | [diff] [blame] | 1226 | |
| 1227 | /* |
| 1228 | * qusb_phy_disable_chirp is not required if soc version is |
| 1229 | * mentioned and is not base version. |
| 1230 | */ |
| 1231 | if (qphy->soc_min_rev == 0) |
| 1232 | qphy->phy.disable_chirp = qusb_phy_disable_chirp; |
| 1233 | |
Hemant Kumar | 2bb3bdf | 2017-11-22 13:53:08 -0800 | [diff] [blame] | 1234 | qphy->phy.start_port_reset = qusb_phy_enable_ext_pulldown; |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1235 | |
| 1236 | ret = usb_add_phy_dev(&qphy->phy); |
| 1237 | if (ret) |
| 1238 | return ret; |
| 1239 | |
| 1240 | ret = qusb_phy_regulator_init(qphy); |
| 1241 | if (ret) |
| 1242 | usb_remove_phy(&qphy->phy); |
| 1243 | |
Mayank Rana | 76a040f | 2017-11-20 14:10:37 -0800 | [diff] [blame] | 1244 | qusb_phy_create_debugfs(qphy); |
| 1245 | |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1246 | return ret; |
| 1247 | } |
| 1248 | |
| 1249 | static int qusb_phy_remove(struct platform_device *pdev) |
| 1250 | { |
| 1251 | struct qusb_phy *qphy = platform_get_drvdata(pdev); |
| 1252 | |
| 1253 | usb_remove_phy(&qphy->phy); |
Devdutt Patnaik | 1c03dfd | 2017-03-19 23:38:43 -0700 | [diff] [blame] | 1254 | qusb_phy_enable_clocks(qphy, false); |
Hemant Kumar | 7dc6372 | 2017-04-27 17:51:11 -0700 | [diff] [blame] | 1255 | qusb_phy_enable_power(qphy, false); |
Mayank Rana | 76a040f | 2017-11-20 14:10:37 -0800 | [diff] [blame] | 1256 | debugfs_remove_recursive(qphy->root); |
Mayank Rana | 3cb43a3 | 2016-08-02 12:10:20 -0700 | [diff] [blame] | 1257 | |
| 1258 | return 0; |
| 1259 | } |
| 1260 | |
| 1261 | static const struct of_device_id qusb_phy_id_table[] = { |
| 1262 | { .compatible = "qcom,qusb2phy-v2", }, |
| 1263 | { }, |
| 1264 | }; |
| 1265 | MODULE_DEVICE_TABLE(of, qusb_phy_id_table); |
| 1266 | |
| 1267 | static struct platform_driver qusb_phy_driver = { |
| 1268 | .probe = qusb_phy_probe, |
| 1269 | .remove = qusb_phy_remove, |
| 1270 | .driver = { |
| 1271 | .name = "msm-qusb-phy-v2", |
| 1272 | .of_match_table = of_match_ptr(qusb_phy_id_table), |
| 1273 | }, |
| 1274 | }; |
| 1275 | |
| 1276 | module_platform_driver(qusb_phy_driver); |
| 1277 | |
| 1278 | MODULE_DESCRIPTION("MSM QUSB2 PHY v2 driver"); |
| 1279 | MODULE_LICENSE("GPL v2"); |