Ajay Agarwal | 1ef6469 | 2018-01-23 19:46:25 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2009-2018, Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/device.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/err.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/ioport.h> |
| 24 | #include <linux/gpio.h> |
| 25 | #include <linux/of_gpio.h> |
| 26 | #include <linux/of_platform.h> |
| 27 | #include <linux/uaccess.h> |
| 28 | #include <linux/debugfs.h> |
| 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/pm_runtime.h> |
| 31 | #include <linux/suspend.h> |
| 32 | #include <linux/of.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/pinctrl/consumer.h> |
| 35 | #include <linux/irqchip/msm-mpm-irq.h> |
| 36 | #include <linux/pm_wakeup.h> |
| 37 | #include <linux/reset.h> |
| 38 | #include <linux/extcon.h> |
| 39 | #include <soc/qcom/scm.h> |
| 40 | |
| 41 | #include <linux/usb.h> |
| 42 | #include <linux/usb/otg.h> |
| 43 | #include <linux/usb/ulpi.h> |
| 44 | #include <linux/usb/gadget.h> |
| 45 | #include <linux/usb/hcd.h> |
| 46 | #include <linux/usb/msm_hsusb.h> |
| 47 | #include <linux/usb/msm_hsusb_hw.h> |
| 48 | #include <linux/regulator/consumer.h> |
| 49 | #include <linux/regulator/driver.h> |
| 50 | #include <linux/regulator/machine.h> |
| 51 | #include <linux/qpnp/qpnp-adc.h> |
| 52 | |
| 53 | #include <linux/msm-bus.h> |
| 54 | |
| 55 | /** |
| 56 | * Requested USB votes for BUS bandwidth |
| 57 | * |
| 58 | * USB_NO_PERF_VOTE BUS Vote for inactive USB session or disconnect |
| 59 | * USB_MAX_PERF_VOTE Maximum BUS bandwidth vote |
| 60 | * USB_MIN_PERF_VOTE Minimum BUS bandwidth vote (for some hw same as NO_PERF) |
| 61 | * |
| 62 | */ |
| 63 | enum usb_bus_vote { |
| 64 | USB_NO_PERF_VOTE = 0, |
| 65 | USB_MAX_PERF_VOTE, |
| 66 | USB_MIN_PERF_VOTE, |
| 67 | }; |
| 68 | |
| 69 | /** |
| 70 | * Supported USB modes |
| 71 | * |
| 72 | * USB_PERIPHERAL Only peripheral mode is supported. |
| 73 | * USB_HOST Only host mode is supported. |
| 74 | * USB_OTG OTG mode is supported. |
| 75 | * |
| 76 | */ |
| 77 | enum usb_mode_type { |
| 78 | USB_NONE = 0, |
| 79 | USB_PERIPHERAL, |
| 80 | USB_HOST, |
| 81 | USB_OTG, |
| 82 | }; |
| 83 | |
| 84 | /** |
| 85 | * OTG control |
| 86 | * |
| 87 | * OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host |
| 88 | * only configuration. |
| 89 | * OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY. |
| 90 | * OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware. |
| 91 | * OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs. |
| 92 | * |
| 93 | */ |
| 94 | enum otg_control_type { |
| 95 | OTG_NO_CONTROL = 0, |
| 96 | OTG_PHY_CONTROL, |
| 97 | OTG_PMIC_CONTROL, |
| 98 | OTG_USER_CONTROL, |
| 99 | }; |
| 100 | |
| 101 | /** |
| 102 | * PHY used in |
| 103 | * |
| 104 | * INVALID_PHY Unsupported PHY |
| 105 | * CI_PHY Chipidea PHY |
| 106 | * SNPS_PICO_PHY Synopsis Pico PHY |
| 107 | * SNPS_FEMTO_PHY Synopsis Femto PHY |
| 108 | * QUSB_ULPI_PHY |
| 109 | * |
| 110 | */ |
| 111 | enum msm_usb_phy_type { |
| 112 | INVALID_PHY = 0, |
| 113 | CI_PHY, /* not supported */ |
| 114 | SNPS_PICO_PHY, |
| 115 | SNPS_FEMTO_PHY, |
| 116 | QUSB_ULPI_PHY, |
| 117 | }; |
| 118 | |
| 119 | #define IDEV_CHG_MAX 1500 |
| 120 | #define IUNIT 100 |
| 121 | #define IDEV_HVDCP_CHG_MAX 1800 |
| 122 | |
| 123 | /** |
| 124 | * Used different VDDCX voltage values |
| 125 | */ |
| 126 | enum usb_vdd_value { |
| 127 | VDD_NONE = 0, |
| 128 | VDD_MIN, |
| 129 | VDD_MAX, |
| 130 | VDD_VAL_MAX, |
| 131 | }; |
| 132 | |
| 133 | /** |
| 134 | * struct msm_otg_platform_data - platform device data |
| 135 | * for msm_otg driver. |
| 136 | * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as |
| 137 | * "do not overwrite default value at this address". |
| 138 | * @vbus_power: VBUS power on/off routine.It should return result |
| 139 | * as success(zero value) or failure(non-zero value). |
| 140 | * @power_budget: VBUS power budget in mA (0 will be treated as 500mA). |
| 141 | * @mode: Supported mode (OTG/peripheral/host). |
| 142 | * @otg_control: OTG switch controlled by user/Id pin |
| 143 | * @default_mode: Default operational mode. Applicable only if |
| 144 | * OTG switch is controller by user. |
| 145 | * @pmic_id_irq: IRQ number assigned for PMIC USB ID line. |
| 146 | * @mpm_otgsessvld_int: MPM wakeup pin assigned for OTG SESSVLD |
| 147 | * interrupt. Used when .otg_control == OTG_PHY_CONTROL. |
| 148 | * @mpm_dpshv_int: MPM wakeup pin assigned for DP SHV interrupt. |
| 149 | * Used during host bus suspend. |
| 150 | * @mpm_dmshv_int: MPM wakeup pin assigned for DM SHV interrupt. |
| 151 | * Used during host bus suspend. |
| 152 | * @disable_reset_on_disconnect: perform USB PHY and LINK reset |
| 153 | * on USB cable disconnection. |
| 154 | * @pnoc_errata_fix: workaround needed for PNOC hardware bug that |
| 155 | * affects USB performance. |
| 156 | * @enable_lpm_on_suspend: Enable the USB core to go into Low |
| 157 | * Power Mode, when USB bus is suspended but cable |
| 158 | * is connected. |
| 159 | * @core_clk_always_on_workaround: Don't disable core_clk when |
| 160 | * USB enters LPM. |
| 161 | * @delay_lpm_on_disconnect: Use a delay before entering LPM |
| 162 | * upon USB cable disconnection. |
| 163 | * @enable_sec_phy: Use second HSPHY with USB2 core |
| 164 | * @bus_scale_table: parameters for bus bandwidth requirements |
| 165 | * @log2_itc: value of 2^(log2_itc-1) will be used as the |
| 166 | * interrupt threshold (ITC), when log2_itc is |
| 167 | * between 1 to 7. |
| 168 | * @l1_supported: enable link power management support. |
| 169 | * @dpdm_pulldown_added: Indicates whether pull down resistors are |
| 170 | * connected on data lines or not. |
| 171 | * @vddmin_gpio: dedictaed gpio in the platform that is used for |
| 172 | * pullup the D+ line in case of bus suspend with |
| 173 | * phy retention. |
| 174 | * @enable_ahb2ahb_bypass: Indicates whether enable AHB2AHB BYPASS |
| 175 | * mode with controller in device mode. |
| 176 | * @bool disable_retention_with_vdd_min: Indicates whether to enable |
| 177 | allowing VDDmin without putting PHY into retention. |
| 178 | * @bool enable_phy_id_pullup: Indicates whether phy id pullup is |
| 179 | enabled or not. |
| 180 | * @usb_id_gpio: Gpio used for USB ID detection. |
| 181 | * @hub_reset_gpio: Gpio used for hub reset. |
| 182 | * @switch_sel_gpio: Gpio used for controlling switch that |
| 183 | routing D+/D- from the USB HUB to the USB jack type B |
| 184 | for peripheral mode. |
| 185 | * @bool phy_dvdd_always_on: PHY DVDD is supplied by always on PMIC LDO. |
| 186 | * @bool emulation: Indicates whether we are running on emulation platform. |
| 187 | * @bool enable_streaming: Indicates whether streaming to be enabled by default. |
| 188 | * @bool enable_axi_prefetch: Indicates whether AXI Prefetch interface is used |
| 189 | for improving data performance. |
| 190 | * @bool enable_sdp_typec_current_limit: Indicates whether type-c current for |
| 191 | sdp charger to be limited. |
| 192 | * @usbeth_reset_gpio: Gpio used for external usb-to-eth reset. |
| 193 | */ |
| 194 | struct msm_otg_platform_data { |
| 195 | int *phy_init_seq; |
| 196 | int phy_init_sz; |
| 197 | int (*vbus_power)(bool on); |
| 198 | unsigned int power_budget; |
| 199 | enum usb_mode_type mode; |
| 200 | enum otg_control_type otg_control; |
| 201 | enum usb_mode_type default_mode; |
| 202 | enum msm_usb_phy_type phy_type; |
| 203 | int pmic_id_irq; |
| 204 | unsigned int mpm_otgsessvld_int; |
| 205 | unsigned int mpm_dpshv_int; |
| 206 | unsigned int mpm_dmshv_int; |
| 207 | bool disable_reset_on_disconnect; |
| 208 | bool pnoc_errata_fix; |
| 209 | bool enable_lpm_on_dev_suspend; |
| 210 | bool core_clk_always_on_workaround; |
| 211 | bool delay_lpm_on_disconnect; |
| 212 | bool dp_manual_pullup; |
| 213 | bool enable_sec_phy; |
| 214 | struct msm_bus_scale_pdata *bus_scale_table; |
| 215 | int log2_itc; |
| 216 | bool l1_supported; |
| 217 | bool dpdm_pulldown_added; |
| 218 | int vddmin_gpio; |
| 219 | bool enable_ahb2ahb_bypass; |
| 220 | bool disable_retention_with_vdd_min; |
| 221 | bool enable_phy_id_pullup; |
| 222 | int usb_id_gpio; |
| 223 | int hub_reset_gpio; |
| 224 | int usbeth_reset_gpio; |
| 225 | int switch_sel_gpio; |
| 226 | bool phy_dvdd_always_on; |
| 227 | bool emulation; |
| 228 | bool enable_streaming; |
| 229 | bool enable_axi_prefetch; |
| 230 | bool enable_sdp_typec_current_limit; |
| 231 | bool vbus_low_as_hostmode; |
| 232 | }; |
| 233 | |
| 234 | #define USB_CHG_BLOCK_ULPI 1 |
| 235 | |
| 236 | #define USB_REQUEST_5V 1 |
| 237 | #define USB_REQUEST_9V 2 |
| 238 | /** |
| 239 | * struct msm_usb_chg_info - MSM USB charger block details. |
| 240 | * @chg_block_type: The type of charger block. QSCRATCH/ULPI. |
| 241 | * @page_offset: USB charger register base may not be aligned to |
| 242 | * PAGE_SIZE. The kernel driver aligns the base |
| 243 | * address and use it for memory mapping. This |
| 244 | * page_offset is used by user space to calaculate |
| 245 | * the corret charger register base address. |
| 246 | * @length: The length of the charger register address space. |
| 247 | */ |
| 248 | struct msm_usb_chg_info { |
| 249 | uint32_t chg_block_type; |
| 250 | __kernel_off_t page_offset; |
| 251 | size_t length; |
| 252 | }; |
| 253 | |
| 254 | /* Get the MSM USB charger block information */ |
| 255 | #define MSM_USB_EXT_CHG_INFO _IOW('M', 0, struct msm_usb_chg_info) |
| 256 | |
| 257 | /* Vote against USB hardware low power mode */ |
| 258 | #define MSM_USB_EXT_CHG_BLOCK_LPM _IOW('M', 1, int) |
| 259 | |
| 260 | /* To tell kernel about voltage being voted */ |
| 261 | #define MSM_USB_EXT_CHG_VOLTAGE_INFO _IOW('M', 2, int) |
| 262 | |
| 263 | /* To tell kernel about voltage request result */ |
| 264 | #define MSM_USB_EXT_CHG_RESULT _IOW('M', 3, int) |
| 265 | |
| 266 | /* To tell kernel whether charger connected is external charger or not */ |
| 267 | #define MSM_USB_EXT_CHG_TYPE _IOW('M', 4, int) |
| 268 | |
| 269 | #define MSM_USB_BASE (motg->regs) |
| 270 | #define MSM_USB_PHY_CSR_BASE (motg->phy_csr_regs) |
| 271 | |
| 272 | #define DRIVER_NAME "msm_otg" |
| 273 | |
| 274 | #define CHG_RECHECK_DELAY (jiffies + msecs_to_jiffies(2000)) |
| 275 | #define ULPI_IO_TIMEOUT_USEC (10 * 1000) |
| 276 | #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */ |
| 277 | #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */ |
| 278 | #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */ |
| 279 | #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */ |
| 280 | |
| 281 | #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */ |
| 282 | #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */ |
| 283 | #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */ |
| 284 | #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */ |
| 285 | |
| 286 | #define USB_PHY_VDD_DIG_VOL_NONE 0 /*uV */ |
| 287 | #define USB_PHY_VDD_DIG_VOL_MIN 1045000 /* uV */ |
| 288 | #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */ |
| 289 | |
| 290 | #define USB_SUSPEND_DELAY_TIME (500 * HZ/1000) /* 500 msec */ |
| 291 | |
| 292 | #define USB_DEFAULT_SYSTEM_CLOCK 80000000 /* 80 MHz */ |
| 293 | |
| 294 | #define PM_QOS_SAMPLE_SEC 2 |
| 295 | #define PM_QOS_THRESHOLD 400 |
| 296 | |
| 297 | #define MICRO_5V 5000000 |
| 298 | #define MICRO_9V 9000000 |
| 299 | |
| 300 | #define SDP_CURRENT_UA 500000 |
| 301 | #define CDP_CURRENT_UA 1500000 |
| 302 | #define DCP_CURRENT_UA 1500000 |
| 303 | #define HVDCP_CURRENT_UA 3000000 |
| 304 | |
| 305 | enum msm_otg_phy_reg_mode { |
| 306 | USB_PHY_REG_OFF, |
| 307 | USB_PHY_REG_ON, |
| 308 | USB_PHY_REG_LPM_ON, |
| 309 | USB_PHY_REG_LPM_OFF, |
| 310 | USB_PHY_REG_3P3_ON, |
| 311 | USB_PHY_REG_3P3_OFF, |
| 312 | }; |
| 313 | |
| 314 | static char *override_phy_init; |
| 315 | module_param(override_phy_init, charp, 0644); |
| 316 | MODULE_PARM_DESC(override_phy_init, |
| 317 | "Override HSUSB PHY Init Settings"); |
| 318 | |
| 319 | unsigned int lpm_disconnect_thresh = 1000; |
| 320 | module_param(lpm_disconnect_thresh, uint, 0644); |
| 321 | MODULE_PARM_DESC(lpm_disconnect_thresh, |
| 322 | "Delay before entering LPM on USB disconnect"); |
| 323 | |
| 324 | static bool floated_charger_enable; |
| 325 | module_param(floated_charger_enable, bool, 0644); |
| 326 | MODULE_PARM_DESC(floated_charger_enable, |
| 327 | "Whether to enable floated charger"); |
| 328 | |
| 329 | /* by default debugging is enabled */ |
| 330 | static unsigned int enable_dbg_log = 1; |
| 331 | module_param(enable_dbg_log, uint, 0644); |
| 332 | MODULE_PARM_DESC(enable_dbg_log, "Debug buffer events"); |
| 333 | |
| 334 | /* Max current to be drawn for HVDCP charger */ |
| 335 | static int hvdcp_max_current = IDEV_HVDCP_CHG_MAX; |
| 336 | module_param(hvdcp_max_current, int, 0644); |
| 337 | MODULE_PARM_DESC(hvdcp_max_current, "max current drawn for HVDCP charger"); |
| 338 | |
| 339 | /* Max current to be drawn for DCP charger */ |
| 340 | static int dcp_max_current = IDEV_CHG_MAX; |
| 341 | module_param(dcp_max_current, int, 0644); |
| 342 | MODULE_PARM_DESC(dcp_max_current, "max current drawn for DCP charger"); |
| 343 | |
| 344 | static DECLARE_COMPLETION(pmic_vbus_init); |
| 345 | static struct msm_otg *the_msm_otg; |
| 346 | static bool debug_bus_voting_enabled; |
| 347 | |
| 348 | static struct regulator *hsusb_3p3; |
| 349 | static struct regulator *hsusb_1p8; |
| 350 | static struct regulator *hsusb_vdd; |
| 351 | static struct regulator *vbus_otg; |
| 352 | static struct power_supply *psy; |
| 353 | |
| 354 | static int vdd_val[VDD_VAL_MAX]; |
| 355 | static u32 bus_freqs[USB_NOC_NUM_VOTE][USB_NUM_BUS_CLOCKS] /*bimc,snoc,pcnoc*/; |
| 356 | static char bus_clkname[USB_NUM_BUS_CLOCKS][20] = {"bimc_clk", "snoc_clk", |
| 357 | "pcnoc_clk"}; |
| 358 | static bool bus_clk_rate_set; |
| 359 | |
| 360 | static void dbg_inc(unsigned int *idx) |
| 361 | { |
| 362 | *idx = (*idx + 1) & (DEBUG_MAX_MSG-1); |
| 363 | } |
| 364 | |
| 365 | static void |
| 366 | msm_otg_dbg_log_event(struct usb_phy *phy, char *event, int d1, int d2) |
| 367 | { |
| 368 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
| 369 | unsigned long flags; |
| 370 | unsigned long long t; |
| 371 | unsigned long nanosec; |
| 372 | |
| 373 | if (!enable_dbg_log) |
| 374 | return; |
| 375 | |
| 376 | write_lock_irqsave(&motg->dbg_lock, flags); |
| 377 | t = cpu_clock(smp_processor_id()); |
| 378 | nanosec = do_div(t, 1000000000)/1000; |
| 379 | scnprintf(motg->buf[motg->dbg_idx], DEBUG_MSG_LEN, |
| 380 | "[%5lu.%06lu]: %s :%d:%d", |
| 381 | (unsigned long)t, nanosec, event, d1, d2); |
| 382 | |
| 383 | motg->dbg_idx++; |
| 384 | motg->dbg_idx = motg->dbg_idx % DEBUG_MAX_MSG; |
| 385 | write_unlock_irqrestore(&motg->dbg_lock, flags); |
| 386 | } |
| 387 | |
| 388 | static int msm_hsusb_ldo_init(struct msm_otg *motg, int init) |
| 389 | { |
| 390 | int rc = 0; |
| 391 | |
| 392 | if (init) { |
| 393 | hsusb_3p3 = devm_regulator_get(motg->phy.dev, "HSUSB_3p3"); |
| 394 | if (IS_ERR(hsusb_3p3)) { |
| 395 | dev_err(motg->phy.dev, "unable to get hsusb 3p3\n"); |
| 396 | return PTR_ERR(hsusb_3p3); |
| 397 | } |
| 398 | |
| 399 | rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN, |
| 400 | USB_PHY_3P3_VOL_MAX); |
| 401 | if (rc) { |
| 402 | dev_err(motg->phy.dev, "unable to set voltage level for hsusb 3p3\n" |
| 403 | ); |
| 404 | return rc; |
| 405 | } |
| 406 | hsusb_1p8 = devm_regulator_get(motg->phy.dev, "HSUSB_1p8"); |
| 407 | if (IS_ERR(hsusb_1p8)) { |
| 408 | dev_err(motg->phy.dev, "unable to get hsusb 1p8\n"); |
| 409 | rc = PTR_ERR(hsusb_1p8); |
| 410 | goto put_3p3_lpm; |
| 411 | } |
| 412 | rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN, |
| 413 | USB_PHY_1P8_VOL_MAX); |
| 414 | if (rc) { |
| 415 | dev_err(motg->phy.dev, "unable to set voltage level for hsusb 1p8\n" |
| 416 | ); |
| 417 | goto put_1p8; |
| 418 | } |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | put_1p8: |
| 424 | regulator_set_voltage(hsusb_1p8, 0, USB_PHY_1P8_VOL_MAX); |
| 425 | put_3p3_lpm: |
| 426 | regulator_set_voltage(hsusb_3p3, 0, USB_PHY_3P3_VOL_MAX); |
| 427 | return rc; |
| 428 | } |
| 429 | |
| 430 | static int msm_hsusb_config_vddcx(int high) |
| 431 | { |
| 432 | struct msm_otg *motg = the_msm_otg; |
| 433 | int max_vol = vdd_val[VDD_MAX]; |
| 434 | int min_vol; |
| 435 | int ret; |
| 436 | |
| 437 | min_vol = vdd_val[!!high]; |
| 438 | ret = regulator_set_voltage(hsusb_vdd, min_vol, max_vol); |
| 439 | if (ret) { |
| 440 | pr_err("%s: unable to set the voltage for regulator HSUSB_VDDCX\n", |
| 441 | __func__); |
| 442 | return ret; |
| 443 | } |
| 444 | |
| 445 | pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol); |
| 446 | msm_otg_dbg_log_event(&motg->phy, "CONFIG VDDCX", min_vol, max_vol); |
| 447 | |
| 448 | return ret; |
| 449 | } |
| 450 | |
| 451 | static int msm_hsusb_ldo_enable(struct msm_otg *motg, |
| 452 | enum msm_otg_phy_reg_mode mode) |
| 453 | { |
| 454 | int ret = 0; |
| 455 | |
| 456 | if (IS_ERR(hsusb_1p8)) { |
| 457 | pr_err("%s: HSUSB_1p8 is not initialized\n", __func__); |
| 458 | return -ENODEV; |
| 459 | } |
| 460 | |
| 461 | if (IS_ERR(hsusb_3p3)) { |
| 462 | pr_err("%s: HSUSB_3p3 is not initialized\n", __func__); |
| 463 | return -ENODEV; |
| 464 | } |
| 465 | |
| 466 | switch (mode) { |
| 467 | case USB_PHY_REG_ON: |
| 468 | ret = regulator_set_load(hsusb_1p8, USB_PHY_1P8_HPM_LOAD); |
| 469 | if (ret < 0) { |
| 470 | pr_err("%s: Unable to set HPM of the regulator HSUSB_1p8\n", |
| 471 | __func__); |
| 472 | return ret; |
| 473 | } |
| 474 | |
| 475 | ret = regulator_enable(hsusb_1p8); |
| 476 | if (ret) { |
| 477 | dev_err(motg->phy.dev, "%s: unable to enable the hsusb 1p8\n", |
| 478 | __func__); |
| 479 | regulator_set_load(hsusb_1p8, 0); |
| 480 | return ret; |
| 481 | } |
| 482 | |
| 483 | /* fall through */ |
| 484 | case USB_PHY_REG_3P3_ON: |
| 485 | ret = regulator_set_load(hsusb_3p3, USB_PHY_3P3_HPM_LOAD); |
| 486 | if (ret < 0) { |
| 487 | pr_err("%s: Unable to set HPM of the regulator HSUSB_3p3\n", |
| 488 | __func__); |
| 489 | if (mode == USB_PHY_REG_ON) { |
| 490 | regulator_set_load(hsusb_1p8, 0); |
| 491 | regulator_disable(hsusb_1p8); |
| 492 | } |
| 493 | return ret; |
| 494 | } |
| 495 | |
| 496 | ret = regulator_enable(hsusb_3p3); |
| 497 | if (ret) { |
| 498 | dev_err(motg->phy.dev, "%s: unable to enable the hsusb 3p3\n", |
| 499 | __func__); |
| 500 | regulator_set_load(hsusb_3p3, 0); |
| 501 | if (mode == USB_PHY_REG_ON) { |
| 502 | regulator_set_load(hsusb_1p8, 0); |
| 503 | regulator_disable(hsusb_1p8); |
| 504 | } |
| 505 | return ret; |
| 506 | } |
| 507 | |
| 508 | break; |
| 509 | |
| 510 | case USB_PHY_REG_OFF: |
| 511 | ret = regulator_disable(hsusb_1p8); |
| 512 | if (ret) { |
| 513 | dev_err(motg->phy.dev, "%s: unable to disable the hsusb 1p8\n", |
| 514 | __func__); |
| 515 | return ret; |
| 516 | } |
| 517 | |
| 518 | ret = regulator_set_load(hsusb_1p8, 0); |
| 519 | if (ret < 0) |
| 520 | pr_err("%s: Unable to set LPM of the regulator HSUSB_1p8\n", |
| 521 | __func__); |
| 522 | |
| 523 | /* fall through */ |
| 524 | case USB_PHY_REG_3P3_OFF: |
| 525 | ret = regulator_disable(hsusb_3p3); |
| 526 | if (ret) { |
| 527 | dev_err(motg->phy.dev, "%s: unable to disable the hsusb 3p3\n", |
| 528 | __func__); |
| 529 | return ret; |
| 530 | } |
| 531 | ret = regulator_set_load(hsusb_3p3, 0); |
| 532 | if (ret < 0) |
| 533 | pr_err("%s: Unable to set LPM of the regulator HSUSB_3p3\n", |
| 534 | __func__); |
| 535 | |
| 536 | break; |
| 537 | |
| 538 | case USB_PHY_REG_LPM_ON: |
| 539 | ret = regulator_set_load(hsusb_1p8, USB_PHY_1P8_LPM_LOAD); |
| 540 | if (ret < 0) { |
| 541 | pr_err("%s: Unable to set LPM of the regulator: HSUSB_1p8\n", |
| 542 | __func__); |
| 543 | return ret; |
| 544 | } |
| 545 | |
| 546 | ret = regulator_set_load(hsusb_3p3, USB_PHY_3P3_LPM_LOAD); |
| 547 | if (ret < 0) { |
| 548 | pr_err("%s: Unable to set LPM of the regulator: HSUSB_3p3\n", |
| 549 | __func__); |
| 550 | regulator_set_load(hsusb_1p8, USB_PHY_REG_ON); |
| 551 | return ret; |
| 552 | } |
| 553 | |
| 554 | break; |
| 555 | |
| 556 | case USB_PHY_REG_LPM_OFF: |
| 557 | ret = regulator_set_load(hsusb_1p8, USB_PHY_1P8_HPM_LOAD); |
| 558 | if (ret < 0) { |
| 559 | pr_err("%s: Unable to set HPM of the regulator: HSUSB_1p8\n", |
| 560 | __func__); |
| 561 | return ret; |
| 562 | } |
| 563 | |
| 564 | ret = regulator_set_load(hsusb_3p3, USB_PHY_3P3_HPM_LOAD); |
| 565 | if (ret < 0) { |
| 566 | pr_err("%s: Unable to set HPM of the regulator: HSUSB_3p3\n", |
| 567 | __func__); |
| 568 | regulator_set_load(hsusb_1p8, USB_PHY_REG_ON); |
| 569 | return ret; |
| 570 | } |
| 571 | |
| 572 | break; |
| 573 | |
| 574 | default: |
| 575 | pr_err("%s: Unsupported mode (%d).", __func__, mode); |
| 576 | return -ENOTSUPP; |
| 577 | } |
| 578 | |
| 579 | pr_debug("%s: USB reg mode (%d) (OFF/HPM/LPM)\n", __func__, mode); |
| 580 | msm_otg_dbg_log_event(&motg->phy, "USB REG MODE", mode, ret); |
| 581 | return ret < 0 ? ret : 0; |
| 582 | } |
| 583 | |
| 584 | static int ulpi_read(struct usb_phy *phy, u32 reg) |
| 585 | { |
| 586 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
| 587 | int cnt = 0; |
| 588 | |
| 589 | if (motg->pdata->emulation) |
| 590 | return 0; |
| 591 | |
| 592 | if (motg->pdata->phy_type == QUSB_ULPI_PHY && reg > 0x3F) { |
| 593 | pr_debug("%s: ULPI vendor-specific reg 0x%02x not supported\n", |
| 594 | __func__, reg); |
| 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | /* initiate read operation */ |
| 599 | writel_relaxed(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg), |
| 600 | USB_ULPI_VIEWPORT); |
| 601 | |
| 602 | /* wait for completion */ |
| 603 | while (cnt < ULPI_IO_TIMEOUT_USEC) { |
| 604 | if (!(readl_relaxed(USB_ULPI_VIEWPORT) & ULPI_RUN)) |
| 605 | break; |
| 606 | udelay(1); |
| 607 | cnt++; |
| 608 | } |
| 609 | |
| 610 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { |
| 611 | dev_err(phy->dev, "ulpi_read: timeout %08x\n", |
| 612 | readl_relaxed(USB_ULPI_VIEWPORT)); |
| 613 | dev_err(phy->dev, "PORTSC: %08x USBCMD: %08x\n", |
| 614 | readl_relaxed(USB_PORTSC), readl_relaxed(USB_USBCMD)); |
| 615 | return -ETIMEDOUT; |
| 616 | } |
| 617 | return ULPI_DATA_READ(readl_relaxed(USB_ULPI_VIEWPORT)); |
| 618 | } |
| 619 | |
| 620 | static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
| 621 | { |
| 622 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
| 623 | int cnt = 0; |
| 624 | |
| 625 | if (motg->pdata->emulation) |
| 626 | return 0; |
| 627 | |
| 628 | if (motg->pdata->phy_type == QUSB_ULPI_PHY && reg > 0x3F) { |
| 629 | pr_debug("%s: ULPI vendor-specific reg 0x%02x not supported\n", |
| 630 | __func__, reg); |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | /* initiate write operation */ |
| 635 | writel_relaxed(ULPI_RUN | ULPI_WRITE | |
| 636 | ULPI_ADDR(reg) | ULPI_DATA(val), |
| 637 | USB_ULPI_VIEWPORT); |
| 638 | |
| 639 | /* wait for completion */ |
| 640 | while (cnt < ULPI_IO_TIMEOUT_USEC) { |
| 641 | if (!(readl_relaxed(USB_ULPI_VIEWPORT) & ULPI_RUN)) |
| 642 | break; |
| 643 | udelay(1); |
| 644 | cnt++; |
| 645 | } |
| 646 | |
| 647 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { |
| 648 | dev_err(phy->dev, "ulpi_write: timeout\n"); |
| 649 | dev_err(phy->dev, "PORTSC: %08x USBCMD: %08x\n", |
| 650 | readl_relaxed(USB_PORTSC), readl_relaxed(USB_USBCMD)); |
| 651 | return -ETIMEDOUT; |
| 652 | } |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | static struct usb_phy_io_ops msm_otg_io_ops = { |
| 657 | .read = ulpi_read, |
| 658 | .write = ulpi_write, |
| 659 | }; |
| 660 | |
| 661 | static void ulpi_init(struct msm_otg *motg) |
| 662 | { |
| 663 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 664 | int aseq[10]; |
| 665 | int *seq = NULL; |
| 666 | |
| 667 | if (override_phy_init) { |
| 668 | pr_debug("%s(): HUSB PHY Init:%s\n", __func__, |
| 669 | override_phy_init); |
| 670 | get_options(override_phy_init, ARRAY_SIZE(aseq), aseq); |
| 671 | seq = &aseq[1]; |
| 672 | } else { |
| 673 | seq = pdata->phy_init_seq; |
| 674 | } |
| 675 | |
| 676 | if (!seq) |
| 677 | return; |
| 678 | |
| 679 | while (seq[0] >= 0) { |
| 680 | if (override_phy_init) |
| 681 | pr_debug("ulpi: write 0x%02x to 0x%02x\n", |
| 682 | seq[0], seq[1]); |
| 683 | |
| 684 | dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n", |
| 685 | seq[0], seq[1]); |
| 686 | msm_otg_dbg_log_event(&motg->phy, "ULPI WRITE", seq[0], seq[1]); |
| 687 | ulpi_write(&motg->phy, seq[0], seq[1]); |
| 688 | seq += 2; |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | static int msm_otg_phy_clk_reset(struct msm_otg *motg) |
| 693 | { |
| 694 | int ret; |
| 695 | |
| 696 | if (!motg->phy_reset_clk) |
| 697 | return 0; |
| 698 | |
| 699 | if (motg->sleep_clk) |
| 700 | clk_disable_unprepare(motg->sleep_clk); |
| 701 | if (motg->phy_csr_clk) |
| 702 | clk_disable_unprepare(motg->phy_csr_clk); |
| 703 | |
| 704 | ret = reset_control_assert(motg->phy_reset); |
| 705 | if (ret) { |
| 706 | pr_err("phy_reset_clk assert failed %d\n", ret); |
| 707 | return ret; |
| 708 | } |
| 709 | /* |
| 710 | * As per databook, 10 usec delay is required between |
| 711 | * PHY POR assert and de-assert. |
| 712 | */ |
| 713 | usleep_range(10, 15); |
| 714 | ret = reset_control_deassert(motg->phy_reset); |
| 715 | if (ret) { |
| 716 | pr_err("phy_reset_clk de-assert failed %d\n", ret); |
| 717 | return ret; |
| 718 | } |
| 719 | /* |
| 720 | * As per databook, it takes 75 usec for PHY to stabilize |
| 721 | * after the reset. |
| 722 | */ |
| 723 | usleep_range(80, 100); |
| 724 | |
| 725 | if (motg->phy_csr_clk) |
| 726 | clk_prepare_enable(motg->phy_csr_clk); |
| 727 | if (motg->sleep_clk) |
| 728 | clk_prepare_enable(motg->sleep_clk); |
| 729 | |
| 730 | return 0; |
| 731 | } |
| 732 | |
| 733 | static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) |
| 734 | { |
| 735 | int ret; |
| 736 | |
| 737 | if (assert) { |
| 738 | /* Using asynchronous block reset to the hardware */ |
| 739 | dev_dbg(motg->phy.dev, "block_reset ASSERT\n"); |
| 740 | clk_disable_unprepare(motg->pclk); |
| 741 | clk_disable_unprepare(motg->core_clk); |
| 742 | ret = reset_control_assert(motg->core_reset); |
| 743 | if (ret) |
| 744 | dev_err(motg->phy.dev, "usb hs_clk assert failed\n"); |
| 745 | } else { |
| 746 | dev_dbg(motg->phy.dev, "block_reset DEASSERT\n"); |
| 747 | ret = reset_control_deassert(motg->core_reset); |
| 748 | ndelay(200); |
| 749 | ret = clk_prepare_enable(motg->core_clk); |
| 750 | WARN(ret, "USB core_clk enable failed\n"); |
| 751 | ret = clk_prepare_enable(motg->pclk); |
| 752 | WARN(ret, "USB pclk enable failed\n"); |
| 753 | if (ret) |
| 754 | dev_err(motg->phy.dev, "usb hs_clk deassert failed\n"); |
| 755 | } |
| 756 | return ret; |
| 757 | } |
| 758 | |
| 759 | static int msm_otg_phy_reset(struct msm_otg *motg) |
| 760 | { |
| 761 | u32 val; |
| 762 | int ret; |
| 763 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 764 | |
| 765 | /* |
| 766 | * AHB2AHB Bypass mode shouldn't be enable before doing |
| 767 | * async clock reset. If it is enable, disable the same. |
| 768 | */ |
| 769 | val = readl_relaxed(USB_AHBMODE); |
| 770 | if (val & AHB2AHB_BYPASS) { |
| 771 | pr_err("%s(): AHB2AHB_BYPASS SET: AHBMODE:%x\n", |
| 772 | __func__, val); |
| 773 | val &= ~AHB2AHB_BYPASS_BIT_MASK; |
| 774 | writel_relaxed(val | AHB2AHB_BYPASS_CLEAR, USB_AHBMODE); |
| 775 | pr_err("%s(): AHBMODE: %x\n", __func__, |
| 776 | readl_relaxed(USB_AHBMODE)); |
| 777 | } |
| 778 | |
| 779 | ret = msm_otg_link_clk_reset(motg, 1); |
| 780 | if (ret) |
| 781 | return ret; |
| 782 | |
| 783 | msm_otg_phy_clk_reset(motg); |
| 784 | |
| 785 | /* wait for 1ms delay as suggested in HPG. */ |
| 786 | usleep_range(1000, 1200); |
| 787 | |
| 788 | ret = msm_otg_link_clk_reset(motg, 0); |
| 789 | if (ret) |
| 790 | return ret; |
| 791 | |
| 792 | if (pdata && pdata->enable_sec_phy) |
| 793 | writel_relaxed(readl_relaxed(USB_PHY_CTRL2) | (1<<16), |
| 794 | USB_PHY_CTRL2); |
| 795 | val = readl_relaxed(USB_PORTSC) & ~PORTSC_PTS_MASK; |
| 796 | writel_relaxed(val | PORTSC_PTS_ULPI, USB_PORTSC); |
| 797 | |
| 798 | dev_info(motg->phy.dev, "phy_reset: success\n"); |
| 799 | msm_otg_dbg_log_event(&motg->phy, "PHY RESET SUCCESS", |
| 800 | motg->inputs, motg->phy.otg->state); |
| 801 | return 0; |
| 802 | } |
| 803 | |
| 804 | #define LINK_RESET_TIMEOUT_USEC (250 * 1000) |
| 805 | static int msm_otg_link_reset(struct msm_otg *motg) |
| 806 | { |
| 807 | int cnt = 0; |
| 808 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 809 | |
| 810 | writel_relaxed(USBCMD_RESET, USB_USBCMD); |
| 811 | while (cnt < LINK_RESET_TIMEOUT_USEC) { |
| 812 | if (!(readl_relaxed(USB_USBCMD) & USBCMD_RESET)) |
| 813 | break; |
| 814 | udelay(1); |
| 815 | cnt++; |
| 816 | } |
| 817 | if (cnt >= LINK_RESET_TIMEOUT_USEC) |
| 818 | return -ETIMEDOUT; |
| 819 | |
| 820 | /* select ULPI phy */ |
| 821 | writel_relaxed(0x80000000, USB_PORTSC); |
| 822 | writel_relaxed(0x0, USB_AHBBURST); |
| 823 | writel_relaxed(0x08, USB_AHBMODE); |
| 824 | |
| 825 | if (pdata && pdata->enable_sec_phy) |
| 826 | writel_relaxed(readl_relaxed(USB_PHY_CTRL2) | (1<<16), |
| 827 | USB_PHY_CTRL2); |
| 828 | return 0; |
| 829 | } |
| 830 | |
| 831 | #define QUSB2PHY_PORT_POWERDOWN 0xB4 |
| 832 | #define QUSB2PHY_PORT_UTMI_CTRL2 0xC4 |
| 833 | |
| 834 | static void msm_usb_phy_reset(struct msm_otg *motg) |
| 835 | { |
| 836 | u32 val; |
| 837 | int ret, *seq; |
| 838 | |
| 839 | switch (motg->pdata->phy_type) { |
| 840 | case SNPS_PICO_PHY: |
| 841 | /* Assert USB PHY_PON */ |
| 842 | val = readl_relaxed(motg->usb_phy_ctrl_reg); |
| 843 | val &= ~PHY_POR_BIT_MASK; |
| 844 | val |= PHY_POR_ASSERT; |
| 845 | writel_relaxed(val, motg->usb_phy_ctrl_reg); |
| 846 | |
| 847 | /* wait for minimum 10 microseconds as |
| 848 | * suggested in HPG. |
| 849 | */ |
| 850 | usleep_range(10, 15); |
| 851 | |
| 852 | /* Deassert USB PHY_PON */ |
| 853 | val = readl_relaxed(motg->usb_phy_ctrl_reg); |
| 854 | val &= ~PHY_POR_BIT_MASK; |
| 855 | val |= PHY_POR_DEASSERT; |
| 856 | writel_relaxed(val, motg->usb_phy_ctrl_reg); |
| 857 | break; |
| 858 | case QUSB_ULPI_PHY: |
| 859 | ret = reset_control_assert(motg->phy_reset); |
| 860 | if (ret) { |
| 861 | pr_err("phy_reset_clk assert failed %d\n", ret); |
| 862 | break; |
| 863 | } |
| 864 | |
| 865 | /* need to delay 10us for PHY to reset */ |
| 866 | usleep_range(10, 20); |
| 867 | |
| 868 | ret = reset_control_deassert(motg->phy_reset); |
| 869 | if (ret) { |
| 870 | pr_err("phy_reset_clk de-assert failed %d\n", ret); |
| 871 | break; |
| 872 | } |
| 873 | |
| 874 | /* Ensure that RESET operation is completed. */ |
| 875 | mb(); |
| 876 | |
| 877 | writel_relaxed(0x23, |
| 878 | motg->phy_csr_regs + QUSB2PHY_PORT_POWERDOWN); |
| 879 | writel_relaxed(0x0, |
| 880 | motg->phy_csr_regs + QUSB2PHY_PORT_UTMI_CTRL2); |
| 881 | |
| 882 | /* Program tuning parameters for PHY */ |
| 883 | seq = motg->pdata->phy_init_seq; |
| 884 | if (seq) { |
| 885 | while (seq[0] >= 0) { |
| 886 | writel_relaxed(seq[1], |
| 887 | motg->phy_csr_regs + seq[0]); |
| 888 | seq += 2; |
| 889 | } |
| 890 | } |
| 891 | |
| 892 | /* ensure above writes are completed before re-enabling PHY */ |
| 893 | wmb(); |
| 894 | writel_relaxed(0x22, |
| 895 | motg->phy_csr_regs + QUSB2PHY_PORT_POWERDOWN); |
| 896 | break; |
| 897 | case SNPS_FEMTO_PHY: |
| 898 | if (!motg->phy_por_clk) { |
| 899 | pr_err("phy_por_clk missing\n"); |
| 900 | break; |
| 901 | } |
| 902 | ret = reset_control_assert(motg->phy_por_reset); |
| 903 | if (ret) { |
| 904 | pr_err("phy_por_clk assert failed %d\n", ret); |
| 905 | break; |
| 906 | } |
| 907 | /* |
| 908 | * The Femto PHY is POR reset in the following scenarios. |
| 909 | * |
| 910 | * 1. After overriding the parameter registers. |
| 911 | * 2. Low power mode exit from PHY retention. |
| 912 | * |
| 913 | * Ensure that SIDDQ is cleared before bringing the PHY |
| 914 | * out of reset. |
| 915 | * |
| 916 | */ |
| 917 | |
| 918 | val = readb_relaxed(USB_PHY_CSR_PHY_CTRL_COMMON0); |
| 919 | val &= ~SIDDQ; |
| 920 | writeb_relaxed(val, USB_PHY_CSR_PHY_CTRL_COMMON0); |
| 921 | |
| 922 | /* |
| 923 | * As per databook, 10 usec delay is required between |
| 924 | * PHY POR assert and de-assert. |
| 925 | */ |
| 926 | usleep_range(10, 20); |
| 927 | ret = reset_control_deassert(motg->phy_por_reset); |
| 928 | if (ret) { |
| 929 | pr_err("phy_por_clk de-assert failed %d\n", ret); |
| 930 | break; |
| 931 | } |
| 932 | /* |
| 933 | * As per databook, it takes 75 usec for PHY to stabilize |
| 934 | * after the reset. |
| 935 | */ |
| 936 | usleep_range(80, 100); |
| 937 | break; |
| 938 | default: |
| 939 | break; |
| 940 | } |
| 941 | /* Ensure that RESET operation is completed. */ |
| 942 | mb(); |
| 943 | } |
| 944 | |
| 945 | static int msm_otg_reset(struct usb_phy *phy) |
| 946 | { |
| 947 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
| 948 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 949 | int ret; |
| 950 | u32 val = 0; |
| 951 | u32 ulpi_val = 0; |
| 952 | |
| 953 | msm_otg_dbg_log_event(&motg->phy, "USB RESET", phy->otg->state, |
| 954 | get_pm_runtime_counter(phy->dev)); |
| 955 | /* |
| 956 | * USB PHY and Link reset also reset the USB BAM. |
| 957 | * Thus perform reset operation only once to avoid |
| 958 | * USB BAM reset on other cases e.g. USB cable disconnections. |
| 959 | * If hardware reported error then it must be reset for recovery. |
| 960 | */ |
| 961 | if (motg->err_event_seen) |
| 962 | dev_info(phy->dev, "performing USB h/w reset for recovery\n"); |
| 963 | else if (pdata->disable_reset_on_disconnect && motg->reset_counter) |
| 964 | return 0; |
| 965 | |
| 966 | motg->reset_counter++; |
| 967 | |
| 968 | disable_irq(motg->irq); |
| 969 | if (motg->phy_irq) |
| 970 | disable_irq(motg->phy_irq); |
| 971 | |
| 972 | ret = msm_otg_phy_reset(motg); |
| 973 | if (ret) { |
| 974 | dev_err(phy->dev, "phy_reset failed\n"); |
| 975 | if (motg->phy_irq) |
| 976 | enable_irq(motg->phy_irq); |
| 977 | |
| 978 | enable_irq(motg->irq); |
| 979 | return ret; |
| 980 | } |
| 981 | |
| 982 | if (motg->phy_irq) |
| 983 | enable_irq(motg->phy_irq); |
| 984 | |
| 985 | enable_irq(motg->irq); |
| 986 | ret = msm_otg_link_reset(motg); |
| 987 | if (ret) { |
| 988 | dev_err(phy->dev, "link reset failed\n"); |
| 989 | return ret; |
| 990 | } |
| 991 | |
| 992 | msleep(100); |
| 993 | |
| 994 | /* Reset USB PHY after performing USB Link RESET */ |
| 995 | msm_usb_phy_reset(motg); |
| 996 | |
| 997 | /* Program USB PHY Override registers. */ |
| 998 | ulpi_init(motg); |
| 999 | |
| 1000 | /* |
| 1001 | * It is required to reset USB PHY after programming |
| 1002 | * the USB PHY Override registers to get the new |
| 1003 | * values into effect. |
| 1004 | */ |
| 1005 | msm_usb_phy_reset(motg); |
| 1006 | |
| 1007 | if (pdata->otg_control == OTG_PHY_CONTROL) { |
| 1008 | val = readl_relaxed(USB_OTGSC); |
| 1009 | if (pdata->mode == USB_OTG) { |
| 1010 | ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; |
| 1011 | val |= OTGSC_IDIE | OTGSC_BSVIE; |
| 1012 | } else if (pdata->mode == USB_PERIPHERAL) { |
| 1013 | ulpi_val = ULPI_INT_SESS_VALID; |
| 1014 | val |= OTGSC_BSVIE; |
| 1015 | } |
| 1016 | writel_relaxed(val, USB_OTGSC); |
| 1017 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE); |
| 1018 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); |
| 1019 | } else if (pdata->otg_control == OTG_PMIC_CONTROL) { |
| 1020 | ulpi_write(phy, OTG_COMP_DISABLE, |
| 1021 | ULPI_SET(ULPI_PWR_CLK_MNG_REG)); |
| 1022 | if (motg->phy_irq) |
| 1023 | writeb_relaxed(USB_PHY_ID_MASK, |
| 1024 | USB2_PHY_USB_PHY_INTERRUPT_MASK1); |
| 1025 | } |
| 1026 | |
| 1027 | if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED) |
| 1028 | writel_relaxed(readl_relaxed(USB_OTGSC) & ~(OTGSC_IDPU), |
| 1029 | USB_OTGSC); |
| 1030 | |
| 1031 | msm_otg_dbg_log_event(&motg->phy, "USB RESET DONE", phy->otg->state, |
| 1032 | get_pm_runtime_counter(phy->dev)); |
| 1033 | |
| 1034 | if (pdata->enable_axi_prefetch) |
| 1035 | writel_relaxed(readl_relaxed(USB_HS_APF_CTRL) | (APF_CTRL_EN), |
| 1036 | USB_HS_APF_CTRL); |
| 1037 | |
| 1038 | /* |
| 1039 | * Disable USB BAM as block reset resets USB BAM registers. |
| 1040 | */ |
| 1041 | msm_usb_bam_enable(CI_CTRL, false); |
| 1042 | |
| 1043 | return 0; |
| 1044 | } |
| 1045 | |
| 1046 | static void msm_otg_kick_sm_work(struct msm_otg *motg) |
| 1047 | { |
| 1048 | if (atomic_read(&motg->in_lpm)) |
| 1049 | motg->resume_pending = true; |
| 1050 | |
| 1051 | /* For device mode, resume now. Let pm_resume handle other cases */ |
| 1052 | if (atomic_read(&motg->pm_suspended) && |
| 1053 | motg->phy.otg->state != OTG_STATE_B_SUSPEND) { |
| 1054 | motg->sm_work_pending = true; |
| 1055 | } else if (!motg->sm_work_pending) { |
| 1056 | /* process event only if previous one is not pending */ |
| 1057 | queue_work(motg->otg_wq, &motg->sm_work); |
| 1058 | } |
| 1059 | } |
| 1060 | |
| 1061 | /* |
| 1062 | * UDC calls usb_phy_set_suspend() to notify during bus suspend/resume. |
| 1063 | * Update relevant state-machine inputs and queue sm_work. |
| 1064 | * LPM enter/exit doesn't happen directly from this routine. |
| 1065 | */ |
| 1066 | |
| 1067 | static int msm_otg_set_suspend(struct usb_phy *phy, int suspend) |
| 1068 | { |
| 1069 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
| 1070 | |
| 1071 | pr_debug("%s(%d) in %s state\n", __func__, suspend, |
| 1072 | usb_otg_state_string(phy->otg->state)); |
| 1073 | msm_otg_dbg_log_event(phy, "SET SUSPEND", suspend, phy->otg->state); |
| 1074 | |
| 1075 | if (!(motg->caps & ALLOW_LPM_ON_DEV_SUSPEND)) |
| 1076 | return 0; |
| 1077 | |
| 1078 | if (suspend) { |
| 1079 | /* called in suspend interrupt context */ |
| 1080 | pr_debug("peripheral bus suspend\n"); |
| 1081 | msm_otg_dbg_log_event(phy, "PERIPHERAL BUS SUSPEND", |
| 1082 | motg->inputs, phy->otg->state); |
| 1083 | |
| 1084 | set_bit(A_BUS_SUSPEND, &motg->inputs); |
| 1085 | } else { |
| 1086 | /* host resume or remote-wakeup */ |
| 1087 | pr_debug("peripheral bus resume\n"); |
| 1088 | msm_otg_dbg_log_event(phy, "PERIPHERAL BUS RESUME", |
| 1089 | motg->inputs, phy->otg->state); |
| 1090 | |
| 1091 | clear_bit(A_BUS_SUSPEND, &motg->inputs); |
| 1092 | } |
| 1093 | /* use kick_sm_work to handle race with pm_resume */ |
| 1094 | msm_otg_kick_sm_work(motg); |
| 1095 | |
| 1096 | return 0; |
| 1097 | } |
| 1098 | |
| 1099 | static int msm_otg_bus_freq_set(struct msm_otg *motg, enum usb_noc_mode mode) |
| 1100 | { |
| 1101 | int i, ret; |
| 1102 | long rate; |
| 1103 | |
| 1104 | for (i = 0; i < USB_NUM_BUS_CLOCKS; i++) { |
| 1105 | rate = bus_freqs[mode][i]; |
| 1106 | if (!rate) { |
| 1107 | pr_debug("%s rate not available\n", bus_clkname[i]); |
| 1108 | continue; |
| 1109 | } |
| 1110 | |
| 1111 | ret = clk_set_rate(motg->bus_clks[i], rate); |
| 1112 | if (ret) { |
| 1113 | pr_err("%s set rate failed: %d\n", bus_clkname[i], ret); |
| 1114 | return ret; |
| 1115 | } |
| 1116 | pr_debug("%s set to %lu Hz\n", bus_clkname[i], |
| 1117 | clk_get_rate(motg->bus_clks[i])); |
| 1118 | msm_otg_dbg_log_event(&motg->phy, "OTG BUS FREQ SET", i, rate); |
| 1119 | } |
| 1120 | |
| 1121 | bus_clk_rate_set = true; |
| 1122 | |
| 1123 | return 0; |
| 1124 | } |
| 1125 | |
| 1126 | static int msm_otg_bus_freq_get(struct msm_otg *motg) |
| 1127 | { |
| 1128 | struct device *dev = motg->phy.dev; |
| 1129 | struct device_node *np = dev->of_node; |
| 1130 | int len = 0, i, count = USB_NUM_BUS_CLOCKS; |
| 1131 | |
| 1132 | if (!np) |
| 1133 | return -EINVAL; |
| 1134 | |
| 1135 | /* SVS requires extra set of frequencies for perf_mode sysfs node */ |
| 1136 | if (motg->default_noc_mode == USB_NOC_SVS_VOTE) |
| 1137 | count *= 2; |
| 1138 | |
| 1139 | len = of_property_count_elems_of_size(np, "qcom,bus-clk-rate", |
| 1140 | sizeof(len)); |
| 1141 | if (!len || (len != count)) { |
| 1142 | pr_err("Invalid bus rate:%d %u\n", len, motg->default_noc_mode); |
| 1143 | return -EINVAL; |
| 1144 | } |
| 1145 | of_property_read_u32_array(np, "qcom,bus-clk-rate", bus_freqs[0], |
| 1146 | count); |
| 1147 | for (i = 0; i < USB_NUM_BUS_CLOCKS; i++) { |
| 1148 | if (bus_freqs[0][i] == 0) { |
| 1149 | motg->bus_clks[i] = NULL; |
| 1150 | pr_debug("%s not available\n", bus_clkname[i]); |
| 1151 | continue; |
| 1152 | } |
| 1153 | |
| 1154 | motg->bus_clks[i] = devm_clk_get(dev, bus_clkname[i]); |
| 1155 | if (IS_ERR(motg->bus_clks[i])) { |
| 1156 | pr_err("%s get failed\n", bus_clkname[i]); |
| 1157 | return PTR_ERR(motg->bus_clks[i]); |
| 1158 | } |
| 1159 | } |
| 1160 | return 0; |
| 1161 | } |
| 1162 | |
| 1163 | static void msm_otg_bus_clks_enable(struct msm_otg *motg) |
| 1164 | { |
| 1165 | int i; |
| 1166 | int ret; |
| 1167 | |
| 1168 | if (!bus_clk_rate_set || motg->bus_clks_enabled) |
| 1169 | return; |
| 1170 | |
| 1171 | for (i = 0; i < USB_NUM_BUS_CLOCKS; i++) { |
| 1172 | if (motg->bus_clks[i] == NULL) |
| 1173 | continue; |
| 1174 | ret = clk_prepare_enable(motg->bus_clks[i]); |
| 1175 | if (ret) { |
| 1176 | pr_err("%s enable rate failed: %d\n", bus_clkname[i], |
| 1177 | ret); |
| 1178 | goto err_clk_en; |
| 1179 | } |
| 1180 | } |
| 1181 | motg->bus_clks_enabled = true; |
| 1182 | return; |
| 1183 | err_clk_en: |
| 1184 | for (--i; i >= 0; --i) { |
| 1185 | if (motg->bus_clks[i] != NULL) |
| 1186 | clk_disable_unprepare(motg->bus_clks[i]); |
| 1187 | } |
| 1188 | } |
| 1189 | |
| 1190 | static void msm_otg_bus_clks_disable(struct msm_otg *motg) |
| 1191 | { |
| 1192 | int i; |
| 1193 | |
| 1194 | if (!bus_clk_rate_set || !motg->bus_clks_enabled) |
| 1195 | return; |
| 1196 | |
| 1197 | for (i = 0; i < USB_NUM_BUS_CLOCKS; i++) { |
| 1198 | if (motg->bus_clks[i] != NULL) |
| 1199 | clk_disable_unprepare(motg->bus_clks[i]); |
| 1200 | } |
| 1201 | motg->bus_clks_enabled = false; |
| 1202 | } |
| 1203 | |
| 1204 | static void msm_otg_bus_vote(struct msm_otg *motg, enum usb_bus_vote vote) |
| 1205 | { |
| 1206 | int ret; |
| 1207 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 1208 | |
| 1209 | msm_otg_dbg_log_event(&motg->phy, "BUS VOTE", vote, |
| 1210 | motg->phy.otg->state); |
| 1211 | /* Check if target allows min_vote to be same as no_vote */ |
| 1212 | if (pdata->bus_scale_table && |
| 1213 | vote >= pdata->bus_scale_table->num_usecases) |
| 1214 | vote = USB_NO_PERF_VOTE; |
| 1215 | |
| 1216 | if (motg->bus_perf_client) { |
| 1217 | ret = msm_bus_scale_client_update_request( |
| 1218 | motg->bus_perf_client, vote); |
| 1219 | if (ret) |
| 1220 | dev_err(motg->phy.dev, "%s: Failed to vote (%d)\n" |
| 1221 | "for bus bw %d\n", __func__, vote, ret); |
| 1222 | } |
| 1223 | |
| 1224 | if (vote == USB_MAX_PERF_VOTE) |
| 1225 | msm_otg_bus_clks_enable(motg); |
| 1226 | else |
| 1227 | msm_otg_bus_clks_disable(motg); |
| 1228 | } |
| 1229 | |
| 1230 | static void msm_otg_enable_phy_hv_int(struct msm_otg *motg) |
| 1231 | { |
| 1232 | bool bsv_id_hv_int = false; |
| 1233 | bool dp_dm_hv_int = false; |
| 1234 | u32 val; |
| 1235 | |
| 1236 | if (motg->pdata->otg_control == OTG_PHY_CONTROL || |
| 1237 | motg->phy_irq) |
| 1238 | bsv_id_hv_int = true; |
| 1239 | if (motg->host_bus_suspend || motg->device_bus_suspend) |
| 1240 | dp_dm_hv_int = true; |
| 1241 | |
| 1242 | if (!bsv_id_hv_int && !dp_dm_hv_int) |
| 1243 | return; |
| 1244 | |
| 1245 | switch (motg->pdata->phy_type) { |
| 1246 | case SNPS_PICO_PHY: |
| 1247 | val = readl_relaxed(motg->usb_phy_ctrl_reg); |
| 1248 | if (bsv_id_hv_int) |
| 1249 | val |= (PHY_IDHV_INTEN | PHY_OTGSESSVLDHV_INTEN); |
| 1250 | if (dp_dm_hv_int) |
| 1251 | val |= PHY_CLAMP_DPDMSE_EN; |
| 1252 | writel_relaxed(val, motg->usb_phy_ctrl_reg); |
| 1253 | break; |
| 1254 | case SNPS_FEMTO_PHY: |
| 1255 | if (bsv_id_hv_int) { |
| 1256 | val = readb_relaxed(USB_PHY_CSR_PHY_CTRL1); |
| 1257 | val |= ID_HV_CLAMP_EN_N; |
| 1258 | writeb_relaxed(val, USB_PHY_CSR_PHY_CTRL1); |
| 1259 | } |
| 1260 | |
| 1261 | if (dp_dm_hv_int) { |
| 1262 | val = readb_relaxed(USB_PHY_CSR_PHY_CTRL3); |
| 1263 | val |= CLAMP_MPM_DPSE_DMSE_EN_N; |
| 1264 | writeb_relaxed(val, USB_PHY_CSR_PHY_CTRL3); |
| 1265 | } |
| 1266 | break; |
| 1267 | default: |
| 1268 | break; |
| 1269 | } |
| 1270 | pr_debug("%s: bsv_id_hv = %d dp_dm_hv_int = %d\n", |
| 1271 | __func__, bsv_id_hv_int, dp_dm_hv_int); |
| 1272 | msm_otg_dbg_log_event(&motg->phy, "PHY HV INTR ENABLED", |
| 1273 | bsv_id_hv_int, dp_dm_hv_int); |
| 1274 | } |
| 1275 | |
| 1276 | static void msm_otg_disable_phy_hv_int(struct msm_otg *motg) |
| 1277 | { |
| 1278 | bool bsv_id_hv_int = false; |
| 1279 | bool dp_dm_hv_int = false; |
| 1280 | u32 val; |
| 1281 | |
| 1282 | if (motg->pdata->otg_control == OTG_PHY_CONTROL || |
| 1283 | motg->phy_irq) |
| 1284 | bsv_id_hv_int = true; |
| 1285 | if (motg->host_bus_suspend || motg->device_bus_suspend) |
| 1286 | dp_dm_hv_int = true; |
| 1287 | |
| 1288 | if (!bsv_id_hv_int && !dp_dm_hv_int) |
| 1289 | return; |
| 1290 | |
| 1291 | switch (motg->pdata->phy_type) { |
| 1292 | case SNPS_PICO_PHY: |
| 1293 | val = readl_relaxed(motg->usb_phy_ctrl_reg); |
| 1294 | if (bsv_id_hv_int) |
| 1295 | val &= ~(PHY_IDHV_INTEN | PHY_OTGSESSVLDHV_INTEN); |
| 1296 | if (dp_dm_hv_int) |
| 1297 | val &= ~PHY_CLAMP_DPDMSE_EN; |
| 1298 | writel_relaxed(val, motg->usb_phy_ctrl_reg); |
| 1299 | break; |
| 1300 | case SNPS_FEMTO_PHY: |
| 1301 | if (bsv_id_hv_int) { |
| 1302 | val = readb_relaxed(USB_PHY_CSR_PHY_CTRL1); |
| 1303 | val &= ~ID_HV_CLAMP_EN_N; |
| 1304 | writeb_relaxed(val, USB_PHY_CSR_PHY_CTRL1); |
| 1305 | } |
| 1306 | |
| 1307 | if (dp_dm_hv_int) { |
| 1308 | val = readb_relaxed(USB_PHY_CSR_PHY_CTRL3); |
| 1309 | val &= ~CLAMP_MPM_DPSE_DMSE_EN_N; |
| 1310 | writeb_relaxed(val, USB_PHY_CSR_PHY_CTRL3); |
| 1311 | } |
| 1312 | break; |
| 1313 | default: |
| 1314 | break; |
| 1315 | } |
| 1316 | pr_debug("%s: bsv_id_hv = %d dp_dm_hv_int = %d\n", |
| 1317 | __func__, bsv_id_hv_int, dp_dm_hv_int); |
| 1318 | msm_otg_dbg_log_event(&motg->phy, "PHY HV INTR DISABLED", |
| 1319 | bsv_id_hv_int, dp_dm_hv_int); |
| 1320 | } |
| 1321 | |
| 1322 | static void msm_otg_enter_phy_retention(struct msm_otg *motg) |
| 1323 | { |
| 1324 | u32 val; |
| 1325 | |
| 1326 | switch (motg->pdata->phy_type) { |
| 1327 | case SNPS_PICO_PHY: |
| 1328 | val = readl_relaxed(motg->usb_phy_ctrl_reg); |
| 1329 | val &= ~PHY_RETEN; |
| 1330 | writel_relaxed(val, motg->usb_phy_ctrl_reg); |
| 1331 | break; |
| 1332 | case SNPS_FEMTO_PHY: |
| 1333 | /* Retention is supported via SIDDQ */ |
| 1334 | val = readb_relaxed(USB_PHY_CSR_PHY_CTRL_COMMON0); |
| 1335 | val |= SIDDQ; |
| 1336 | writeb_relaxed(val, USB_PHY_CSR_PHY_CTRL_COMMON0); |
| 1337 | break; |
| 1338 | default: |
| 1339 | break; |
| 1340 | } |
| 1341 | pr_debug("USB PHY is in retention\n"); |
| 1342 | msm_otg_dbg_log_event(&motg->phy, "USB PHY ENTER RETENTION", |
| 1343 | motg->pdata->phy_type, 0); |
| 1344 | } |
| 1345 | |
| 1346 | static void msm_otg_exit_phy_retention(struct msm_otg *motg) |
| 1347 | { |
| 1348 | int val; |
| 1349 | |
| 1350 | switch (motg->pdata->phy_type) { |
| 1351 | case SNPS_PICO_PHY: |
| 1352 | val = readl_relaxed(motg->usb_phy_ctrl_reg); |
| 1353 | val |= PHY_RETEN; |
| 1354 | writel_relaxed(val, motg->usb_phy_ctrl_reg); |
| 1355 | break; |
| 1356 | case SNPS_FEMTO_PHY: |
| 1357 | /* |
| 1358 | * It is required to do USB block reset to bring Femto PHY out |
| 1359 | * of retention. |
| 1360 | */ |
| 1361 | msm_otg_reset(&motg->phy); |
| 1362 | break; |
| 1363 | default: |
| 1364 | break; |
| 1365 | } |
| 1366 | pr_debug("USB PHY is exited from retention\n"); |
| 1367 | msm_otg_dbg_log_event(&motg->phy, "USB PHY EXIT RETENTION", |
| 1368 | motg->pdata->phy_type, 0); |
| 1369 | } |
| 1370 | |
| 1371 | static void msm_id_status_w(struct work_struct *w); |
| 1372 | static irqreturn_t msm_otg_phy_irq_handler(int irq, void *data) |
| 1373 | { |
| 1374 | struct msm_otg *motg = data; |
| 1375 | |
| 1376 | msm_otg_dbg_log_event(&motg->phy, "PHY ID IRQ", |
| 1377 | atomic_read(&motg->in_lpm), motg->phy.otg->state); |
| 1378 | if (atomic_read(&motg->in_lpm)) { |
| 1379 | pr_debug("PHY ID IRQ in LPM\n"); |
| 1380 | motg->phy_irq_pending = true; |
| 1381 | msm_otg_kick_sm_work(motg); |
| 1382 | } else { |
| 1383 | pr_debug("PHY ID IRQ outside LPM\n"); |
| 1384 | msm_id_status_w(&motg->id_status_work.work); |
| 1385 | } |
| 1386 | |
| 1387 | return IRQ_HANDLED; |
| 1388 | } |
| 1389 | |
| 1390 | #define PHY_SUSPEND_TIMEOUT_USEC (5 * 1000) |
| 1391 | #define PHY_DEVICE_BUS_SUSPEND_TIMEOUT_USEC 100 |
| 1392 | #define PHY_RESUME_TIMEOUT_USEC (100 * 1000) |
| 1393 | |
| 1394 | #define PHY_SUSPEND_RETRIES_MAX 3 |
| 1395 | |
| 1396 | static void msm_otg_set_vbus_state(int online); |
| 1397 | static void msm_otg_perf_vote_update(struct msm_otg *motg, bool perf_mode); |
| 1398 | |
| 1399 | #ifdef CONFIG_PM_SLEEP |
| 1400 | static int msm_otg_suspend(struct msm_otg *motg) |
| 1401 | { |
| 1402 | struct usb_phy *phy = &motg->phy; |
| 1403 | struct usb_bus *bus = phy->otg->host; |
| 1404 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 1405 | int cnt; |
| 1406 | bool host_bus_suspend, device_bus_suspend, dcp, prop_charger; |
| 1407 | bool floated_charger, sm_work_busy; |
| 1408 | u32 cmd_val; |
| 1409 | u32 portsc, config2; |
| 1410 | u32 func_ctrl; |
| 1411 | int phcd_retry_cnt = 0, ret; |
| 1412 | unsigned int phy_suspend_timeout; |
| 1413 | |
| 1414 | cnt = 0; |
| 1415 | msm_otg_dbg_log_event(phy, "LPM ENTER START", |
| 1416 | motg->inputs, phy->otg->state); |
| 1417 | |
| 1418 | if (atomic_read(&motg->in_lpm)) |
| 1419 | return 0; |
| 1420 | |
| 1421 | cancel_delayed_work_sync(&motg->perf_vote_work); |
| 1422 | |
| 1423 | disable_irq(motg->irq); |
| 1424 | if (motg->phy_irq) |
| 1425 | disable_irq(motg->phy_irq); |
| 1426 | lpm_start: |
| 1427 | host_bus_suspend = phy->otg->host && !test_bit(ID, &motg->inputs); |
| 1428 | device_bus_suspend = phy->otg->gadget && test_bit(ID, &motg->inputs) && |
| 1429 | test_bit(A_BUS_SUSPEND, &motg->inputs) && |
| 1430 | motg->caps & ALLOW_LPM_ON_DEV_SUSPEND; |
| 1431 | |
| 1432 | if (host_bus_suspend) |
| 1433 | msm_otg_perf_vote_update(motg, false); |
| 1434 | /* |
| 1435 | * Allow putting PHY into SIDDQ with wall charger connected in |
| 1436 | * case of external charger detection. |
| 1437 | */ |
| 1438 | dcp = (motg->chg_type == USB_DCP_CHARGER) && !motg->is_ext_chg_dcp; |
| 1439 | prop_charger = motg->chg_type == USB_NONCOMPLIANT_CHARGER; |
| 1440 | floated_charger = motg->chg_type == USB_FLOATED_CHARGER; |
| 1441 | |
| 1442 | /* !BSV, but its handling is in progress by otg sm_work */ |
| 1443 | sm_work_busy = !test_bit(B_SESS_VLD, &motg->inputs) && |
| 1444 | phy->otg->state == OTG_STATE_B_PERIPHERAL; |
| 1445 | |
| 1446 | /* Perform block reset to recover from UDC error events on disconnect */ |
| 1447 | if (motg->err_event_seen) |
| 1448 | msm_otg_reset(phy); |
| 1449 | |
| 1450 | /* Enable line state difference wakeup fix for only device and host |
| 1451 | * bus suspend scenarios. Otherwise PHY can not be suspended when |
| 1452 | * a charger that pulls DP/DM high is connected. |
| 1453 | */ |
| 1454 | config2 = readl_relaxed(USB_GENCONFIG_2); |
| 1455 | if (device_bus_suspend) |
| 1456 | config2 |= GENCONFIG_2_LINESTATE_DIFF_WAKEUP_EN; |
| 1457 | else |
| 1458 | config2 &= ~GENCONFIG_2_LINESTATE_DIFF_WAKEUP_EN; |
| 1459 | writel_relaxed(config2, USB_GENCONFIG_2); |
| 1460 | |
| 1461 | /* |
| 1462 | * Abort suspend when, |
| 1463 | * 1. charging detection in progress due to cable plug-in |
| 1464 | * 2. host mode activation in progress due to Micro-A cable insertion |
| 1465 | * 3. !BSV, but its handling is in progress by otg sm_work |
| 1466 | * Don't abort suspend in case of dcp detected by PMIC |
| 1467 | */ |
| 1468 | |
| 1469 | if ((test_bit(B_SESS_VLD, &motg->inputs) && !device_bus_suspend && |
| 1470 | !dcp && !motg->is_ext_chg_dcp && !prop_charger && |
| 1471 | !floated_charger) || sm_work_busy) { |
| 1472 | msm_otg_dbg_log_event(phy, "LPM ENTER ABORTED", |
| 1473 | motg->inputs, motg->chg_type); |
| 1474 | enable_irq(motg->irq); |
| 1475 | if (motg->phy_irq) |
| 1476 | enable_irq(motg->phy_irq); |
| 1477 | return -EBUSY; |
| 1478 | } |
| 1479 | |
| 1480 | if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED) { |
| 1481 | /* put the controller in non-driving mode */ |
| 1482 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
| 1483 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
| 1484 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; |
| 1485 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
| 1486 | ulpi_write(phy, ULPI_IFC_CTRL_AUTORESUME, |
| 1487 | ULPI_CLR(ULPI_IFC_CTRL)); |
| 1488 | } |
| 1489 | |
| 1490 | /* |
| 1491 | * PHY suspend sequence as mentioned in the databook. |
| 1492 | * |
| 1493 | * Device bus suspend: The controller may abort PHY suspend if |
| 1494 | * there is an incoming reset or resume from the host. If PHCD |
| 1495 | * is not set within 100 usec. Abort the LPM sequence. |
| 1496 | * |
| 1497 | * Host bus suspend: If the peripheral is attached, PHY is already |
| 1498 | * put into suspend along with the peripheral bus suspend. poll for |
| 1499 | * PHCD upto 5 msec. If the peripheral is not attached i.e entering |
| 1500 | * LPM with Micro-A cable, set the PHCD and poll for it for 5 msec. |
| 1501 | * |
| 1502 | * No cable connected: Set the PHCD to suspend the PHY. Poll for PHCD |
| 1503 | * upto 5 msec. |
| 1504 | * |
| 1505 | * The controller aborts PHY suspend only in device bus suspend case. |
| 1506 | * In other cases, it is observed that PHCD may not get set within |
| 1507 | * the timeout. If so, set the PHCD again and poll for it before |
| 1508 | * reset recovery. |
| 1509 | */ |
| 1510 | |
| 1511 | phcd_retry: |
| 1512 | if (device_bus_suspend) |
| 1513 | phy_suspend_timeout = PHY_DEVICE_BUS_SUSPEND_TIMEOUT_USEC; |
| 1514 | else |
| 1515 | phy_suspend_timeout = PHY_SUSPEND_TIMEOUT_USEC; |
| 1516 | |
| 1517 | cnt = 0; |
| 1518 | portsc = readl_relaxed(USB_PORTSC); |
| 1519 | if (!(portsc & PORTSC_PHCD)) { |
| 1520 | writel_relaxed(portsc | PORTSC_PHCD, |
| 1521 | USB_PORTSC); |
| 1522 | while (cnt < phy_suspend_timeout) { |
| 1523 | if (readl_relaxed(USB_PORTSC) & PORTSC_PHCD) |
| 1524 | break; |
| 1525 | udelay(1); |
| 1526 | cnt++; |
| 1527 | } |
| 1528 | } |
| 1529 | |
| 1530 | if (cnt >= phy_suspend_timeout) { |
| 1531 | if (phcd_retry_cnt > PHY_SUSPEND_RETRIES_MAX) { |
| 1532 | msm_otg_dbg_log_event(phy, "PHY SUSPEND FAILED", |
| 1533 | phcd_retry_cnt, phy->otg->state); |
| 1534 | dev_err(phy->dev, "PHY suspend failed\n"); |
| 1535 | ret = -EBUSY; |
| 1536 | goto phy_suspend_fail; |
| 1537 | } |
| 1538 | |
| 1539 | if (device_bus_suspend) { |
| 1540 | dev_dbg(phy->dev, "PHY suspend aborted\n"); |
| 1541 | ret = -EBUSY; |
| 1542 | goto phy_suspend_fail; |
| 1543 | } else { |
| 1544 | if (phcd_retry_cnt++ < PHY_SUSPEND_RETRIES_MAX) { |
| 1545 | dev_dbg(phy->dev, "PHY suspend retry\n"); |
| 1546 | goto phcd_retry; |
| 1547 | } else { |
| 1548 | dev_err(phy->dev, "reset attempt during PHY suspend\n"); |
| 1549 | phcd_retry_cnt++; |
| 1550 | motg->reset_counter = 0; |
| 1551 | msm_otg_reset(phy); |
| 1552 | goto lpm_start; |
| 1553 | } |
| 1554 | } |
| 1555 | } |
| 1556 | |
| 1557 | /* |
| 1558 | * PHY has capability to generate interrupt asynchronously in low |
| 1559 | * power mode (LPM). This interrupt is level triggered. So USB IRQ |
| 1560 | * line must be disabled till async interrupt enable bit is cleared |
| 1561 | * in USBCMD register. Assert STP (ULPI interface STOP signal) to |
| 1562 | * block data communication from PHY. |
| 1563 | * |
| 1564 | * PHY retention mode is disallowed while entering to LPM with wall |
| 1565 | * charger connected. But PHY is put into suspend mode. Hence |
| 1566 | * enable asynchronous interrupt to detect charger disconnection when |
| 1567 | * PMIC notifications are unavailable. |
| 1568 | */ |
| 1569 | cmd_val = readl_relaxed(USB_USBCMD); |
| 1570 | if (host_bus_suspend || device_bus_suspend || |
| 1571 | (motg->pdata->otg_control == OTG_PHY_CONTROL)) |
| 1572 | cmd_val |= ASYNC_INTR_CTRL | ULPI_STP_CTRL; |
| 1573 | else |
| 1574 | cmd_val |= ULPI_STP_CTRL; |
| 1575 | writel_relaxed(cmd_val, USB_USBCMD); |
| 1576 | |
| 1577 | /* |
| 1578 | * BC1.2 spec mandates PD to enable VDP_SRC when charging from DCP. |
| 1579 | * PHY retention and collapse can not happen with VDP_SRC enabled. |
| 1580 | */ |
| 1581 | |
| 1582 | |
| 1583 | /* |
| 1584 | * We come here in 3 scenarios. |
| 1585 | * |
| 1586 | * (1) No cable connected (out of session): |
| 1587 | * - BSV/ID HV interrupts are enabled for PHY based detection. |
| 1588 | * - PHY is put in retention. |
| 1589 | * - If allowed (PMIC based detection), PHY is power collapsed. |
| 1590 | * - DVDD (CX/MX) minimization and XO shutdown are allowed. |
| 1591 | * - The wakeup is through VBUS/ID interrupt from PHY/PMIC/user. |
| 1592 | * (2) USB wall charger: |
| 1593 | * - BSV/ID HV interrupts are enabled for PHY based detection. |
| 1594 | * - For BC1.2 compliant charger, retention is not allowed to |
| 1595 | * keep VDP_SRC on. XO shutdown is allowed. |
| 1596 | * - The wakeup is through VBUS/ID interrupt from PHY/PMIC/user. |
| 1597 | * (3) Device/Host Bus suspend (if LPM is enabled): |
| 1598 | * - BSV/ID HV interrupts are enabled for PHY based detection. |
| 1599 | * - D+/D- MPM pin are configured to wakeup from line state |
| 1600 | * change through PHY HV interrupts. PHY HV interrupts are |
| 1601 | * also enabled. If MPM pins are not available, retention and |
| 1602 | * XO is not allowed. |
| 1603 | * - PHY is put into retention only if a gpio is used to keep |
| 1604 | * the D+ pull-up. ALLOW_BUS_SUSPEND_WITHOUT_REWORK capability |
| 1605 | * is set means, PHY can enable D+ pull-up or D+/D- pull-down |
| 1606 | * without any re-work and PHY should not be put into retention. |
| 1607 | * - DVDD (CX/MX) minimization and XO shutdown is allowed if |
| 1608 | * ALLOW_BUS_SUSPEND_WITHOUT_REWORK is set (PHY DVDD is supplied |
| 1609 | * via PMIC LDO) or board level re-work is present. |
| 1610 | * - The wakeup is through VBUS/ID interrupt from PHY/PMIC/user |
| 1611 | * or USB link asynchronous interrupt for line state change. |
| 1612 | * |
| 1613 | */ |
| 1614 | motg->host_bus_suspend = host_bus_suspend; |
| 1615 | motg->device_bus_suspend = device_bus_suspend; |
| 1616 | |
| 1617 | if (motg->caps & ALLOW_PHY_RETENTION && !device_bus_suspend && !dcp && |
| 1618 | (!host_bus_suspend || (motg->caps & |
| 1619 | ALLOW_BUS_SUSPEND_WITHOUT_REWORK) || |
| 1620 | ((motg->caps & ALLOW_HOST_PHY_RETENTION) |
| 1621 | && (pdata->dpdm_pulldown_added || !(portsc & PORTSC_CCS))))) { |
| 1622 | msm_otg_enable_phy_hv_int(motg); |
| 1623 | if ((!host_bus_suspend || !(motg->caps & |
| 1624 | ALLOW_BUS_SUSPEND_WITHOUT_REWORK)) && |
| 1625 | !(motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) { |
| 1626 | msm_otg_enter_phy_retention(motg); |
| 1627 | motg->lpm_flags |= PHY_RETENTIONED; |
| 1628 | } |
| 1629 | } else if (device_bus_suspend && !dcp && |
| 1630 | (pdata->mpm_dpshv_int || pdata->mpm_dmshv_int)) { |
| 1631 | /* DP DM HV interrupts are used for bus resume from XO off */ |
| 1632 | msm_otg_enable_phy_hv_int(motg); |
| 1633 | if (motg->caps & ALLOW_PHY_RETENTION && pdata->vddmin_gpio) { |
| 1634 | |
| 1635 | /* |
| 1636 | * This is HW WA needed when PHY_CLAMP_DPDMSE_EN is |
| 1637 | * enabled and we put the phy in retention mode. |
| 1638 | * Without this WA, the async_irq will be fired right |
| 1639 | * after suspending whithout any bus resume. |
| 1640 | */ |
| 1641 | config2 = readl_relaxed(USB_GENCONFIG_2); |
| 1642 | config2 &= ~GENCONFIG_2_DPSE_DMSE_HV_INTR_EN; |
| 1643 | writel_relaxed(config2, USB_GENCONFIG_2); |
| 1644 | |
| 1645 | msm_otg_enter_phy_retention(motg); |
| 1646 | motg->lpm_flags |= PHY_RETENTIONED; |
| 1647 | gpio_direction_output(pdata->vddmin_gpio, 1); |
| 1648 | } |
| 1649 | } |
| 1650 | |
| 1651 | /* Ensure that above operation is completed before turning off clocks */ |
| 1652 | mb(); |
| 1653 | /* Consider clocks on workaround flag only in case of bus suspend */ |
| 1654 | if (!(phy->otg->state == OTG_STATE_B_PERIPHERAL && |
| 1655 | test_bit(A_BUS_SUSPEND, &motg->inputs)) || |
| 1656 | !motg->pdata->core_clk_always_on_workaround) { |
| 1657 | clk_disable_unprepare(motg->pclk); |
| 1658 | clk_disable_unprepare(motg->core_clk); |
| 1659 | if (motg->phy_csr_clk) |
| 1660 | clk_disable_unprepare(motg->phy_csr_clk); |
| 1661 | motg->lpm_flags |= CLOCKS_DOWN; |
| 1662 | } |
| 1663 | |
| 1664 | /* usb phy no more require TCXO clock, hence vote for TCXO disable */ |
| 1665 | if (!host_bus_suspend || (motg->caps & |
| 1666 | ALLOW_BUS_SUSPEND_WITHOUT_REWORK) || |
| 1667 | ((motg->caps & ALLOW_HOST_PHY_RETENTION) && |
| 1668 | (pdata->dpdm_pulldown_added || !(portsc & PORTSC_CCS)))) { |
| 1669 | if (motg->xo_clk) { |
| 1670 | clk_disable_unprepare(motg->xo_clk); |
| 1671 | motg->lpm_flags |= XO_SHUTDOWN; |
| 1672 | } |
| 1673 | } |
| 1674 | |
| 1675 | if (motg->caps & ALLOW_PHY_POWER_COLLAPSE && |
| 1676 | !host_bus_suspend && !dcp && !device_bus_suspend) { |
| 1677 | msm_hsusb_ldo_enable(motg, USB_PHY_REG_OFF); |
| 1678 | motg->lpm_flags |= PHY_PWR_COLLAPSED; |
| 1679 | } else if (motg->caps & ALLOW_PHY_REGULATORS_LPM && |
| 1680 | !host_bus_suspend && !device_bus_suspend && !dcp) { |
| 1681 | msm_hsusb_ldo_enable(motg, USB_PHY_REG_LPM_ON); |
| 1682 | motg->lpm_flags |= PHY_REGULATORS_LPM; |
| 1683 | } |
| 1684 | |
| 1685 | if (motg->lpm_flags & PHY_RETENTIONED || |
| 1686 | (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) { |
| 1687 | regulator_disable(hsusb_vdd); |
| 1688 | msm_hsusb_config_vddcx(0); |
| 1689 | } |
| 1690 | |
| 1691 | if (device_may_wakeup(phy->dev)) { |
| 1692 | if (host_bus_suspend || device_bus_suspend) { |
| 1693 | enable_irq_wake(motg->async_irq); |
| 1694 | enable_irq_wake(motg->irq); |
| 1695 | } |
| 1696 | |
| 1697 | if (motg->phy_irq) |
| 1698 | enable_irq_wake(motg->phy_irq); |
| 1699 | if (motg->pdata->pmic_id_irq) |
| 1700 | enable_irq_wake(motg->pdata->pmic_id_irq); |
| 1701 | if (motg->ext_id_irq) |
| 1702 | enable_irq_wake(motg->ext_id_irq); |
| 1703 | if (pdata->otg_control == OTG_PHY_CONTROL && |
| 1704 | pdata->mpm_otgsessvld_int) |
| 1705 | msm_mpm_set_pin_wake(pdata->mpm_otgsessvld_int, 1); |
| 1706 | if ((host_bus_suspend || device_bus_suspend) && |
| 1707 | pdata->mpm_dpshv_int) |
| 1708 | msm_mpm_set_pin_wake(pdata->mpm_dpshv_int, 1); |
| 1709 | if ((host_bus_suspend || device_bus_suspend) && |
| 1710 | pdata->mpm_dmshv_int) |
| 1711 | msm_mpm_set_pin_wake(pdata->mpm_dmshv_int, 1); |
| 1712 | } |
| 1713 | if (bus) |
| 1714 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); |
| 1715 | |
| 1716 | msm_otg_bus_vote(motg, USB_NO_PERF_VOTE); |
| 1717 | |
| 1718 | atomic_set(&motg->in_lpm, 1); |
| 1719 | |
| 1720 | /* Enable ASYNC IRQ during LPM */ |
| 1721 | enable_irq(motg->async_irq); |
| 1722 | if (motg->phy_irq) |
| 1723 | enable_irq(motg->phy_irq); |
| 1724 | |
| 1725 | enable_irq(motg->irq); |
| 1726 | pm_relax(&motg->pdev->dev); |
| 1727 | |
| 1728 | dev_dbg(phy->dev, "LPM caps = %lu flags = %lu\n", |
| 1729 | motg->caps, motg->lpm_flags); |
| 1730 | dev_info(phy->dev, "USB in low power mode\n"); |
| 1731 | msm_otg_dbg_log_event(phy, "LPM ENTER DONE", |
| 1732 | motg->caps, motg->lpm_flags); |
| 1733 | |
| 1734 | if (motg->err_event_seen) { |
| 1735 | motg->err_event_seen = false; |
| 1736 | if (motg->vbus_state != test_bit(B_SESS_VLD, &motg->inputs)) |
| 1737 | msm_otg_set_vbus_state(motg->vbus_state); |
| 1738 | if (motg->id_state != test_bit(ID, &motg->inputs)) |
| 1739 | msm_id_status_w(&motg->id_status_work.work); |
| 1740 | } |
| 1741 | |
| 1742 | return 0; |
| 1743 | |
| 1744 | phy_suspend_fail: |
| 1745 | enable_irq(motg->irq); |
| 1746 | if (motg->phy_irq) |
| 1747 | enable_irq(motg->phy_irq); |
| 1748 | return ret; |
| 1749 | } |
| 1750 | |
| 1751 | static int msm_otg_resume(struct msm_otg *motg) |
| 1752 | { |
| 1753 | struct usb_phy *phy = &motg->phy; |
| 1754 | struct usb_bus *bus = phy->otg->host; |
| 1755 | struct usb_hcd *hcd = bus_to_hcd(phy->otg->host); |
| 1756 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 1757 | int cnt = 0; |
| 1758 | unsigned int temp; |
| 1759 | unsigned int ret; |
| 1760 | u32 func_ctrl; |
| 1761 | |
| 1762 | msm_otg_dbg_log_event(phy, "LPM EXIT START", motg->inputs, |
| 1763 | phy->otg->state); |
| 1764 | if (!atomic_read(&motg->in_lpm)) { |
| 1765 | msm_otg_dbg_log_event(phy, "USB NOT IN LPM", |
| 1766 | atomic_read(&motg->in_lpm), phy->otg->state); |
| 1767 | return 0; |
| 1768 | } |
| 1769 | |
| 1770 | disable_irq(motg->irq); |
| 1771 | pm_stay_awake(&motg->pdev->dev); |
| 1772 | |
| 1773 | /* |
| 1774 | * If we are resuming from the device bus suspend, restore |
| 1775 | * the max performance bus vote. Otherwise put a minimum |
| 1776 | * bus vote to satisfy the requirement for enabling clocks. |
| 1777 | */ |
| 1778 | |
| 1779 | if (motg->device_bus_suspend && debug_bus_voting_enabled) |
| 1780 | msm_otg_bus_vote(motg, USB_MAX_PERF_VOTE); |
| 1781 | else |
| 1782 | msm_otg_bus_vote(motg, USB_MIN_PERF_VOTE); |
| 1783 | |
| 1784 | /* Vote for TCXO when waking up the phy */ |
| 1785 | if (motg->lpm_flags & XO_SHUTDOWN) { |
| 1786 | if (motg->xo_clk) |
| 1787 | clk_prepare_enable(motg->xo_clk); |
| 1788 | motg->lpm_flags &= ~XO_SHUTDOWN; |
| 1789 | } |
| 1790 | |
| 1791 | if (motg->lpm_flags & CLOCKS_DOWN) { |
| 1792 | if (motg->phy_csr_clk) { |
| 1793 | ret = clk_prepare_enable(motg->phy_csr_clk); |
| 1794 | WARN(ret, "USB phy_csr_clk enable failed\n"); |
| 1795 | } |
| 1796 | ret = clk_prepare_enable(motg->core_clk); |
| 1797 | WARN(ret, "USB core_clk enable failed\n"); |
| 1798 | ret = clk_prepare_enable(motg->pclk); |
| 1799 | WARN(ret, "USB pclk enable failed\n"); |
| 1800 | motg->lpm_flags &= ~CLOCKS_DOWN; |
| 1801 | } |
| 1802 | |
| 1803 | if (motg->lpm_flags & PHY_PWR_COLLAPSED) { |
| 1804 | msm_hsusb_ldo_enable(motg, USB_PHY_REG_ON); |
| 1805 | motg->lpm_flags &= ~PHY_PWR_COLLAPSED; |
| 1806 | } else if (motg->lpm_flags & PHY_REGULATORS_LPM) { |
| 1807 | msm_hsusb_ldo_enable(motg, USB_PHY_REG_LPM_OFF); |
| 1808 | motg->lpm_flags &= ~PHY_REGULATORS_LPM; |
| 1809 | } |
| 1810 | |
| 1811 | if (motg->lpm_flags & PHY_RETENTIONED || |
| 1812 | (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) { |
| 1813 | msm_hsusb_config_vddcx(1); |
| 1814 | ret = regulator_enable(hsusb_vdd); |
| 1815 | WARN(ret, "hsusb_vdd LDO enable failed\n"); |
| 1816 | msm_otg_disable_phy_hv_int(motg); |
| 1817 | msm_otg_exit_phy_retention(motg); |
| 1818 | motg->lpm_flags &= ~PHY_RETENTIONED; |
| 1819 | if (pdata->vddmin_gpio && motg->device_bus_suspend) |
| 1820 | gpio_direction_input(pdata->vddmin_gpio); |
| 1821 | } else if (motg->device_bus_suspend) { |
| 1822 | msm_otg_disable_phy_hv_int(motg); |
| 1823 | } |
| 1824 | |
| 1825 | temp = readl_relaxed(USB_USBCMD); |
| 1826 | temp &= ~ASYNC_INTR_CTRL; |
| 1827 | temp &= ~ULPI_STP_CTRL; |
| 1828 | writel_relaxed(temp, USB_USBCMD); |
| 1829 | |
| 1830 | /* |
| 1831 | * PHY comes out of low power mode (LPM) in case of wakeup |
| 1832 | * from asynchronous interrupt. |
| 1833 | */ |
| 1834 | if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD)) |
| 1835 | goto skip_phy_resume; |
| 1836 | |
| 1837 | writel_relaxed(readl_relaxed(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC); |
| 1838 | |
| 1839 | while (cnt < PHY_RESUME_TIMEOUT_USEC) { |
| 1840 | if (!(readl_relaxed(USB_PORTSC) & PORTSC_PHCD)) |
| 1841 | break; |
| 1842 | udelay(1); |
| 1843 | cnt++; |
| 1844 | } |
| 1845 | |
| 1846 | if (cnt >= PHY_RESUME_TIMEOUT_USEC) { |
| 1847 | /* |
| 1848 | * This is a fatal error. Reset the link and |
| 1849 | * PHY. USB state can not be restored. Re-insertion |
| 1850 | * of USB cable is the only way to get USB working. |
| 1851 | */ |
| 1852 | dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n" |
| 1853 | ); |
| 1854 | msm_otg_reset(phy); |
| 1855 | } |
| 1856 | |
| 1857 | skip_phy_resume: |
| 1858 | if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED) { |
| 1859 | /* put the controller in normal mode */ |
| 1860 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
| 1861 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
| 1862 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL; |
| 1863 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
| 1864 | } |
| 1865 | |
| 1866 | if (device_may_wakeup(phy->dev)) { |
| 1867 | if (motg->host_bus_suspend || motg->device_bus_suspend) { |
| 1868 | disable_irq_wake(motg->async_irq); |
| 1869 | disable_irq_wake(motg->irq); |
| 1870 | } |
| 1871 | |
| 1872 | if (motg->phy_irq) |
| 1873 | disable_irq_wake(motg->phy_irq); |
| 1874 | if (motg->pdata->pmic_id_irq) |
| 1875 | disable_irq_wake(motg->pdata->pmic_id_irq); |
| 1876 | if (motg->ext_id_irq) |
| 1877 | disable_irq_wake(motg->ext_id_irq); |
| 1878 | if (pdata->otg_control == OTG_PHY_CONTROL && |
| 1879 | pdata->mpm_otgsessvld_int) |
| 1880 | msm_mpm_set_pin_wake(pdata->mpm_otgsessvld_int, 0); |
| 1881 | if ((motg->host_bus_suspend || motg->device_bus_suspend) && |
| 1882 | pdata->mpm_dpshv_int) |
| 1883 | msm_mpm_set_pin_wake(pdata->mpm_dpshv_int, 0); |
| 1884 | if ((motg->host_bus_suspend || motg->device_bus_suspend) && |
| 1885 | pdata->mpm_dmshv_int) |
| 1886 | msm_mpm_set_pin_wake(pdata->mpm_dmshv_int, 0); |
| 1887 | } |
| 1888 | if (bus) |
| 1889 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); |
| 1890 | |
| 1891 | atomic_set(&motg->in_lpm, 0); |
| 1892 | |
| 1893 | if (motg->async_int) { |
| 1894 | /* Match the disable_irq call from ISR */ |
| 1895 | enable_irq(motg->async_int); |
| 1896 | motg->async_int = 0; |
| 1897 | } |
| 1898 | enable_irq(motg->irq); |
| 1899 | |
| 1900 | /* Enable ASYNC_IRQ only during LPM */ |
| 1901 | disable_irq(motg->async_irq); |
| 1902 | |
| 1903 | if (motg->phy_irq_pending) { |
| 1904 | motg->phy_irq_pending = false; |
| 1905 | msm_id_status_w(&motg->id_status_work.work); |
| 1906 | } |
| 1907 | |
| 1908 | if (motg->host_bus_suspend) { |
| 1909 | usb_hcd_resume_root_hub(hcd); |
| 1910 | schedule_delayed_work(&motg->perf_vote_work, |
| 1911 | msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); |
| 1912 | } |
| 1913 | |
| 1914 | dev_info(phy->dev, "USB exited from low power mode\n"); |
| 1915 | msm_otg_dbg_log_event(phy, "LPM EXIT DONE", |
| 1916 | motg->caps, motg->lpm_flags); |
| 1917 | |
| 1918 | return 0; |
| 1919 | } |
| 1920 | #endif |
| 1921 | |
| 1922 | static void msm_otg_notify_host_mode(struct msm_otg *motg, bool host_mode) |
| 1923 | { |
| 1924 | if (!psy) { |
| 1925 | pr_err("No USB power supply registered!\n"); |
| 1926 | return; |
| 1927 | } |
| 1928 | |
| 1929 | motg->host_mode = host_mode; |
| 1930 | power_supply_changed(psy); |
| 1931 | } |
| 1932 | |
| 1933 | static int msm_otg_notify_chg_type(struct msm_otg *motg) |
| 1934 | { |
| 1935 | static int charger_type; |
| 1936 | union power_supply_propval pval = {0}; |
| 1937 | |
| 1938 | /* |
| 1939 | * TODO |
| 1940 | * Unify OTG driver charger types and power supply charger types |
| 1941 | */ |
| 1942 | if (charger_type == motg->chg_type) |
| 1943 | return 0; |
| 1944 | |
| 1945 | if (motg->chg_type == USB_SDP_CHARGER) |
| 1946 | charger_type = POWER_SUPPLY_TYPE_USB; |
| 1947 | else if (motg->chg_type == USB_CDP_CHARGER) |
| 1948 | charger_type = POWER_SUPPLY_TYPE_USB_CDP; |
| 1949 | else if (motg->chg_type == USB_DCP_CHARGER || |
| 1950 | motg->chg_type == USB_NONCOMPLIANT_CHARGER || |
| 1951 | motg->chg_type == USB_FLOATED_CHARGER) |
| 1952 | charger_type = POWER_SUPPLY_TYPE_USB_DCP; |
| 1953 | else |
| 1954 | charger_type = POWER_SUPPLY_TYPE_UNKNOWN; |
| 1955 | |
| 1956 | if (!psy) { |
| 1957 | pr_err("No USB power supply registered!\n"); |
| 1958 | return -EINVAL; |
| 1959 | } |
| 1960 | |
| 1961 | pr_debug("setting usb power supply type %d\n", charger_type); |
| 1962 | msm_otg_dbg_log_event(&motg->phy, "SET USB PWR SUPPLY TYPE", |
| 1963 | motg->chg_type, charger_type); |
| 1964 | pval.intval = charger_type; |
| 1965 | power_supply_set_property(psy, POWER_SUPPLY_PROP_TYPE, &pval); |
| 1966 | return 0; |
| 1967 | } |
| 1968 | |
| 1969 | static int msm_otg_notify_power_supply(struct msm_otg *motg, unsigned int mA) |
| 1970 | { |
| 1971 | union power_supply_propval pval = {0}; |
| 1972 | bool enable; |
| 1973 | int limit; |
| 1974 | |
| 1975 | if (!psy) { |
| 1976 | dev_dbg(motg->phy.dev, "no usb power supply registered\n"); |
| 1977 | goto psy_error; |
| 1978 | } |
| 1979 | |
| 1980 | if (motg->cur_power == 0 && mA > 2) { |
| 1981 | /* Enable charging */ |
| 1982 | enable = true; |
| 1983 | limit = 1000 * mA; |
| 1984 | } else if (motg->cur_power >= 0 && (mA == 0 || mA == 2)) { |
| 1985 | /* Disable charging */ |
| 1986 | enable = false; |
| 1987 | /* Set max current limit in uA */ |
| 1988 | limit = 1000 * mA; |
| 1989 | } else { |
| 1990 | enable = true; |
| 1991 | /* Current has changed (100/2 --> 500) */ |
| 1992 | limit = 1000 * mA; |
| 1993 | } |
| 1994 | |
| 1995 | pval.intval = enable; |
| 1996 | if (power_supply_set_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval)) |
| 1997 | goto psy_error; |
| 1998 | |
| 1999 | pval.intval = limit; |
| 2000 | if (power_supply_set_property(psy, POWER_SUPPLY_PROP_CURRENT_MAX, |
| 2001 | &pval)) |
| 2002 | goto psy_error; |
| 2003 | |
| 2004 | power_supply_changed(psy); |
| 2005 | return 0; |
| 2006 | |
| 2007 | psy_error: |
| 2008 | dev_dbg(motg->phy.dev, "power supply error when setting property\n"); |
| 2009 | return -ENXIO; |
| 2010 | } |
| 2011 | |
| 2012 | static void msm_otg_set_online_status(struct msm_otg *motg) |
| 2013 | { |
| 2014 | union power_supply_propval pval = {0}; |
| 2015 | |
| 2016 | if (!psy) { |
| 2017 | dev_dbg(motg->phy.dev, "no usb power supply registered\n"); |
| 2018 | return; |
| 2019 | } |
| 2020 | |
| 2021 | /* Set power supply online status to false */ |
| 2022 | pval.intval = false; |
| 2023 | if (power_supply_set_property(psy, POWER_SUPPLY_PROP_ONLINE, &pval)) |
| 2024 | dev_dbg(motg->phy.dev, "error setting power supply property\n"); |
| 2025 | } |
| 2026 | |
| 2027 | static void msm_otg_notify_charger(struct msm_otg *motg, unsigned int mA) |
| 2028 | { |
| 2029 | struct usb_gadget *g = motg->phy.otg->gadget; |
| 2030 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 2031 | |
| 2032 | if (g && g->is_a_peripheral) |
| 2033 | return; |
| 2034 | |
| 2035 | dev_dbg(motg->phy.dev, "Requested curr from USB = %u, max-type-c:%u\n", |
| 2036 | mA, motg->typec_current_max); |
| 2037 | /* Save bc1.2 max_curr if type-c charger later moves to diff mode */ |
| 2038 | motg->bc1p2_current_max = mA; |
| 2039 | |
| 2040 | /* |
| 2041 | * Limit type-c charger current to 500 for SDP charger to avoid more |
| 2042 | * current drawn than 500 with Hosts that don't support type C due to |
| 2043 | * non compliant type-c to standard A cables. |
| 2044 | */ |
| 2045 | if (pdata->enable_sdp_typec_current_limit && |
| 2046 | (motg->chg_type == USB_SDP_CHARGER) && |
| 2047 | motg->typec_current_max > 500) |
| 2048 | motg->typec_current_max = 500; |
| 2049 | |
| 2050 | /* Override mA if type-c charger used (use hvdcp/bc1.2 if it is 500) */ |
| 2051 | if (motg->typec_current_max > 500 && mA < motg->typec_current_max) |
| 2052 | mA = motg->typec_current_max; |
| 2053 | |
| 2054 | if (msm_otg_notify_chg_type(motg)) |
| 2055 | dev_err(motg->phy.dev, |
| 2056 | "Failed notifying %d charger type to PMIC\n", |
| 2057 | motg->chg_type); |
| 2058 | |
| 2059 | /* |
| 2060 | * This condition will be true when usb cable is disconnected |
| 2061 | * during bootup before enumeration. Check charger type also |
| 2062 | * to avoid clearing online flag in case of valid charger. |
| 2063 | */ |
| 2064 | if (motg->online && motg->cur_power == 0 && mA == 0 && |
| 2065 | (motg->chg_type == USB_INVALID_CHARGER)) |
| 2066 | msm_otg_set_online_status(motg); |
| 2067 | |
| 2068 | if (motg->cur_power == mA) |
| 2069 | return; |
| 2070 | |
| 2071 | dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA); |
| 2072 | msm_otg_dbg_log_event(&motg->phy, "AVAIL CURR FROM USB", |
| 2073 | mA, motg->chg_type); |
| 2074 | |
| 2075 | msm_otg_notify_power_supply(motg, mA); |
| 2076 | |
| 2077 | motg->cur_power = mA; |
| 2078 | } |
| 2079 | |
| 2080 | static int msm_otg_set_power(struct usb_phy *phy, unsigned int mA) |
| 2081 | { |
| 2082 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
| 2083 | |
| 2084 | /* |
| 2085 | * Gadget driver uses set_power method to notify about the |
| 2086 | * available current based on suspend/configured states. |
| 2087 | * |
| 2088 | * IDEV_CHG can be drawn irrespective of suspend/un-configured |
| 2089 | * states when CDP/ACA is connected. |
| 2090 | */ |
| 2091 | if (motg->chg_type == USB_SDP_CHARGER) |
| 2092 | msm_otg_notify_charger(motg, mA); |
| 2093 | |
| 2094 | return 0; |
| 2095 | } |
| 2096 | |
| 2097 | static void msm_hsusb_vbus_power(struct msm_otg *motg, bool on); |
| 2098 | |
| 2099 | static void msm_otg_perf_vote_update(struct msm_otg *motg, bool perf_mode) |
| 2100 | { |
| 2101 | static bool curr_perf_mode; |
| 2102 | int ret, latency = motg->pm_qos_latency; |
| 2103 | long clk_rate; |
| 2104 | |
| 2105 | if (curr_perf_mode == perf_mode) |
| 2106 | return; |
| 2107 | |
| 2108 | if (perf_mode) { |
| 2109 | if (latency) |
| 2110 | pm_qos_update_request(&motg->pm_qos_req_dma, latency); |
| 2111 | msm_otg_bus_vote(motg, USB_MAX_PERF_VOTE); |
| 2112 | clk_rate = motg->core_clk_rate; |
| 2113 | } else { |
| 2114 | if (latency) |
| 2115 | pm_qos_update_request(&motg->pm_qos_req_dma, |
| 2116 | PM_QOS_DEFAULT_VALUE); |
| 2117 | msm_otg_bus_vote(motg, USB_MIN_PERF_VOTE); |
| 2118 | clk_rate = motg->core_clk_svs_rate; |
| 2119 | } |
| 2120 | |
| 2121 | if (clk_rate) { |
| 2122 | ret = clk_set_rate(motg->core_clk, clk_rate); |
| 2123 | if (ret) |
| 2124 | dev_err(motg->phy.dev, "sys_clk set_rate fail:%d %ld\n", |
| 2125 | ret, clk_rate); |
| 2126 | } |
| 2127 | curr_perf_mode = perf_mode; |
| 2128 | pr_debug("%s: latency updated to: %d, core_freq to: %ld\n", __func__, |
| 2129 | latency, clk_rate); |
| 2130 | } |
| 2131 | |
| 2132 | static void msm_otg_perf_vote_work(struct work_struct *w) |
| 2133 | { |
| 2134 | struct msm_otg *motg = container_of(w, struct msm_otg, |
| 2135 | perf_vote_work.work); |
| 2136 | unsigned int curr_sample_int_count; |
| 2137 | bool in_perf_mode = false; |
| 2138 | |
| 2139 | curr_sample_int_count = motg->usb_irq_count; |
| 2140 | motg->usb_irq_count = 0; |
| 2141 | |
| 2142 | if (curr_sample_int_count >= PM_QOS_THRESHOLD) |
| 2143 | in_perf_mode = true; |
| 2144 | |
| 2145 | msm_otg_perf_vote_update(motg, in_perf_mode); |
| 2146 | pr_debug("%s: in_perf_mode:%u, interrupts in last sample:%u\n", |
| 2147 | __func__, in_perf_mode, curr_sample_int_count); |
| 2148 | |
| 2149 | schedule_delayed_work(&motg->perf_vote_work, |
| 2150 | msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); |
| 2151 | } |
| 2152 | |
| 2153 | static void msm_otg_start_host(struct usb_otg *otg, int on) |
| 2154 | { |
| 2155 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
| 2156 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 2157 | struct usb_hcd *hcd; |
| 2158 | u32 val; |
| 2159 | |
| 2160 | if (!otg->host) |
| 2161 | return; |
| 2162 | |
| 2163 | hcd = bus_to_hcd(otg->host); |
| 2164 | |
| 2165 | msm_otg_dbg_log_event(&motg->phy, "PM RT: StartHost GET", |
| 2166 | get_pm_runtime_counter(motg->phy.dev), 0); |
| 2167 | pm_runtime_get_sync(otg->usb_phy->dev); |
| 2168 | if (on) { |
| 2169 | dev_dbg(otg->usb_phy->dev, "host on\n"); |
| 2170 | msm_otg_dbg_log_event(&motg->phy, "HOST ON", |
| 2171 | motg->inputs, otg->state); |
| 2172 | msm_hsusb_vbus_power(motg, 1); |
| 2173 | msm_otg_reset(&motg->phy); |
| 2174 | |
| 2175 | if (pdata->otg_control == OTG_PHY_CONTROL) |
| 2176 | ulpi_write(otg->usb_phy, OTG_COMP_DISABLE, |
| 2177 | ULPI_SET(ULPI_PWR_CLK_MNG_REG)); |
| 2178 | |
| 2179 | if (pdata->enable_axi_prefetch) { |
| 2180 | val = readl_relaxed(USB_HS_APF_CTRL); |
| 2181 | val &= ~APF_CTRL_EN; |
| 2182 | writel_relaxed(val, USB_HS_APF_CTRL); |
| 2183 | } |
| 2184 | usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); |
| 2185 | #ifdef CONFIG_SMP |
| 2186 | motg->pm_qos_req_dma.type = PM_QOS_REQ_AFFINE_IRQ; |
| 2187 | motg->pm_qos_req_dma.irq = motg->irq; |
| 2188 | #endif |
| 2189 | pm_qos_add_request(&motg->pm_qos_req_dma, |
| 2190 | PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
| 2191 | /* start in perf mode for better performance initially */ |
| 2192 | msm_otg_perf_vote_update(motg, true); |
| 2193 | schedule_delayed_work(&motg->perf_vote_work, |
| 2194 | msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); |
| 2195 | } else { |
| 2196 | dev_dbg(otg->usb_phy->dev, "host off\n"); |
| 2197 | msm_otg_dbg_log_event(&motg->phy, "HOST OFF", |
| 2198 | motg->inputs, otg->state); |
| 2199 | msm_hsusb_vbus_power(motg, 0); |
| 2200 | |
| 2201 | cancel_delayed_work_sync(&motg->perf_vote_work); |
| 2202 | msm_otg_perf_vote_update(motg, false); |
| 2203 | pm_qos_remove_request(&motg->pm_qos_req_dma); |
| 2204 | |
| 2205 | pm_runtime_disable(&hcd->self.root_hub->dev); |
| 2206 | pm_runtime_barrier(&hcd->self.root_hub->dev); |
| 2207 | usb_remove_hcd(hcd); |
| 2208 | msm_otg_reset(&motg->phy); |
| 2209 | |
| 2210 | if (pdata->enable_axi_prefetch) |
| 2211 | writel_relaxed(readl_relaxed(USB_HS_APF_CTRL) |
| 2212 | | (APF_CTRL_EN), USB_HS_APF_CTRL); |
| 2213 | |
| 2214 | /* HCD core reset all bits of PORTSC. select ULPI phy */ |
| 2215 | writel_relaxed(0x80000000, USB_PORTSC); |
| 2216 | |
| 2217 | if (pdata->otg_control == OTG_PHY_CONTROL) |
| 2218 | ulpi_write(otg->usb_phy, OTG_COMP_DISABLE, |
| 2219 | ULPI_CLR(ULPI_PWR_CLK_MNG_REG)); |
| 2220 | } |
| 2221 | msm_otg_dbg_log_event(&motg->phy, "PM RT: StartHost PUT", |
| 2222 | get_pm_runtime_counter(motg->phy.dev), 0); |
| 2223 | |
| 2224 | pm_runtime_mark_last_busy(otg->usb_phy->dev); |
| 2225 | pm_runtime_put_autosuspend(otg->usb_phy->dev); |
| 2226 | } |
| 2227 | |
| 2228 | static void msm_hsusb_vbus_power(struct msm_otg *motg, bool on) |
| 2229 | { |
| 2230 | int ret; |
| 2231 | static bool vbus_is_on; |
| 2232 | |
| 2233 | msm_otg_dbg_log_event(&motg->phy, "VBUS POWER", on, vbus_is_on); |
| 2234 | if (vbus_is_on == on) |
| 2235 | return; |
| 2236 | |
| 2237 | if (motg->pdata->vbus_power) { |
| 2238 | ret = motg->pdata->vbus_power(on); |
| 2239 | if (!ret) |
| 2240 | vbus_is_on = on; |
| 2241 | return; |
| 2242 | } |
| 2243 | |
| 2244 | if (!vbus_otg) { |
| 2245 | pr_err("vbus_otg is NULL."); |
| 2246 | return; |
| 2247 | } |
| 2248 | |
| 2249 | /* |
| 2250 | * if entering host mode tell the charger to not draw any current |
| 2251 | * from usb before turning on the boost. |
| 2252 | * if exiting host mode disable the boost before enabling to draw |
| 2253 | * current from the source. |
| 2254 | */ |
| 2255 | if (on) { |
| 2256 | msm_otg_notify_host_mode(motg, on); |
| 2257 | ret = regulator_enable(vbus_otg); |
| 2258 | if (ret) { |
| 2259 | pr_err("unable to enable vbus_otg\n"); |
| 2260 | return; |
| 2261 | } |
| 2262 | vbus_is_on = true; |
| 2263 | } else { |
| 2264 | ret = regulator_disable(vbus_otg); |
| 2265 | if (ret) { |
| 2266 | pr_err("unable to disable vbus_otg\n"); |
| 2267 | return; |
| 2268 | } |
| 2269 | msm_otg_notify_host_mode(motg, on); |
| 2270 | vbus_is_on = false; |
| 2271 | } |
| 2272 | } |
| 2273 | |
| 2274 | static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) |
| 2275 | { |
| 2276 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
| 2277 | struct usb_hcd *hcd; |
| 2278 | |
| 2279 | /* |
| 2280 | * Fail host registration if this board can support |
| 2281 | * only peripheral configuration. |
| 2282 | */ |
| 2283 | if (motg->pdata->mode == USB_PERIPHERAL) { |
| 2284 | dev_info(otg->usb_phy->dev, "Host mode is not supported\n"); |
| 2285 | return -ENODEV; |
| 2286 | } |
| 2287 | |
| 2288 | if (!motg->pdata->vbus_power && host) { |
| 2289 | vbus_otg = devm_regulator_get(motg->phy.dev, "vbus_otg"); |
| 2290 | if (IS_ERR(vbus_otg)) { |
| 2291 | msm_otg_dbg_log_event(&motg->phy, |
| 2292 | "UNABLE TO GET VBUS_OTG", |
| 2293 | otg->state, 0); |
| 2294 | pr_err("Unable to get vbus_otg\n"); |
| 2295 | return PTR_ERR(vbus_otg); |
| 2296 | } |
| 2297 | } |
| 2298 | |
| 2299 | if (!host) { |
| 2300 | if (otg->state == OTG_STATE_A_HOST) { |
| 2301 | msm_otg_start_host(otg, 0); |
| 2302 | otg->host = NULL; |
| 2303 | otg->state = OTG_STATE_UNDEFINED; |
| 2304 | queue_work(motg->otg_wq, &motg->sm_work); |
| 2305 | } else { |
| 2306 | otg->host = NULL; |
| 2307 | } |
| 2308 | |
| 2309 | return 0; |
| 2310 | } |
| 2311 | |
| 2312 | hcd = bus_to_hcd(host); |
| 2313 | hcd->power_budget = motg->pdata->power_budget; |
| 2314 | |
| 2315 | otg->host = host; |
| 2316 | dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n"); |
| 2317 | msm_otg_dbg_log_event(&motg->phy, "HOST DRIVER REGISTERED", |
| 2318 | hcd->power_budget, motg->pdata->mode); |
| 2319 | |
| 2320 | /* |
| 2321 | * Kick the state machine work, if peripheral is not supported |
| 2322 | * or peripheral is already registered with us. |
| 2323 | */ |
| 2324 | if (motg->pdata->mode == USB_HOST || otg->gadget) |
| 2325 | queue_work(motg->otg_wq, &motg->sm_work); |
| 2326 | |
| 2327 | return 0; |
| 2328 | } |
| 2329 | |
| 2330 | static void msm_otg_start_peripheral(struct usb_otg *otg, int on) |
| 2331 | { |
| 2332 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
| 2333 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 2334 | struct pinctrl_state *set_state; |
| 2335 | int ret; |
| 2336 | |
| 2337 | if (!otg->gadget) |
| 2338 | return; |
| 2339 | |
| 2340 | msm_otg_dbg_log_event(&motg->phy, "PM RT: StartPeri GET", |
| 2341 | get_pm_runtime_counter(motg->phy.dev), 0); |
| 2342 | pm_runtime_get_sync(otg->usb_phy->dev); |
| 2343 | if (on) { |
| 2344 | dev_dbg(otg->usb_phy->dev, "gadget on\n"); |
| 2345 | msm_otg_dbg_log_event(&motg->phy, "GADGET ON", |
| 2346 | motg->inputs, otg->state); |
| 2347 | |
| 2348 | /* Configure BUS performance parameters for MAX bandwidth */ |
| 2349 | if (debug_bus_voting_enabled) |
| 2350 | msm_otg_bus_vote(motg, USB_MAX_PERF_VOTE); |
| 2351 | /* bump up usb core_clk to default */ |
| 2352 | clk_set_rate(motg->core_clk, motg->core_clk_rate); |
| 2353 | |
| 2354 | usb_gadget_vbus_connect(otg->gadget); |
| 2355 | |
| 2356 | /* |
| 2357 | * Request VDD min gpio, if need to support VDD |
| 2358 | * minimazation during peripheral bus suspend. |
| 2359 | */ |
| 2360 | if (pdata->vddmin_gpio) { |
| 2361 | if (motg->phy_pinctrl) { |
| 2362 | set_state = |
| 2363 | pinctrl_lookup_state(motg->phy_pinctrl, |
| 2364 | "hsusb_active"); |
| 2365 | if (IS_ERR(set_state)) { |
| 2366 | pr_err("cannot get phy pinctrl active state\n"); |
| 2367 | } else { |
| 2368 | pinctrl_select_state(motg->phy_pinctrl, |
| 2369 | set_state); |
| 2370 | } |
| 2371 | } |
| 2372 | |
| 2373 | ret = gpio_request(pdata->vddmin_gpio, |
| 2374 | "MSM_OTG_VDD_MIN_GPIO"); |
| 2375 | if (ret < 0) { |
| 2376 | dev_err(otg->usb_phy->dev, "gpio req failed for vdd min:%d\n", |
| 2377 | ret); |
| 2378 | pdata->vddmin_gpio = 0; |
| 2379 | } |
| 2380 | } |
| 2381 | } else { |
| 2382 | dev_dbg(otg->usb_phy->dev, "gadget off\n"); |
| 2383 | msm_otg_dbg_log_event(&motg->phy, "GADGET OFF", |
| 2384 | motg->inputs, otg->state); |
| 2385 | usb_gadget_vbus_disconnect(otg->gadget); |
| 2386 | clear_bit(A_BUS_SUSPEND, &motg->inputs); |
| 2387 | /* Configure BUS performance parameters to default */ |
| 2388 | msm_otg_bus_vote(motg, USB_MIN_PERF_VOTE); |
| 2389 | |
| 2390 | if (pdata->vddmin_gpio) { |
| 2391 | gpio_free(pdata->vddmin_gpio); |
| 2392 | if (motg->phy_pinctrl) { |
| 2393 | set_state = |
| 2394 | pinctrl_lookup_state(motg->phy_pinctrl, |
| 2395 | "hsusb_sleep"); |
| 2396 | if (IS_ERR(set_state)) |
| 2397 | pr_err("cannot get phy pinctrl sleep state\n"); |
| 2398 | else |
| 2399 | pinctrl_select_state(motg->phy_pinctrl, |
| 2400 | set_state); |
| 2401 | } |
| 2402 | } |
| 2403 | } |
| 2404 | msm_otg_dbg_log_event(&motg->phy, "PM RT: StartPeri PUT", |
| 2405 | get_pm_runtime_counter(motg->phy.dev), 0); |
| 2406 | pm_runtime_mark_last_busy(otg->usb_phy->dev); |
| 2407 | pm_runtime_put_autosuspend(otg->usb_phy->dev); |
| 2408 | } |
| 2409 | |
| 2410 | static int msm_otg_set_peripheral(struct usb_otg *otg, |
| 2411 | struct usb_gadget *gadget) |
| 2412 | { |
| 2413 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
| 2414 | |
| 2415 | /* |
| 2416 | * Fail peripheral registration if this board can support |
| 2417 | * only host configuration. |
| 2418 | */ |
| 2419 | if (motg->pdata->mode == USB_HOST) { |
| 2420 | dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n"); |
| 2421 | return -ENODEV; |
| 2422 | } |
| 2423 | |
| 2424 | if (!gadget) { |
| 2425 | if (otg->state == OTG_STATE_B_PERIPHERAL) { |
| 2426 | msm_otg_dbg_log_event(&motg->phy, |
| 2427 | "PM RUNTIME: PERIPHERAL GET1", |
| 2428 | get_pm_runtime_counter(otg->usb_phy->dev), 0); |
| 2429 | msm_otg_start_peripheral(otg, 0); |
| 2430 | otg->gadget = NULL; |
| 2431 | otg->state = OTG_STATE_UNDEFINED; |
| 2432 | queue_work(motg->otg_wq, &motg->sm_work); |
| 2433 | } else { |
| 2434 | otg->gadget = NULL; |
| 2435 | } |
| 2436 | |
| 2437 | return 0; |
| 2438 | } |
| 2439 | otg->gadget = gadget; |
| 2440 | dev_dbg(otg->usb_phy->dev, "peripheral driver registered w/ tranceiver\n"); |
| 2441 | msm_otg_dbg_log_event(&motg->phy, "PERIPHERAL DRIVER REGISTERED", |
| 2442 | otg->state, motg->pdata->mode); |
| 2443 | |
| 2444 | /* |
| 2445 | * Kick the state machine work, if host is not supported |
| 2446 | * or host is already registered with us. |
| 2447 | */ |
| 2448 | if (motg->pdata->mode == USB_PERIPHERAL || otg->host) |
| 2449 | queue_work(motg->otg_wq, &motg->sm_work); |
| 2450 | |
| 2451 | return 0; |
| 2452 | } |
| 2453 | |
| 2454 | static bool msm_otg_read_pmic_id_state(struct msm_otg *motg) |
| 2455 | { |
| 2456 | unsigned long flags; |
| 2457 | bool id; |
| 2458 | int ret; |
| 2459 | |
| 2460 | if (!motg->pdata->pmic_id_irq) |
| 2461 | return -ENODEV; |
| 2462 | |
| 2463 | local_irq_save(flags); |
| 2464 | ret = irq_get_irqchip_state(motg->pdata->pmic_id_irq, |
| 2465 | IRQCHIP_STATE_LINE_LEVEL, &id); |
| 2466 | local_irq_restore(flags); |
| 2467 | |
| 2468 | /* |
| 2469 | * If we can not read ID line state for some reason, treat |
| 2470 | * it as float. This would prevent MHL discovery and kicking |
| 2471 | * host mode unnecessarily. |
| 2472 | */ |
| 2473 | if (ret < 0) |
| 2474 | return true; |
| 2475 | |
| 2476 | return !!id; |
| 2477 | } |
| 2478 | |
| 2479 | static bool msm_otg_read_phy_id_state(struct msm_otg *motg) |
| 2480 | { |
| 2481 | u8 val; |
| 2482 | |
| 2483 | /* |
| 2484 | * clear the pending/outstanding interrupts and |
| 2485 | * read the ID status from the SRC_STATUS register. |
| 2486 | */ |
| 2487 | writeb_relaxed(USB_PHY_ID_MASK, USB2_PHY_USB_PHY_INTERRUPT_CLEAR1); |
| 2488 | |
| 2489 | writeb_relaxed(0x1, USB2_PHY_USB_PHY_IRQ_CMD); |
| 2490 | /* |
| 2491 | * Databook says 200 usec delay is required for |
| 2492 | * clearing the interrupts. |
| 2493 | */ |
| 2494 | udelay(200); |
| 2495 | writeb_relaxed(0x0, USB2_PHY_USB_PHY_IRQ_CMD); |
| 2496 | |
| 2497 | val = readb_relaxed(USB2_PHY_USB_PHY_INTERRUPT_SRC_STATUS); |
| 2498 | if (val & USB_PHY_IDDIG_1_0) |
| 2499 | return false; /* ID is grounded */ |
| 2500 | else |
| 2501 | return true; |
| 2502 | } |
| 2503 | |
| 2504 | static void msm_otg_chg_check_timer_func(unsigned long data) |
| 2505 | { |
| 2506 | struct msm_otg *motg = (struct msm_otg *) data; |
| 2507 | struct usb_otg *otg = motg->phy.otg; |
| 2508 | |
| 2509 | if (atomic_read(&motg->in_lpm) || |
| 2510 | !test_bit(B_SESS_VLD, &motg->inputs) || |
| 2511 | otg->state != OTG_STATE_B_PERIPHERAL || |
| 2512 | otg->gadget->speed != USB_SPEED_UNKNOWN) { |
| 2513 | dev_dbg(otg->usb_phy->dev, "Nothing to do in chg_check_timer\n"); |
| 2514 | return; |
| 2515 | } |
| 2516 | |
| 2517 | if ((readl_relaxed(USB_PORTSC) & PORTSC_LS) == PORTSC_LS) { |
| 2518 | dev_dbg(otg->usb_phy->dev, "DCP is detected as SDP\n"); |
| 2519 | msm_otg_dbg_log_event(&motg->phy, "DCP IS DETECTED AS SDP", |
| 2520 | otg->state, 0); |
| 2521 | set_bit(B_FALSE_SDP, &motg->inputs); |
| 2522 | queue_work(motg->otg_wq, &motg->sm_work); |
| 2523 | } |
| 2524 | } |
| 2525 | |
| 2526 | static bool msm_chg_check_secondary_det(struct msm_otg *motg) |
| 2527 | { |
| 2528 | struct usb_phy *phy = &motg->phy; |
| 2529 | u32 chg_det; |
| 2530 | bool ret = false; |
| 2531 | |
| 2532 | switch (motg->pdata->phy_type) { |
| 2533 | case SNPS_PICO_PHY: |
| 2534 | case SNPS_FEMTO_PHY: |
| 2535 | chg_det = ulpi_read(phy, 0x87); |
| 2536 | ret = chg_det & 1; |
| 2537 | break; |
| 2538 | default: |
| 2539 | break; |
| 2540 | } |
| 2541 | return ret; |
| 2542 | } |
| 2543 | |
| 2544 | static void msm_chg_enable_secondary_det(struct msm_otg *motg) |
| 2545 | { |
| 2546 | struct usb_phy *phy = &motg->phy; |
| 2547 | |
| 2548 | switch (motg->pdata->phy_type) { |
| 2549 | case SNPS_PICO_PHY: |
| 2550 | case SNPS_FEMTO_PHY: |
| 2551 | /* |
| 2552 | * Configure DM as current source, DP as current sink |
| 2553 | * and enable battery charging comparators. |
| 2554 | */ |
| 2555 | ulpi_write(phy, 0x8, 0x85); |
| 2556 | ulpi_write(phy, 0x2, 0x85); |
| 2557 | ulpi_write(phy, 0x1, 0x85); |
| 2558 | break; |
| 2559 | default: |
| 2560 | break; |
| 2561 | } |
| 2562 | } |
| 2563 | |
| 2564 | static bool msm_chg_check_primary_det(struct msm_otg *motg) |
| 2565 | { |
| 2566 | struct usb_phy *phy = &motg->phy; |
| 2567 | u32 chg_det; |
| 2568 | bool ret = false; |
| 2569 | |
| 2570 | switch (motg->pdata->phy_type) { |
| 2571 | case SNPS_PICO_PHY: |
| 2572 | case SNPS_FEMTO_PHY: |
| 2573 | chg_det = ulpi_read(phy, 0x87); |
| 2574 | ret = chg_det & 1; |
| 2575 | /* Turn off VDP_SRC */ |
| 2576 | ulpi_write(phy, 0x3, 0x86); |
| 2577 | msleep(20); |
| 2578 | break; |
| 2579 | default: |
| 2580 | break; |
| 2581 | } |
| 2582 | return ret; |
| 2583 | } |
| 2584 | |
| 2585 | static void msm_chg_enable_primary_det(struct msm_otg *motg) |
| 2586 | { |
| 2587 | struct usb_phy *phy = &motg->phy; |
| 2588 | |
| 2589 | switch (motg->pdata->phy_type) { |
| 2590 | case SNPS_PICO_PHY: |
| 2591 | case SNPS_FEMTO_PHY: |
| 2592 | /* |
| 2593 | * Configure DP as current source, DM as current sink |
| 2594 | * and enable battery charging comparators. |
| 2595 | */ |
| 2596 | ulpi_write(phy, 0x2, 0x85); |
| 2597 | ulpi_write(phy, 0x1, 0x85); |
| 2598 | break; |
| 2599 | default: |
| 2600 | break; |
| 2601 | } |
| 2602 | } |
| 2603 | |
| 2604 | static bool msm_chg_check_dcd(struct msm_otg *motg) |
| 2605 | { |
| 2606 | struct usb_phy *phy = &motg->phy; |
| 2607 | u32 line_state; |
| 2608 | bool ret = false; |
| 2609 | |
| 2610 | switch (motg->pdata->phy_type) { |
| 2611 | case SNPS_PICO_PHY: |
| 2612 | case SNPS_FEMTO_PHY: |
| 2613 | line_state = ulpi_read(phy, 0x87); |
| 2614 | ret = line_state & 2; |
| 2615 | break; |
| 2616 | default: |
| 2617 | break; |
| 2618 | } |
| 2619 | return ret; |
| 2620 | } |
| 2621 | |
| 2622 | static void msm_chg_disable_dcd(struct msm_otg *motg) |
| 2623 | { |
| 2624 | struct usb_phy *phy = &motg->phy; |
| 2625 | |
| 2626 | switch (motg->pdata->phy_type) { |
| 2627 | case SNPS_PICO_PHY: |
| 2628 | ulpi_write(phy, 0x10, 0x86); |
| 2629 | break; |
| 2630 | case SNPS_FEMTO_PHY: |
| 2631 | ulpi_write(phy, 0x10, 0x86); |
| 2632 | /* |
| 2633 | * Disable the Rdm_down after |
| 2634 | * the DCD is completed. |
| 2635 | */ |
| 2636 | ulpi_write(phy, 0x04, 0x0C); |
| 2637 | break; |
| 2638 | default: |
| 2639 | break; |
| 2640 | } |
| 2641 | } |
| 2642 | |
| 2643 | static void msm_chg_enable_dcd(struct msm_otg *motg) |
| 2644 | { |
| 2645 | struct usb_phy *phy = &motg->phy; |
| 2646 | |
| 2647 | switch (motg->pdata->phy_type) { |
| 2648 | case SNPS_PICO_PHY: |
| 2649 | /* Data contact detection enable */ |
| 2650 | ulpi_write(phy, 0x10, 0x85); |
| 2651 | break; |
| 2652 | case SNPS_FEMTO_PHY: |
| 2653 | /* |
| 2654 | * Idp_src and Rdm_down are de-coupled |
| 2655 | * on Femto PHY. If Idp_src alone is |
| 2656 | * enabled, DCD timeout is observed with |
| 2657 | * wall charger. But a genuine DCD timeout |
| 2658 | * may be incorrectly interpreted. Also |
| 2659 | * BC1.2 compliance testers expect Rdm_down |
| 2660 | * to enabled during DCD. Enable Rdm_down |
| 2661 | * explicitly before enabling the DCD. |
| 2662 | */ |
| 2663 | ulpi_write(phy, 0x04, 0x0B); |
| 2664 | ulpi_write(phy, 0x10, 0x85); |
| 2665 | break; |
| 2666 | default: |
| 2667 | break; |
| 2668 | } |
| 2669 | } |
| 2670 | |
| 2671 | static void msm_chg_block_on(struct msm_otg *motg) |
| 2672 | { |
| 2673 | struct usb_phy *phy = &motg->phy; |
| 2674 | u32 func_ctrl; |
| 2675 | |
| 2676 | /* put the controller in non-driving mode */ |
| 2677 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
| 2678 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
| 2679 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; |
| 2680 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
| 2681 | |
| 2682 | switch (motg->pdata->phy_type) { |
| 2683 | case SNPS_PICO_PHY: |
| 2684 | case SNPS_FEMTO_PHY: |
| 2685 | /* disable DP and DM pull down resistors */ |
| 2686 | ulpi_write(phy, 0x6, 0xC); |
| 2687 | /* Clear charger detecting control bits */ |
| 2688 | ulpi_write(phy, 0x1F, 0x86); |
| 2689 | /* Clear alt interrupt latch and enable bits */ |
| 2690 | ulpi_write(phy, 0x1F, 0x92); |
| 2691 | ulpi_write(phy, 0x1F, 0x95); |
| 2692 | udelay(100); |
| 2693 | break; |
| 2694 | default: |
| 2695 | break; |
| 2696 | } |
| 2697 | } |
| 2698 | |
| 2699 | static void msm_chg_block_off(struct msm_otg *motg) |
| 2700 | { |
| 2701 | struct usb_phy *phy = &motg->phy; |
| 2702 | u32 func_ctrl; |
| 2703 | |
| 2704 | switch (motg->pdata->phy_type) { |
| 2705 | case SNPS_PICO_PHY: |
| 2706 | case SNPS_FEMTO_PHY: |
| 2707 | /* Clear charger detecting control bits */ |
| 2708 | ulpi_write(phy, 0x3F, 0x86); |
| 2709 | /* Clear alt interrupt latch and enable bits */ |
| 2710 | ulpi_write(phy, 0x1F, 0x92); |
| 2711 | ulpi_write(phy, 0x1F, 0x95); |
| 2712 | /* re-enable DP and DM pull down resistors */ |
| 2713 | ulpi_write(phy, 0x6, 0xB); |
| 2714 | break; |
| 2715 | default: |
| 2716 | break; |
| 2717 | } |
| 2718 | |
| 2719 | /* put the controller in normal mode */ |
| 2720 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
| 2721 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
| 2722 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL; |
| 2723 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
| 2724 | } |
| 2725 | |
| 2726 | static const char *chg_to_string(enum usb_chg_type chg_type) |
| 2727 | { |
| 2728 | switch (chg_type) { |
| 2729 | case USB_SDP_CHARGER: return "USB_SDP_CHARGER"; |
| 2730 | case USB_DCP_CHARGER: return "USB_DCP_CHARGER"; |
| 2731 | case USB_CDP_CHARGER: return "USB_CDP_CHARGER"; |
| 2732 | case USB_NONCOMPLIANT_CHARGER: return "USB_NONCOMPLIANT_CHARGER"; |
| 2733 | case USB_FLOATED_CHARGER: return "USB_FLOATED_CHARGER"; |
| 2734 | default: return "INVALID_CHARGER"; |
| 2735 | } |
| 2736 | } |
| 2737 | |
| 2738 | #define MSM_CHG_DCD_TIMEOUT (750 * HZ/1000) /* 750 msec */ |
| 2739 | #define MSM_CHG_DCD_POLL_TIME (50 * HZ/1000) /* 50 msec */ |
| 2740 | #define MSM_CHG_PRIMARY_DET_TIME (50 * HZ/1000) /* TVDPSRC_ON */ |
| 2741 | #define MSM_CHG_SECONDARY_DET_TIME (50 * HZ/1000) /* TVDMSRC_ON */ |
| 2742 | static void msm_chg_detect_work(struct work_struct *w) |
| 2743 | { |
| 2744 | struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work); |
| 2745 | struct usb_phy *phy = &motg->phy; |
| 2746 | bool is_dcd = false, tmout, vout; |
| 2747 | static bool dcd; |
| 2748 | u32 line_state, dm_vlgc; |
| 2749 | unsigned long delay; |
| 2750 | |
| 2751 | dev_dbg(phy->dev, "chg detection work\n"); |
| 2752 | msm_otg_dbg_log_event(phy, "CHG DETECTION WORK", |
| 2753 | motg->chg_state, get_pm_runtime_counter(phy->dev)); |
| 2754 | |
| 2755 | switch (motg->chg_state) { |
| 2756 | case USB_CHG_STATE_UNDEFINED: |
| 2757 | case USB_CHG_STATE_IN_PROGRESS: |
| 2758 | msm_chg_block_on(motg); |
| 2759 | msm_chg_enable_dcd(motg); |
| 2760 | motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; |
| 2761 | motg->dcd_time = 0; |
| 2762 | delay = MSM_CHG_DCD_POLL_TIME; |
| 2763 | break; |
| 2764 | case USB_CHG_STATE_WAIT_FOR_DCD: |
| 2765 | is_dcd = msm_chg_check_dcd(motg); |
| 2766 | motg->dcd_time += MSM_CHG_DCD_POLL_TIME; |
| 2767 | tmout = motg->dcd_time >= MSM_CHG_DCD_TIMEOUT; |
| 2768 | if (is_dcd || tmout) { |
| 2769 | if (is_dcd) |
| 2770 | dcd = true; |
| 2771 | else |
| 2772 | dcd = false; |
| 2773 | msm_chg_disable_dcd(motg); |
| 2774 | msm_chg_enable_primary_det(motg); |
| 2775 | delay = MSM_CHG_PRIMARY_DET_TIME; |
| 2776 | motg->chg_state = USB_CHG_STATE_DCD_DONE; |
| 2777 | } else { |
| 2778 | delay = MSM_CHG_DCD_POLL_TIME; |
| 2779 | } |
| 2780 | break; |
| 2781 | case USB_CHG_STATE_DCD_DONE: |
| 2782 | vout = msm_chg_check_primary_det(motg); |
| 2783 | line_state = readl_relaxed(USB_PORTSC) & PORTSC_LS; |
| 2784 | dm_vlgc = line_state & PORTSC_LS_DM; |
| 2785 | if (vout && !dm_vlgc) { /* VDAT_REF < DM < VLGC */ |
| 2786 | if (line_state) { /* DP > VLGC */ |
| 2787 | motg->chg_type = USB_NONCOMPLIANT_CHARGER; |
| 2788 | motg->chg_state = USB_CHG_STATE_DETECTED; |
| 2789 | delay = 0; |
| 2790 | } else { |
| 2791 | msm_chg_enable_secondary_det(motg); |
| 2792 | delay = MSM_CHG_SECONDARY_DET_TIME; |
| 2793 | motg->chg_state = USB_CHG_STATE_PRIMARY_DONE; |
| 2794 | } |
| 2795 | } else { /* DM < VDAT_REF || DM > VLGC */ |
| 2796 | if (line_state) /* DP > VLGC or/and DM > VLGC */ |
| 2797 | motg->chg_type = USB_NONCOMPLIANT_CHARGER; |
| 2798 | else if (!dcd && floated_charger_enable) |
| 2799 | motg->chg_type = USB_FLOATED_CHARGER; |
| 2800 | else |
| 2801 | motg->chg_type = USB_SDP_CHARGER; |
| 2802 | |
| 2803 | motg->chg_state = USB_CHG_STATE_DETECTED; |
| 2804 | delay = 0; |
| 2805 | goto state_detected; |
| 2806 | } |
| 2807 | break; |
| 2808 | case USB_CHG_STATE_PRIMARY_DONE: |
| 2809 | vout = msm_chg_check_secondary_det(motg); |
| 2810 | if (vout) |
| 2811 | motg->chg_type = USB_DCP_CHARGER; |
| 2812 | else |
| 2813 | motg->chg_type = USB_CDP_CHARGER; |
| 2814 | motg->chg_state = USB_CHG_STATE_SECONDARY_DONE; |
| 2815 | /* fall through */ |
| 2816 | case USB_CHG_STATE_SECONDARY_DONE: |
| 2817 | motg->chg_state = USB_CHG_STATE_DETECTED; |
| 2818 | case USB_CHG_STATE_DETECTED: |
| 2819 | state_detected: |
| 2820 | /* |
| 2821 | * Notify the charger type to power supply |
| 2822 | * owner as soon as we determine the charger. |
| 2823 | */ |
| 2824 | if (motg->chg_type == USB_DCP_CHARGER && motg->ext_chg_opened) { |
| 2825 | init_completion(&motg->ext_chg_wait); |
| 2826 | motg->ext_chg_active = DEFAULT; |
| 2827 | } |
| 2828 | msm_otg_notify_chg_type(motg); |
| 2829 | msm_chg_block_off(motg); |
| 2830 | |
| 2831 | /* Enable VDP_SRC in case of DCP charger */ |
| 2832 | if (motg->chg_type == USB_DCP_CHARGER) |
| 2833 | ulpi_write(phy, 0x2, 0x85); |
| 2834 | |
| 2835 | dev_dbg(phy->dev, "chg_type = %s\n", |
| 2836 | chg_to_string(motg->chg_type)); |
| 2837 | msm_otg_dbg_log_event(phy, "CHG WORK PUT: CHG_TYPE", |
| 2838 | motg->chg_type, get_pm_runtime_counter(phy->dev)); |
| 2839 | /* to match _get from sm_work before starting chg_det_work */ |
| 2840 | pm_runtime_mark_last_busy(phy->dev); |
| 2841 | pm_runtime_put_autosuspend(phy->dev); |
| 2842 | |
| 2843 | queue_work(motg->otg_wq, &motg->sm_work); |
| 2844 | return; |
| 2845 | default: |
| 2846 | return; |
| 2847 | } |
| 2848 | |
| 2849 | msm_otg_dbg_log_event(phy, "CHG WORK: QUEUE", motg->chg_type, delay); |
| 2850 | queue_delayed_work(motg->otg_wq, &motg->chg_work, delay); |
| 2851 | } |
| 2852 | |
| 2853 | #define VBUS_INIT_TIMEOUT msecs_to_jiffies(5000) |
| 2854 | |
| 2855 | /* |
| 2856 | * We support OTG, Peripheral only and Host only configurations. In case |
| 2857 | * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen |
| 2858 | * via Id pin status or user request (debugfs). Id/BSV interrupts are not |
| 2859 | * enabled when switch is controlled by user and default mode is supplied |
| 2860 | * by board file, which can be changed by userspace later. |
| 2861 | */ |
| 2862 | static void msm_otg_init_sm(struct msm_otg *motg) |
| 2863 | { |
| 2864 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 2865 | u32 otgsc = readl_relaxed(USB_OTGSC); |
| 2866 | int ret; |
| 2867 | |
| 2868 | switch (pdata->mode) { |
| 2869 | case USB_OTG: |
| 2870 | if (pdata->otg_control == OTG_USER_CONTROL) { |
| 2871 | if (pdata->default_mode == USB_HOST) { |
| 2872 | clear_bit(ID, &motg->inputs); |
| 2873 | } else if (pdata->default_mode == USB_PERIPHERAL) { |
| 2874 | set_bit(ID, &motg->inputs); |
| 2875 | set_bit(B_SESS_VLD, &motg->inputs); |
| 2876 | } else { |
| 2877 | set_bit(ID, &motg->inputs); |
| 2878 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 2879 | } |
| 2880 | } else if (pdata->otg_control == OTG_PHY_CONTROL) { |
| 2881 | if (otgsc & OTGSC_ID) |
| 2882 | set_bit(ID, &motg->inputs); |
| 2883 | else |
| 2884 | clear_bit(ID, &motg->inputs); |
| 2885 | if (otgsc & OTGSC_BSV) |
| 2886 | set_bit(B_SESS_VLD, &motg->inputs); |
| 2887 | else |
| 2888 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 2889 | } else if (pdata->otg_control == OTG_PMIC_CONTROL) { |
| 2890 | if (pdata->pmic_id_irq) { |
| 2891 | if (msm_otg_read_pmic_id_state(motg)) |
| 2892 | set_bit(ID, &motg->inputs); |
| 2893 | else |
| 2894 | clear_bit(ID, &motg->inputs); |
| 2895 | } else if (motg->ext_id_irq) { |
| 2896 | if (gpio_get_value(pdata->usb_id_gpio)) |
| 2897 | set_bit(ID, &motg->inputs); |
| 2898 | else |
| 2899 | clear_bit(ID, &motg->inputs); |
| 2900 | } else if (motg->phy_irq) { |
| 2901 | if (msm_otg_read_phy_id_state(motg)) |
| 2902 | set_bit(ID, &motg->inputs); |
| 2903 | else |
| 2904 | clear_bit(ID, &motg->inputs); |
| 2905 | } |
| 2906 | /* |
| 2907 | * VBUS initial state is reported after PMIC |
| 2908 | * driver initialization. Wait for it. |
| 2909 | */ |
| 2910 | ret = wait_for_completion_timeout(&pmic_vbus_init, |
| 2911 | VBUS_INIT_TIMEOUT); |
| 2912 | if (!ret) { |
| 2913 | dev_dbg(motg->phy.dev, "%s: timeout waiting for PMIC VBUS\n", |
| 2914 | __func__); |
| 2915 | msm_otg_dbg_log_event(&motg->phy, |
| 2916 | "PMIC VBUS WAIT TMOUT", motg->inputs, |
| 2917 | motg->phy.otg->state); |
| 2918 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 2919 | pmic_vbus_init.done = 1; |
| 2920 | } |
| 2921 | } |
| 2922 | break; |
| 2923 | case USB_HOST: |
| 2924 | clear_bit(ID, &motg->inputs); |
| 2925 | break; |
| 2926 | case USB_PERIPHERAL: |
| 2927 | set_bit(ID, &motg->inputs); |
| 2928 | if (pdata->otg_control == OTG_PHY_CONTROL) { |
| 2929 | if (otgsc & OTGSC_BSV) |
| 2930 | set_bit(B_SESS_VLD, &motg->inputs); |
| 2931 | else |
| 2932 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 2933 | } else if (pdata->otg_control == OTG_PMIC_CONTROL) { |
| 2934 | /* |
| 2935 | * VBUS initial state is reported after PMIC |
| 2936 | * driver initialization. Wait for it. |
| 2937 | */ |
| 2938 | ret = wait_for_completion_timeout(&pmic_vbus_init, |
| 2939 | VBUS_INIT_TIMEOUT); |
| 2940 | if (!ret) { |
| 2941 | dev_dbg(motg->phy.dev, "%s: timeout waiting for PMIC VBUS\n", |
| 2942 | __func__); |
| 2943 | msm_otg_dbg_log_event(&motg->phy, |
| 2944 | "PMIC VBUS WAIT TMOUT", motg->inputs, |
| 2945 | motg->phy.otg->state); |
| 2946 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 2947 | pmic_vbus_init.done = 1; |
| 2948 | } |
| 2949 | } else if (pdata->otg_control == OTG_USER_CONTROL) { |
| 2950 | set_bit(ID, &motg->inputs); |
| 2951 | set_bit(B_SESS_VLD, &motg->inputs); |
| 2952 | } |
| 2953 | break; |
| 2954 | default: |
| 2955 | break; |
| 2956 | } |
| 2957 | msm_otg_dbg_log_event(&motg->phy, "SM INIT", pdata->mode, motg->inputs); |
| 2958 | if (motg->id_state != USB_ID_GROUND) |
| 2959 | motg->id_state = (test_bit(ID, &motg->inputs)) ? USB_ID_FLOAT : |
| 2960 | USB_ID_GROUND; |
| 2961 | } |
| 2962 | |
| 2963 | static void msm_otg_wait_for_ext_chg_done(struct msm_otg *motg) |
| 2964 | { |
| 2965 | struct usb_phy *phy = &motg->phy; |
| 2966 | unsigned long t; |
| 2967 | |
| 2968 | /* |
| 2969 | * Defer next cable connect event till external charger |
| 2970 | * detection is completed. |
| 2971 | */ |
| 2972 | |
| 2973 | if (motg->ext_chg_active == ACTIVE) { |
| 2974 | |
| 2975 | do_wait: |
| 2976 | pr_debug("before msm_otg ext chg wait\n"); |
| 2977 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: WAIT", 0, 0); |
| 2978 | |
| 2979 | t = wait_for_completion_timeout(&motg->ext_chg_wait, |
| 2980 | msecs_to_jiffies(3000)); |
| 2981 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: DONE", t, 0); |
| 2982 | |
| 2983 | if (!t) |
| 2984 | pr_err("msm_otg ext chg wait timeout\n"); |
| 2985 | else if (motg->ext_chg_active == ACTIVE) |
| 2986 | goto do_wait; |
| 2987 | else |
| 2988 | pr_debug("msm_otg ext chg wait done\n"); |
| 2989 | } |
| 2990 | |
| 2991 | if (motg->ext_chg_opened) { |
| 2992 | if (phy->flags & ENABLE_DP_MANUAL_PULLUP) { |
| 2993 | ulpi_write(phy, ULPI_MISC_A_VBUSVLDEXT | |
| 2994 | ULPI_MISC_A_VBUSVLDEXTSEL, |
| 2995 | ULPI_CLR(ULPI_MISC_A)); |
| 2996 | } |
| 2997 | /* clear charging register bits */ |
| 2998 | ulpi_write(phy, 0x3F, 0x86); |
| 2999 | /* re-enable DP and DM pull-down resistors*/ |
| 3000 | ulpi_write(phy, 0x6, 0xB); |
| 3001 | } |
| 3002 | } |
| 3003 | |
| 3004 | static void msm_otg_sm_work(struct work_struct *w) |
| 3005 | { |
| 3006 | struct msm_otg *motg = container_of(w, struct msm_otg, sm_work); |
| 3007 | struct usb_otg *otg = motg->phy.otg; |
| 3008 | struct device *dev = otg->usb_phy->dev; |
| 3009 | bool work = 0, dcp; |
| 3010 | int ret; |
| 3011 | |
| 3012 | pr_debug("%s work\n", usb_otg_state_string(otg->state)); |
| 3013 | msm_otg_dbg_log_event(&motg->phy, "SM WORK:", |
| 3014 | otg->state, motg->inputs); |
| 3015 | |
| 3016 | /* Just resume h/w if reqd, pm_count is handled based on state/inputs */ |
| 3017 | if (motg->resume_pending) { |
| 3018 | pm_runtime_get_sync(otg->usb_phy->dev); |
| 3019 | if (atomic_read(&motg->in_lpm)) { |
| 3020 | dev_err(dev, "SM WORK: USB is in LPM\n"); |
| 3021 | msm_otg_dbg_log_event(&motg->phy, |
| 3022 | "SM WORK: USB IS IN LPM", |
| 3023 | otg->state, motg->inputs); |
| 3024 | msm_otg_resume(motg); |
| 3025 | } |
| 3026 | motg->resume_pending = false; |
| 3027 | pm_runtime_put_noidle(otg->usb_phy->dev); |
| 3028 | } |
| 3029 | |
| 3030 | switch (otg->state) { |
| 3031 | case OTG_STATE_UNDEFINED: |
| 3032 | pm_runtime_get_sync(otg->usb_phy->dev); |
| 3033 | msm_otg_reset(otg->usb_phy); |
| 3034 | /* Add child device only after block reset */ |
| 3035 | ret = of_platform_populate(motg->pdev->dev.of_node, NULL, NULL, |
| 3036 | &motg->pdev->dev); |
| 3037 | if (ret) |
| 3038 | dev_dbg(&motg->pdev->dev, "failed to add BAM core\n"); |
| 3039 | |
| 3040 | msm_otg_init_sm(motg); |
| 3041 | otg->state = OTG_STATE_B_IDLE; |
| 3042 | if (!test_bit(B_SESS_VLD, &motg->inputs) && |
| 3043 | test_bit(ID, &motg->inputs)) { |
| 3044 | msm_otg_dbg_log_event(&motg->phy, |
| 3045 | "PM RUNTIME: UNDEF PUT", |
| 3046 | get_pm_runtime_counter(otg->usb_phy->dev), 0); |
| 3047 | pm_runtime_put_sync(otg->usb_phy->dev); |
| 3048 | break; |
| 3049 | } |
| 3050 | pm_runtime_put(otg->usb_phy->dev); |
| 3051 | /* FALL THROUGH */ |
| 3052 | case OTG_STATE_B_IDLE: |
| 3053 | if (!test_bit(ID, &motg->inputs) && otg->host) { |
| 3054 | pr_debug("!id\n"); |
| 3055 | msm_otg_dbg_log_event(&motg->phy, "!ID", |
| 3056 | motg->inputs, otg->state); |
| 3057 | |
| 3058 | msm_otg_start_host(otg, 1); |
| 3059 | otg->state = OTG_STATE_A_HOST; |
| 3060 | } else if (test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3061 | pr_debug("b_sess_vld\n"); |
| 3062 | msm_otg_dbg_log_event(&motg->phy, "B_SESS_VLD", |
| 3063 | motg->inputs, otg->state); |
| 3064 | switch (motg->chg_state) { |
| 3065 | case USB_CHG_STATE_UNDEFINED: |
| 3066 | /* put at the end of chg_det or disconnect */ |
| 3067 | pm_runtime_get_sync(otg->usb_phy->dev); |
| 3068 | msm_otg_dbg_log_event(&motg->phy, "PM CHG GET", |
| 3069 | get_pm_runtime_counter(dev), 0); |
| 3070 | motg->chg_state = USB_CHG_STATE_IN_PROGRESS; |
| 3071 | msm_chg_detect_work(&motg->chg_work.work); |
| 3072 | break; |
| 3073 | case USB_CHG_STATE_DETECTED: |
| 3074 | switch (motg->chg_type) { |
| 3075 | case USB_DCP_CHARGER: |
| 3076 | /* fall through */ |
| 3077 | case USB_NONCOMPLIANT_CHARGER: |
| 3078 | msm_otg_notify_charger(motg, |
| 3079 | dcp_max_current); |
| 3080 | if (!motg->is_ext_chg_dcp) |
| 3081 | otg->state = |
| 3082 | OTG_STATE_B_CHARGER; |
| 3083 | break; |
| 3084 | case USB_FLOATED_CHARGER: |
| 3085 | msm_otg_notify_charger(motg, |
| 3086 | IDEV_CHG_MAX); |
| 3087 | otg->state = OTG_STATE_B_CHARGER; |
| 3088 | break; |
| 3089 | case USB_CDP_CHARGER: |
| 3090 | msm_otg_notify_charger(motg, |
| 3091 | IDEV_CHG_MAX); |
| 3092 | /* fall through */ |
| 3093 | case USB_SDP_CHARGER: |
| 3094 | pm_runtime_get_sync(otg->usb_phy->dev); |
| 3095 | msm_otg_start_peripheral(otg, 1); |
| 3096 | otg->state = |
| 3097 | OTG_STATE_B_PERIPHERAL; |
| 3098 | mod_timer(&motg->chg_check_timer, |
| 3099 | CHG_RECHECK_DELAY); |
| 3100 | break; |
| 3101 | default: |
| 3102 | break; |
| 3103 | } |
| 3104 | break; |
| 3105 | default: |
| 3106 | break; |
| 3107 | } |
| 3108 | } else { |
| 3109 | pr_debug("chg_work cancel"); |
| 3110 | msm_otg_dbg_log_event(&motg->phy, "CHG_WORK CANCEL", |
| 3111 | motg->inputs, otg->state); |
| 3112 | del_timer_sync(&motg->chg_check_timer); |
| 3113 | clear_bit(B_FALSE_SDP, &motg->inputs); |
| 3114 | cancel_delayed_work_sync(&motg->chg_work); |
| 3115 | /* |
| 3116 | * Find out whether chg_w couldn't start or finished. |
| 3117 | * In both the cases, runtime ref_count vote is missing |
| 3118 | */ |
| 3119 | if (motg->chg_state == USB_CHG_STATE_UNDEFINED || |
| 3120 | motg->chg_state == USB_CHG_STATE_DETECTED) { |
| 3121 | msm_otg_dbg_log_event(&motg->phy, "RT !CHG GET", |
| 3122 | get_pm_runtime_counter(otg->usb_phy->dev), 0); |
| 3123 | pm_runtime_get_sync(dev); |
| 3124 | } |
| 3125 | |
| 3126 | dcp = (motg->chg_type == USB_DCP_CHARGER); |
| 3127 | motg->chg_state = USB_CHG_STATE_UNDEFINED; |
| 3128 | motg->chg_type = USB_INVALID_CHARGER; |
| 3129 | msm_otg_notify_charger(motg, 0); |
| 3130 | if (dcp) { |
| 3131 | if (motg->ext_chg_active == DEFAULT) |
| 3132 | motg->ext_chg_active = INACTIVE; |
| 3133 | msm_otg_wait_for_ext_chg_done(motg); |
| 3134 | /* Turn off VDP_SRC */ |
| 3135 | ulpi_write(otg->usb_phy, 0x2, 0x86); |
| 3136 | } |
| 3137 | msm_chg_block_off(motg); |
| 3138 | msm_otg_dbg_log_event(&motg->phy, "RT: CHG A PUT", |
| 3139 | get_pm_runtime_counter(otg->usb_phy->dev), 0); |
| 3140 | /* Delay used only if autosuspend enabled */ |
| 3141 | pm_runtime_mark_last_busy(dev); |
| 3142 | pm_runtime_put_autosuspend(dev); |
| 3143 | } |
| 3144 | break; |
| 3145 | case OTG_STATE_B_PERIPHERAL: |
| 3146 | if (test_bit(B_SESS_VLD, &motg->inputs) && |
| 3147 | test_bit(B_FALSE_SDP, &motg->inputs)) { |
| 3148 | pr_debug("B_FALSE_SDP\n"); |
| 3149 | msm_otg_start_peripheral(otg, 0); |
| 3150 | motg->chg_type = USB_DCP_CHARGER; |
| 3151 | clear_bit(B_FALSE_SDP, &motg->inputs); |
| 3152 | otg->state = OTG_STATE_B_IDLE; |
| 3153 | msm_otg_dbg_log_event(&motg->phy, "B_FALSE_SDP PUT", |
| 3154 | get_pm_runtime_counter(dev), motg->inputs); |
| 3155 | pm_runtime_put_sync(dev); |
| 3156 | /* schedule work to update charging current */ |
| 3157 | work = 1; |
| 3158 | } else if (!test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3159 | msm_otg_start_peripheral(otg, 0); |
| 3160 | msm_otg_dbg_log_event(&motg->phy, "RT PM: B_PERI A PUT", |
| 3161 | get_pm_runtime_counter(dev), 0); |
| 3162 | /* _put for _get done on cable connect in B_IDLE */ |
| 3163 | pm_runtime_put_noidle(dev); |
| 3164 | /* Schedule work to finish cable disconnect processing*/ |
| 3165 | otg->state = OTG_STATE_B_IDLE; |
| 3166 | work = 1; |
| 3167 | } else if (test_bit(A_BUS_SUSPEND, &motg->inputs)) { |
| 3168 | pr_debug("a_bus_suspend\n"); |
| 3169 | msm_otg_dbg_log_event(&motg->phy, |
| 3170 | "BUS_SUSPEND: PM RT PUT", |
| 3171 | get_pm_runtime_counter(dev), 0); |
| 3172 | otg->state = OTG_STATE_B_SUSPEND; |
| 3173 | /* _get on connect in B_IDLE or host resume in B_SUSP */ |
| 3174 | pm_runtime_mark_last_busy(dev); |
| 3175 | pm_runtime_put_autosuspend(dev); |
| 3176 | } |
| 3177 | break; |
| 3178 | case OTG_STATE_B_SUSPEND: |
| 3179 | if (!test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3180 | msm_otg_start_peripheral(otg, 0); |
| 3181 | otg->state = OTG_STATE_B_IDLE; |
| 3182 | /* Schedule work to finish cable disconnect processing*/ |
| 3183 | work = 1; |
| 3184 | } else if (!test_bit(A_BUS_SUSPEND, &motg->inputs)) { |
| 3185 | pr_debug("!a_bus_suspend\n"); |
| 3186 | otg->state = OTG_STATE_B_PERIPHERAL; |
| 3187 | msm_otg_dbg_log_event(&motg->phy, |
| 3188 | "BUS_RESUME: PM RT GET", |
| 3189 | get_pm_runtime_counter(dev), 0); |
| 3190 | pm_runtime_get_sync(dev); |
| 3191 | } |
| 3192 | break; |
| 3193 | |
| 3194 | case OTG_STATE_B_CHARGER: |
| 3195 | if (test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3196 | pr_debug("BSV set again\n"); |
| 3197 | msm_otg_dbg_log_event(&motg->phy, "BSV SET AGAIN", |
| 3198 | motg->inputs, otg->state); |
| 3199 | } else if (!test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3200 | otg->state = OTG_STATE_B_IDLE; |
| 3201 | work = 1; |
| 3202 | } |
| 3203 | break; |
| 3204 | case OTG_STATE_A_HOST: |
| 3205 | if (test_bit(ID, &motg->inputs)) { |
| 3206 | msm_otg_start_host(otg, 0); |
| 3207 | otg->state = OTG_STATE_B_IDLE; |
| 3208 | work = 1; |
| 3209 | } |
| 3210 | break; |
| 3211 | default: |
| 3212 | break; |
| 3213 | } |
| 3214 | |
| 3215 | if (work) |
| 3216 | queue_work(motg->otg_wq, &motg->sm_work); |
| 3217 | } |
| 3218 | |
| 3219 | static irqreturn_t msm_otg_irq(int irq, void *data) |
| 3220 | { |
| 3221 | struct msm_otg *motg = data; |
| 3222 | struct usb_otg *otg = motg->phy.otg; |
| 3223 | u32 otgsc = 0; |
| 3224 | bool work = 0; |
| 3225 | |
| 3226 | if (atomic_read(&motg->in_lpm)) { |
| 3227 | pr_debug("OTG IRQ: %d in LPM\n", irq); |
| 3228 | msm_otg_dbg_log_event(&motg->phy, "OTG IRQ IS IN LPM", |
| 3229 | irq, otg->state); |
| 3230 | /*Ignore interrupt if one interrupt already seen in LPM*/ |
| 3231 | if (motg->async_int) |
| 3232 | return IRQ_HANDLED; |
| 3233 | |
| 3234 | disable_irq_nosync(irq); |
| 3235 | motg->async_int = irq; |
| 3236 | msm_otg_kick_sm_work(motg); |
| 3237 | |
| 3238 | return IRQ_HANDLED; |
| 3239 | } |
| 3240 | motg->usb_irq_count++; |
| 3241 | |
| 3242 | otgsc = readl_relaxed(USB_OTGSC); |
| 3243 | if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS))) |
| 3244 | return IRQ_NONE; |
| 3245 | |
| 3246 | if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) { |
| 3247 | if (otgsc & OTGSC_ID) { |
| 3248 | dev_dbg(otg->usb_phy->dev, "ID set\n"); |
| 3249 | msm_otg_dbg_log_event(&motg->phy, "ID SET", |
| 3250 | motg->inputs, otg->state); |
| 3251 | set_bit(ID, &motg->inputs); |
| 3252 | } else { |
| 3253 | dev_dbg(otg->usb_phy->dev, "ID clear\n"); |
| 3254 | msm_otg_dbg_log_event(&motg->phy, "ID CLEAR", |
| 3255 | motg->inputs, otg->state); |
| 3256 | clear_bit(ID, &motg->inputs); |
| 3257 | } |
| 3258 | work = 1; |
| 3259 | } else if ((otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { |
| 3260 | if (otgsc & OTGSC_BSV) { |
| 3261 | dev_dbg(otg->usb_phy->dev, "BSV set\n"); |
| 3262 | msm_otg_dbg_log_event(&motg->phy, "BSV SET", |
| 3263 | motg->inputs, otg->state); |
| 3264 | set_bit(B_SESS_VLD, &motg->inputs); |
| 3265 | } else { |
| 3266 | dev_dbg(otg->usb_phy->dev, "BSV clear\n"); |
| 3267 | msm_otg_dbg_log_event(&motg->phy, "BSV CLEAR", |
| 3268 | motg->inputs, otg->state); |
| 3269 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 3270 | clear_bit(A_BUS_SUSPEND, &motg->inputs); |
| 3271 | } |
| 3272 | work = 1; |
| 3273 | } |
| 3274 | if (work) |
| 3275 | queue_work(motg->otg_wq, &motg->sm_work); |
| 3276 | |
| 3277 | writel_relaxed(otgsc, USB_OTGSC); |
| 3278 | |
| 3279 | return IRQ_HANDLED; |
| 3280 | } |
| 3281 | |
| 3282 | static void msm_otg_set_vbus_state(int online) |
| 3283 | { |
| 3284 | struct msm_otg *motg = the_msm_otg; |
| 3285 | static bool init; |
| 3286 | |
| 3287 | motg->vbus_state = online; |
| 3288 | |
| 3289 | if (motg->err_event_seen) |
| 3290 | return; |
| 3291 | |
| 3292 | if (online) { |
| 3293 | pr_debug("PMIC: BSV set\n"); |
| 3294 | msm_otg_dbg_log_event(&motg->phy, "PMIC: BSV SET", |
| 3295 | init, motg->inputs); |
| 3296 | if (test_and_set_bit(B_SESS_VLD, &motg->inputs) && init) |
| 3297 | return; |
| 3298 | } else { |
| 3299 | pr_debug("PMIC: BSV clear\n"); |
| 3300 | msm_otg_dbg_log_event(&motg->phy, "PMIC: BSV CLEAR", |
| 3301 | init, motg->inputs); |
| 3302 | motg->is_ext_chg_dcp = false; |
| 3303 | if (!test_and_clear_bit(B_SESS_VLD, &motg->inputs) && init) |
| 3304 | return; |
| 3305 | } |
| 3306 | |
| 3307 | /* do not queue state m/c work if id is grounded */ |
| 3308 | if (!test_bit(ID, &motg->inputs) && |
| 3309 | !motg->pdata->vbus_low_as_hostmode) { |
| 3310 | /* |
| 3311 | * state machine work waits for initial VBUS |
| 3312 | * completion in UNDEFINED state. Process |
| 3313 | * the initial VBUS event in ID_GND state. |
| 3314 | */ |
| 3315 | if (init) |
| 3316 | return; |
| 3317 | } |
| 3318 | |
| 3319 | if (!init) { |
| 3320 | init = true; |
| 3321 | if (pmic_vbus_init.done && |
| 3322 | test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3323 | pr_debug("PMIC: BSV came late\n"); |
| 3324 | msm_otg_dbg_log_event(&motg->phy, "PMIC: BSV CAME LATE", |
| 3325 | init, motg->inputs); |
| 3326 | goto out; |
| 3327 | } |
| 3328 | |
| 3329 | if (motg->pdata->vbus_low_as_hostmode && |
| 3330 | !test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3331 | motg->id_state = USB_ID_GROUND; |
| 3332 | clear_bit(ID, &motg->inputs); |
| 3333 | } |
| 3334 | complete(&pmic_vbus_init); |
| 3335 | pr_debug("PMIC: BSV init complete\n"); |
| 3336 | msm_otg_dbg_log_event(&motg->phy, "PMIC: BSV INIT COMPLETE", |
| 3337 | init, motg->inputs); |
| 3338 | return; |
| 3339 | } |
| 3340 | |
| 3341 | out: |
| 3342 | if (motg->is_ext_chg_dcp) { |
| 3343 | if (test_bit(B_SESS_VLD, &motg->inputs)) { |
| 3344 | msm_otg_notify_charger(motg, IDEV_CHG_MAX); |
| 3345 | } else { |
| 3346 | motg->is_ext_chg_dcp = false; |
| 3347 | motg->chg_state = USB_CHG_STATE_UNDEFINED; |
| 3348 | motg->chg_type = USB_INVALID_CHARGER; |
| 3349 | msm_otg_notify_charger(motg, 0); |
| 3350 | } |
| 3351 | return; |
| 3352 | } |
| 3353 | |
| 3354 | msm_otg_dbg_log_event(&motg->phy, "CHECK VBUS EVENT DURING SUSPEND", |
| 3355 | atomic_read(&motg->pm_suspended), |
| 3356 | motg->sm_work_pending); |
| 3357 | |
| 3358 | /* Move to host mode on vbus low if required */ |
| 3359 | if (motg->pdata->vbus_low_as_hostmode) { |
| 3360 | if (!test_bit(B_SESS_VLD, &motg->inputs)) |
| 3361 | clear_bit(ID, &motg->inputs); |
| 3362 | else |
| 3363 | set_bit(ID, &motg->inputs); |
| 3364 | } |
| 3365 | msm_otg_kick_sm_work(motg); |
| 3366 | } |
| 3367 | |
| 3368 | static void msm_id_status_w(struct work_struct *w) |
| 3369 | { |
| 3370 | struct msm_otg *motg = container_of(w, struct msm_otg, |
| 3371 | id_status_work.work); |
| 3372 | int work = 0; |
| 3373 | |
| 3374 | dev_dbg(motg->phy.dev, "ID status_w\n"); |
| 3375 | |
| 3376 | if (motg->pdata->pmic_id_irq) |
| 3377 | motg->id_state = msm_otg_read_pmic_id_state(motg); |
| 3378 | else if (motg->ext_id_irq) |
| 3379 | motg->id_state = gpio_get_value(motg->pdata->usb_id_gpio); |
| 3380 | else if (motg->phy_irq) |
| 3381 | motg->id_state = msm_otg_read_phy_id_state(motg); |
| 3382 | |
| 3383 | if (motg->err_event_seen) |
| 3384 | return; |
| 3385 | |
| 3386 | if (motg->id_state) { |
| 3387 | if (gpio_is_valid(motg->pdata->switch_sel_gpio)) |
| 3388 | gpio_direction_input(motg->pdata->switch_sel_gpio); |
| 3389 | if (!test_and_set_bit(ID, &motg->inputs)) { |
| 3390 | pr_debug("ID set\n"); |
| 3391 | msm_otg_dbg_log_event(&motg->phy, "ID SET", |
| 3392 | motg->inputs, motg->phy.otg->state); |
| 3393 | work = 1; |
| 3394 | } |
| 3395 | } else { |
| 3396 | if (gpio_is_valid(motg->pdata->switch_sel_gpio)) |
| 3397 | gpio_direction_output(motg->pdata->switch_sel_gpio, 1); |
| 3398 | if (test_and_clear_bit(ID, &motg->inputs)) { |
| 3399 | pr_debug("ID clear\n"); |
| 3400 | msm_otg_dbg_log_event(&motg->phy, "ID CLEAR", |
| 3401 | motg->inputs, motg->phy.otg->state); |
| 3402 | work = 1; |
| 3403 | } |
| 3404 | } |
| 3405 | |
| 3406 | if (work && (motg->phy.otg->state != OTG_STATE_UNDEFINED)) { |
| 3407 | msm_otg_dbg_log_event(&motg->phy, |
| 3408 | "CHECK ID EVENT DURING SUSPEND", |
| 3409 | atomic_read(&motg->pm_suspended), |
| 3410 | motg->sm_work_pending); |
| 3411 | msm_otg_kick_sm_work(motg); |
| 3412 | } |
| 3413 | } |
| 3414 | |
| 3415 | #define MSM_ID_STATUS_DELAY 5 /* 5msec */ |
| 3416 | static irqreturn_t msm_id_irq(int irq, void *data) |
| 3417 | { |
| 3418 | struct msm_otg *motg = data; |
| 3419 | |
| 3420 | /*schedule delayed work for 5msec for ID line state to settle*/ |
| 3421 | queue_delayed_work(motg->otg_wq, &motg->id_status_work, |
| 3422 | msecs_to_jiffies(MSM_ID_STATUS_DELAY)); |
| 3423 | |
| 3424 | return IRQ_HANDLED; |
| 3425 | } |
| 3426 | |
| 3427 | int msm_otg_pm_notify(struct notifier_block *notify_block, |
| 3428 | unsigned long mode, void *unused) |
| 3429 | { |
| 3430 | struct msm_otg *motg = container_of( |
| 3431 | notify_block, struct msm_otg, pm_notify); |
| 3432 | |
| 3433 | dev_dbg(motg->phy.dev, "OTG PM notify:%lx, sm_pending:%u\n", mode, |
| 3434 | motg->sm_work_pending); |
| 3435 | msm_otg_dbg_log_event(&motg->phy, "PM NOTIFY", |
| 3436 | mode, motg->sm_work_pending); |
| 3437 | |
| 3438 | switch (mode) { |
| 3439 | case PM_POST_SUSPEND: |
| 3440 | /* OTG sm_work can be armed now */ |
| 3441 | atomic_set(&motg->pm_suspended, 0); |
| 3442 | |
| 3443 | /* Handle any deferred wakeup events from USB during suspend */ |
| 3444 | if (motg->sm_work_pending) { |
| 3445 | motg->sm_work_pending = false; |
| 3446 | queue_work(motg->otg_wq, &motg->sm_work); |
| 3447 | } |
| 3448 | break; |
| 3449 | |
| 3450 | default: |
| 3451 | break; |
| 3452 | } |
| 3453 | |
| 3454 | return NOTIFY_OK; |
| 3455 | } |
| 3456 | |
| 3457 | static int msm_otg_mode_show(struct seq_file *s, void *unused) |
| 3458 | { |
| 3459 | struct msm_otg *motg = s->private; |
| 3460 | struct usb_otg *otg = motg->phy.otg; |
| 3461 | |
| 3462 | switch (otg->state) { |
| 3463 | case OTG_STATE_A_HOST: |
| 3464 | seq_puts(s, "host\n"); |
| 3465 | break; |
| 3466 | case OTG_STATE_B_IDLE: |
| 3467 | case OTG_STATE_B_PERIPHERAL: |
| 3468 | case OTG_STATE_B_SUSPEND: |
| 3469 | seq_puts(s, "peripheral\n"); |
| 3470 | break; |
| 3471 | default: |
| 3472 | seq_puts(s, "none\n"); |
| 3473 | break; |
| 3474 | } |
| 3475 | |
| 3476 | return 0; |
| 3477 | } |
| 3478 | |
| 3479 | static int msm_otg_mode_open(struct inode *inode, struct file *file) |
| 3480 | { |
| 3481 | return single_open(file, msm_otg_mode_show, inode->i_private); |
| 3482 | } |
| 3483 | |
| 3484 | static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, |
| 3485 | size_t count, loff_t *ppos) |
| 3486 | { |
| 3487 | struct seq_file *s = file->private_data; |
| 3488 | struct msm_otg *motg = s->private; |
| 3489 | char buf[16]; |
| 3490 | struct usb_phy *phy = &motg->phy; |
| 3491 | int status = count; |
| 3492 | enum usb_mode_type req_mode; |
| 3493 | |
| 3494 | memset(buf, 0x00, sizeof(buf)); |
| 3495 | |
| 3496 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) { |
| 3497 | status = -EFAULT; |
| 3498 | goto out; |
| 3499 | } |
| 3500 | |
| 3501 | if (!strncmp(buf, "host", 4)) { |
| 3502 | req_mode = USB_HOST; |
| 3503 | } else if (!strncmp(buf, "peripheral", 10)) { |
| 3504 | req_mode = USB_PERIPHERAL; |
| 3505 | } else if (!strncmp(buf, "none", 4)) { |
| 3506 | req_mode = USB_NONE; |
| 3507 | } else { |
| 3508 | status = -EINVAL; |
| 3509 | goto out; |
| 3510 | } |
| 3511 | |
| 3512 | switch (req_mode) { |
| 3513 | case USB_NONE: |
| 3514 | switch (phy->otg->state) { |
| 3515 | case OTG_STATE_A_HOST: |
| 3516 | case OTG_STATE_B_PERIPHERAL: |
| 3517 | case OTG_STATE_B_SUSPEND: |
| 3518 | set_bit(ID, &motg->inputs); |
| 3519 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 3520 | break; |
| 3521 | default: |
| 3522 | goto out; |
| 3523 | } |
| 3524 | break; |
| 3525 | case USB_PERIPHERAL: |
| 3526 | switch (phy->otg->state) { |
| 3527 | case OTG_STATE_B_IDLE: |
| 3528 | case OTG_STATE_A_HOST: |
| 3529 | set_bit(ID, &motg->inputs); |
| 3530 | set_bit(B_SESS_VLD, &motg->inputs); |
| 3531 | break; |
| 3532 | default: |
| 3533 | goto out; |
| 3534 | } |
| 3535 | break; |
| 3536 | case USB_HOST: |
| 3537 | switch (phy->otg->state) { |
| 3538 | case OTG_STATE_B_IDLE: |
| 3539 | case OTG_STATE_B_PERIPHERAL: |
| 3540 | case OTG_STATE_B_SUSPEND: |
| 3541 | clear_bit(ID, &motg->inputs); |
| 3542 | break; |
| 3543 | default: |
| 3544 | goto out; |
| 3545 | } |
| 3546 | break; |
| 3547 | default: |
| 3548 | goto out; |
| 3549 | } |
| 3550 | |
| 3551 | motg->id_state = (test_bit(ID, &motg->inputs)) ? USB_ID_FLOAT : |
| 3552 | USB_ID_GROUND; |
| 3553 | queue_work(motg->otg_wq, &motg->sm_work); |
| 3554 | out: |
| 3555 | return status; |
| 3556 | } |
| 3557 | |
| 3558 | const struct file_operations msm_otg_mode_fops = { |
| 3559 | .open = msm_otg_mode_open, |
| 3560 | .read = seq_read, |
| 3561 | .write = msm_otg_mode_write, |
| 3562 | .llseek = seq_lseek, |
| 3563 | .release = single_release, |
| 3564 | }; |
| 3565 | |
| 3566 | static int msm_otg_show_otg_state(struct seq_file *s, void *unused) |
| 3567 | { |
| 3568 | struct msm_otg *motg = s->private; |
| 3569 | struct usb_phy *phy = &motg->phy; |
| 3570 | |
| 3571 | seq_printf(s, "%s\n", usb_otg_state_string(phy->otg->state)); |
| 3572 | return 0; |
| 3573 | } |
| 3574 | |
| 3575 | static int msm_otg_otg_state_open(struct inode *inode, struct file *file) |
| 3576 | { |
| 3577 | return single_open(file, msm_otg_show_otg_state, inode->i_private); |
| 3578 | } |
| 3579 | |
| 3580 | const struct file_operations msm_otg_state_fops = { |
| 3581 | .open = msm_otg_otg_state_open, |
| 3582 | .read = seq_read, |
| 3583 | .llseek = seq_lseek, |
| 3584 | .release = single_release, |
| 3585 | }; |
| 3586 | |
| 3587 | static int msm_otg_show_chg_type(struct seq_file *s, void *unused) |
| 3588 | { |
| 3589 | struct msm_otg *motg = s->private; |
| 3590 | |
| 3591 | seq_printf(s, "%s\n", chg_to_string(motg->chg_type)); |
| 3592 | return 0; |
| 3593 | } |
| 3594 | |
| 3595 | static int msm_otg_chg_open(struct inode *inode, struct file *file) |
| 3596 | { |
| 3597 | return single_open(file, msm_otg_show_chg_type, inode->i_private); |
| 3598 | } |
| 3599 | |
| 3600 | const struct file_operations msm_otg_chg_fops = { |
| 3601 | .open = msm_otg_chg_open, |
| 3602 | .read = seq_read, |
| 3603 | .llseek = seq_lseek, |
| 3604 | .release = single_release, |
| 3605 | }; |
| 3606 | |
| 3607 | static int msm_otg_bus_show(struct seq_file *s, void *unused) |
| 3608 | { |
| 3609 | if (debug_bus_voting_enabled) |
| 3610 | seq_puts(s, "enabled\n"); |
| 3611 | else |
| 3612 | seq_puts(s, "disabled\n"); |
| 3613 | |
| 3614 | return 0; |
| 3615 | } |
| 3616 | |
| 3617 | static int msm_otg_bus_open(struct inode *inode, struct file *file) |
| 3618 | { |
| 3619 | return single_open(file, msm_otg_bus_show, inode->i_private); |
| 3620 | } |
| 3621 | |
| 3622 | static ssize_t msm_otg_bus_write(struct file *file, const char __user *ubuf, |
| 3623 | size_t count, loff_t *ppos) |
| 3624 | { |
| 3625 | char buf[8]; |
| 3626 | struct seq_file *s = file->private_data; |
| 3627 | struct msm_otg *motg = s->private; |
| 3628 | |
| 3629 | memset(buf, 0x00, sizeof(buf)); |
| 3630 | |
| 3631 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) |
| 3632 | return -EFAULT; |
| 3633 | |
| 3634 | if (!strncmp(buf, "enable", 6)) { |
| 3635 | /* Do not vote here. Let OTG statemachine decide when to vote */ |
| 3636 | debug_bus_voting_enabled = true; |
| 3637 | } else { |
| 3638 | debug_bus_voting_enabled = false; |
| 3639 | msm_otg_bus_vote(motg, USB_MIN_PERF_VOTE); |
| 3640 | } |
| 3641 | |
| 3642 | return count; |
| 3643 | } |
| 3644 | |
| 3645 | static int msm_otg_dbg_buff_show(struct seq_file *s, void *unused) |
| 3646 | { |
| 3647 | struct msm_otg *motg = s->private; |
| 3648 | unsigned long flags; |
| 3649 | unsigned int i; |
| 3650 | |
| 3651 | read_lock_irqsave(&motg->dbg_lock, flags); |
| 3652 | |
| 3653 | i = motg->dbg_idx; |
| 3654 | if (strnlen(motg->buf[i], DEBUG_MSG_LEN)) |
| 3655 | seq_printf(s, "%s\n", motg->buf[i]); |
| 3656 | for (dbg_inc(&i); i != motg->dbg_idx; dbg_inc(&i)) { |
| 3657 | if (!strnlen(motg->buf[i], DEBUG_MSG_LEN)) |
| 3658 | continue; |
| 3659 | seq_printf(s, "%s\n", motg->buf[i]); |
| 3660 | } |
| 3661 | read_unlock_irqrestore(&motg->dbg_lock, flags); |
| 3662 | |
| 3663 | return 0; |
| 3664 | } |
| 3665 | |
| 3666 | static int msm_otg_dbg_buff_open(struct inode *inode, struct file *file) |
| 3667 | { |
| 3668 | return single_open(file, msm_otg_dbg_buff_show, inode->i_private); |
| 3669 | } |
| 3670 | |
| 3671 | const struct file_operations msm_otg_dbg_buff_fops = { |
| 3672 | .open = msm_otg_dbg_buff_open, |
| 3673 | .read = seq_read, |
| 3674 | .llseek = seq_lseek, |
| 3675 | .release = single_release, |
| 3676 | }; |
| 3677 | |
| 3678 | static int msm_otg_dpdm_regulator_enable(struct regulator_dev *rdev) |
| 3679 | { |
| 3680 | int ret = 0; |
| 3681 | struct msm_otg *motg = rdev_get_drvdata(rdev); |
| 3682 | |
| 3683 | if (!motg->rm_pulldown) { |
| 3684 | ret = msm_hsusb_ldo_enable(motg, USB_PHY_REG_3P3_ON); |
| 3685 | if (!ret) { |
| 3686 | motg->rm_pulldown = true; |
| 3687 | msm_otg_dbg_log_event(&motg->phy, "RM Pulldown", |
| 3688 | motg->rm_pulldown, 0); |
| 3689 | } |
| 3690 | } |
| 3691 | |
| 3692 | return ret; |
| 3693 | } |
| 3694 | |
| 3695 | static int msm_otg_dpdm_regulator_disable(struct regulator_dev *rdev) |
| 3696 | { |
| 3697 | int ret = 0; |
| 3698 | struct msm_otg *motg = rdev_get_drvdata(rdev); |
| 3699 | |
| 3700 | if (motg->rm_pulldown) { |
| 3701 | ret = msm_hsusb_ldo_enable(motg, USB_PHY_REG_3P3_OFF); |
| 3702 | if (!ret) { |
| 3703 | motg->rm_pulldown = false; |
| 3704 | msm_otg_dbg_log_event(&motg->phy, "RM Pulldown", |
| 3705 | motg->rm_pulldown, 0); |
| 3706 | } |
| 3707 | } |
| 3708 | |
| 3709 | return ret; |
| 3710 | } |
| 3711 | |
| 3712 | static int msm_otg_dpdm_regulator_is_enabled(struct regulator_dev *rdev) |
| 3713 | { |
| 3714 | struct msm_otg *motg = rdev_get_drvdata(rdev); |
| 3715 | |
| 3716 | return motg->rm_pulldown; |
| 3717 | } |
| 3718 | |
| 3719 | static struct regulator_ops msm_otg_dpdm_regulator_ops = { |
| 3720 | .enable = msm_otg_dpdm_regulator_enable, |
| 3721 | .disable = msm_otg_dpdm_regulator_disable, |
| 3722 | .is_enabled = msm_otg_dpdm_regulator_is_enabled, |
| 3723 | }; |
| 3724 | |
| 3725 | static int usb_phy_regulator_init(struct msm_otg *motg) |
| 3726 | { |
| 3727 | struct device *dev = motg->phy.dev; |
| 3728 | struct regulator_config cfg = {}; |
| 3729 | struct regulator_init_data *init_data; |
| 3730 | |
| 3731 | init_data = devm_kzalloc(dev, sizeof(*init_data), GFP_KERNEL); |
| 3732 | if (!init_data) |
| 3733 | return -ENOMEM; |
| 3734 | |
| 3735 | init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_STATUS; |
| 3736 | motg->dpdm_rdesc.owner = THIS_MODULE; |
| 3737 | motg->dpdm_rdesc.type = REGULATOR_VOLTAGE; |
| 3738 | motg->dpdm_rdesc.ops = &msm_otg_dpdm_regulator_ops; |
| 3739 | motg->dpdm_rdesc.name = kbasename(dev->of_node->full_name); |
| 3740 | |
| 3741 | cfg.dev = dev; |
| 3742 | cfg.init_data = init_data; |
| 3743 | cfg.driver_data = motg; |
| 3744 | cfg.of_node = dev->of_node; |
| 3745 | |
| 3746 | motg->dpdm_rdev = devm_regulator_register(dev, &motg->dpdm_rdesc, &cfg); |
| 3747 | if (IS_ERR(motg->dpdm_rdev)) |
| 3748 | return PTR_ERR(motg->dpdm_rdev); |
| 3749 | |
| 3750 | return 0; |
| 3751 | } |
| 3752 | |
| 3753 | const struct file_operations msm_otg_bus_fops = { |
| 3754 | .open = msm_otg_bus_open, |
| 3755 | .read = seq_read, |
| 3756 | .write = msm_otg_bus_write, |
| 3757 | .llseek = seq_lseek, |
| 3758 | .release = single_release, |
| 3759 | }; |
| 3760 | |
| 3761 | static struct dentry *msm_otg_dbg_root; |
| 3762 | |
| 3763 | static int msm_otg_debugfs_init(struct msm_otg *motg) |
| 3764 | { |
| 3765 | struct dentry *msm_otg_dentry; |
| 3766 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 3767 | |
| 3768 | msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL); |
| 3769 | |
| 3770 | if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root)) |
| 3771 | return -ENODEV; |
| 3772 | |
| 3773 | if ((pdata->mode == USB_OTG || pdata->mode == USB_PERIPHERAL) && |
| 3774 | pdata->otg_control == OTG_USER_CONTROL) { |
| 3775 | |
| 3776 | msm_otg_dentry = debugfs_create_file("mode", 0644, |
| 3777 | msm_otg_dbg_root, motg, &msm_otg_mode_fops); |
| 3778 | |
| 3779 | if (!msm_otg_dentry) { |
| 3780 | debugfs_remove(msm_otg_dbg_root); |
| 3781 | msm_otg_dbg_root = NULL; |
| 3782 | return -ENODEV; |
| 3783 | } |
| 3784 | } |
| 3785 | |
| 3786 | msm_otg_dentry = debugfs_create_file("chg_type", 0444, msm_otg_dbg_root, |
| 3787 | motg, &msm_otg_chg_fops); |
| 3788 | |
| 3789 | if (!msm_otg_dentry) { |
| 3790 | debugfs_remove_recursive(msm_otg_dbg_root); |
| 3791 | return -ENODEV; |
| 3792 | } |
| 3793 | |
| 3794 | msm_otg_dentry = debugfs_create_file("bus_voting", 0644, |
| 3795 | msm_otg_dbg_root, motg, &msm_otg_bus_fops); |
| 3796 | |
| 3797 | if (!msm_otg_dentry) { |
| 3798 | debugfs_remove_recursive(msm_otg_dbg_root); |
| 3799 | return -ENODEV; |
| 3800 | } |
| 3801 | |
| 3802 | msm_otg_dentry = debugfs_create_file("otg_state", 0444, |
| 3803 | msm_otg_dbg_root, motg, &msm_otg_state_fops); |
| 3804 | |
| 3805 | if (!msm_otg_dentry) { |
| 3806 | debugfs_remove_recursive(msm_otg_dbg_root); |
| 3807 | return -ENODEV; |
| 3808 | } |
| 3809 | |
| 3810 | msm_otg_dentry = debugfs_create_file("dbg_buff", 0444, |
| 3811 | msm_otg_dbg_root, motg, &msm_otg_dbg_buff_fops); |
| 3812 | |
| 3813 | if (!msm_otg_dentry) { |
| 3814 | debugfs_remove_recursive(msm_otg_dbg_root); |
| 3815 | return -ENODEV; |
| 3816 | } |
| 3817 | return 0; |
| 3818 | } |
| 3819 | |
| 3820 | static void msm_otg_debugfs_cleanup(void) |
| 3821 | { |
| 3822 | debugfs_remove_recursive(msm_otg_dbg_root); |
| 3823 | } |
| 3824 | |
| 3825 | static ssize_t |
| 3826 | set_msm_otg_perf_mode(struct device *dev, struct device_attribute *attr, |
| 3827 | const char *buf, size_t count) |
| 3828 | { |
| 3829 | struct msm_otg *motg = the_msm_otg; |
| 3830 | int ret; |
| 3831 | long clk_rate; |
| 3832 | |
| 3833 | pr_debug("%s: enable:%d\n", __func__, !strncasecmp(buf, "enable", 6)); |
| 3834 | |
| 3835 | if (!strncasecmp(buf, "enable", 6)) { |
| 3836 | clk_rate = motg->core_clk_nominal_rate; |
| 3837 | msm_otg_bus_freq_set(motg, USB_NOC_NOM_VOTE); |
| 3838 | } else { |
| 3839 | clk_rate = motg->core_clk_svs_rate; |
| 3840 | msm_otg_bus_freq_set(motg, USB_NOC_SVS_VOTE); |
| 3841 | } |
| 3842 | |
| 3843 | if (clk_rate) { |
| 3844 | pr_debug("Set usb sys_clk rate:%ld\n", clk_rate); |
| 3845 | ret = clk_set_rate(motg->core_clk, clk_rate); |
| 3846 | if (ret) |
| 3847 | pr_err("sys_clk set_rate fail:%d %ld\n", ret, clk_rate); |
| 3848 | msm_otg_dbg_log_event(&motg->phy, "OTG PERF SET", |
| 3849 | clk_rate, ret); |
| 3850 | } else { |
| 3851 | pr_err("usb sys_clk rate is undefined\n"); |
| 3852 | } |
| 3853 | |
| 3854 | return count; |
| 3855 | } |
| 3856 | |
| 3857 | static DEVICE_ATTR(perf_mode, 0200, NULL, set_msm_otg_perf_mode); |
| 3858 | |
| 3859 | #define MSM_OTG_CMD_ID 0x09 |
| 3860 | #define MSM_OTG_DEVICE_ID 0x04 |
| 3861 | #define MSM_OTG_VMID_IDX 0xFF |
| 3862 | #define MSM_OTG_MEM_TYPE 0x02 |
| 3863 | struct msm_otg_scm_cmd_buf { |
| 3864 | unsigned int device_id; |
| 3865 | unsigned int vmid_idx; |
| 3866 | unsigned int mem_type; |
| 3867 | } __attribute__ ((__packed__)); |
| 3868 | |
| 3869 | static void msm_otg_pnoc_errata_fix(struct msm_otg *motg) |
| 3870 | { |
| 3871 | int ret; |
| 3872 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 3873 | struct msm_otg_scm_cmd_buf cmd_buf; |
| 3874 | |
| 3875 | if (!pdata->pnoc_errata_fix) |
| 3876 | return; |
| 3877 | |
| 3878 | dev_dbg(motg->phy.dev, "applying fix for pnoc h/w issue\n"); |
| 3879 | |
| 3880 | cmd_buf.device_id = MSM_OTG_DEVICE_ID; |
| 3881 | cmd_buf.vmid_idx = MSM_OTG_VMID_IDX; |
| 3882 | cmd_buf.mem_type = MSM_OTG_MEM_TYPE; |
| 3883 | |
| 3884 | ret = scm_call(SCM_SVC_MP, MSM_OTG_CMD_ID, &cmd_buf, |
| 3885 | sizeof(cmd_buf), NULL, 0); |
| 3886 | |
| 3887 | if (ret) |
| 3888 | dev_err(motg->phy.dev, "scm command failed to update VMIDMT\n"); |
| 3889 | } |
| 3890 | |
| 3891 | static u64 msm_otg_dma_mask = DMA_BIT_MASK(32); |
| 3892 | static struct platform_device *msm_otg_add_pdev( |
| 3893 | struct platform_device *ofdev, const char *name) |
| 3894 | { |
| 3895 | struct platform_device *pdev; |
| 3896 | const struct resource *res = ofdev->resource; |
| 3897 | unsigned int num = ofdev->num_resources; |
| 3898 | int retval; |
| 3899 | struct ci13xxx_platform_data ci_pdata; |
| 3900 | struct msm_otg_platform_data *otg_pdata; |
| 3901 | struct msm_otg *motg; |
| 3902 | |
| 3903 | pdev = platform_device_alloc(name, -1); |
| 3904 | if (!pdev) { |
| 3905 | retval = -ENOMEM; |
| 3906 | goto error; |
| 3907 | } |
| 3908 | |
| 3909 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
| 3910 | pdev->dev.dma_mask = &msm_otg_dma_mask; |
| 3911 | pdev->dev.parent = &ofdev->dev; |
| 3912 | |
| 3913 | if (num) { |
| 3914 | retval = platform_device_add_resources(pdev, res, num); |
| 3915 | if (retval) |
| 3916 | goto error; |
| 3917 | } |
| 3918 | |
| 3919 | if (!strcmp(name, "msm_hsusb")) { |
| 3920 | otg_pdata = |
| 3921 | (struct msm_otg_platform_data *) |
| 3922 | ofdev->dev.platform_data; |
| 3923 | motg = platform_get_drvdata(ofdev); |
| 3924 | ci_pdata.log2_itc = otg_pdata->log2_itc; |
| 3925 | ci_pdata.usb_core_id = 0; |
| 3926 | ci_pdata.l1_supported = otg_pdata->l1_supported; |
| 3927 | ci_pdata.enable_ahb2ahb_bypass = |
| 3928 | otg_pdata->enable_ahb2ahb_bypass; |
| 3929 | ci_pdata.enable_streaming = otg_pdata->enable_streaming; |
| 3930 | ci_pdata.enable_axi_prefetch = otg_pdata->enable_axi_prefetch; |
| 3931 | retval = platform_device_add_data(pdev, &ci_pdata, |
| 3932 | sizeof(ci_pdata)); |
| 3933 | if (retval) |
| 3934 | goto error; |
| 3935 | } |
| 3936 | |
| 3937 | retval = platform_device_add(pdev); |
| 3938 | if (retval) |
| 3939 | goto error; |
| 3940 | |
| 3941 | return pdev; |
| 3942 | |
| 3943 | error: |
| 3944 | platform_device_put(pdev); |
| 3945 | return ERR_PTR(retval); |
| 3946 | } |
| 3947 | |
| 3948 | static int msm_otg_setup_devices(struct platform_device *ofdev, |
| 3949 | enum usb_mode_type mode, bool init) |
| 3950 | { |
| 3951 | const char *gadget_name = "msm_hsusb"; |
| 3952 | const char *host_name = "msm_hsusb_host"; |
| 3953 | static struct platform_device *gadget_pdev; |
| 3954 | static struct platform_device *host_pdev; |
| 3955 | int retval = 0; |
| 3956 | |
| 3957 | if (!init) { |
| 3958 | if (gadget_pdev) { |
| 3959 | platform_device_unregister(gadget_pdev); |
| 3960 | device_remove_file(&gadget_pdev->dev, |
| 3961 | &dev_attr_perf_mode); |
| 3962 | } |
| 3963 | if (host_pdev) |
| 3964 | platform_device_unregister(host_pdev); |
| 3965 | return 0; |
| 3966 | } |
| 3967 | |
| 3968 | switch (mode) { |
| 3969 | case USB_OTG: |
| 3970 | /* fall through */ |
| 3971 | case USB_PERIPHERAL: |
| 3972 | gadget_pdev = msm_otg_add_pdev(ofdev, gadget_name); |
| 3973 | if (IS_ERR(gadget_pdev)) { |
| 3974 | retval = PTR_ERR(gadget_pdev); |
| 3975 | break; |
| 3976 | } |
| 3977 | if (device_create_file(&gadget_pdev->dev, &dev_attr_perf_mode)) |
| 3978 | dev_err(&gadget_pdev->dev, "perf_mode file failed\n"); |
| 3979 | if (mode == USB_PERIPHERAL) |
| 3980 | break; |
| 3981 | /* fall through */ |
| 3982 | case USB_HOST: |
| 3983 | host_pdev = msm_otg_add_pdev(ofdev, host_name); |
| 3984 | if (IS_ERR(host_pdev)) { |
| 3985 | retval = PTR_ERR(host_pdev); |
| 3986 | if (mode == USB_OTG) { |
| 3987 | platform_device_unregister(gadget_pdev); |
| 3988 | device_remove_file(&gadget_pdev->dev, |
| 3989 | &dev_attr_perf_mode); |
| 3990 | } |
| 3991 | } |
| 3992 | break; |
| 3993 | default: |
| 3994 | break; |
| 3995 | } |
| 3996 | |
| 3997 | return retval; |
| 3998 | } |
| 3999 | |
| 4000 | static int msm_otg_ext_chg_open(struct inode *inode, struct file *file) |
| 4001 | { |
| 4002 | struct msm_otg *motg = the_msm_otg; |
| 4003 | |
| 4004 | pr_debug("msm_otg ext chg open\n"); |
| 4005 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: OPEN", |
| 4006 | motg->inputs, motg->phy.otg->state); |
| 4007 | |
| 4008 | motg->ext_chg_opened = true; |
| 4009 | file->private_data = (void *)motg; |
| 4010 | return 0; |
| 4011 | } |
| 4012 | |
| 4013 | static long |
| 4014 | msm_otg_ext_chg_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
| 4015 | { |
| 4016 | struct msm_otg *motg = file->private_data; |
| 4017 | struct msm_usb_chg_info info = {0}; |
| 4018 | int ret = 0, val; |
| 4019 | |
| 4020 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: IOCTL", cmd, 0); |
| 4021 | switch (cmd) { |
| 4022 | case MSM_USB_EXT_CHG_INFO: |
| 4023 | info.chg_block_type = USB_CHG_BLOCK_ULPI; |
| 4024 | info.page_offset = motg->io_res->start & ~PAGE_MASK; |
| 4025 | /* mmap() works on PAGE granularity */ |
| 4026 | info.length = PAGE_SIZE; |
| 4027 | |
| 4028 | if (copy_to_user((void __user *)arg, &info, sizeof(info))) { |
| 4029 | pr_err("%s: copy to user failed\n\n", __func__); |
| 4030 | ret = -EFAULT; |
| 4031 | } |
| 4032 | break; |
| 4033 | case MSM_USB_EXT_CHG_BLOCK_LPM: |
| 4034 | if (get_user(val, (int __user *)arg)) { |
| 4035 | pr_err("%s: get_user failed\n\n", __func__); |
| 4036 | ret = -EFAULT; |
| 4037 | break; |
| 4038 | } |
| 4039 | pr_debug("%s: LPM block request %d\n", __func__, val); |
| 4040 | msm_otg_dbg_log_event(&motg->phy, "LPM BLOCK REQ", val, 0); |
| 4041 | if (val) { /* block LPM */ |
| 4042 | if (motg->chg_type == USB_DCP_CHARGER) { |
| 4043 | motg->ext_chg_active = ACTIVE; |
| 4044 | msm_otg_dbg_log_event(&motg->phy, |
| 4045 | "PM RUNTIME: EXT_CHG GET", |
| 4046 | get_pm_runtime_counter(motg->phy.dev), 0); |
| 4047 | pm_runtime_get_sync(motg->phy.dev); |
| 4048 | } else { |
| 4049 | motg->ext_chg_active = INACTIVE; |
| 4050 | complete(&motg->ext_chg_wait); |
| 4051 | ret = -ENODEV; |
| 4052 | } |
| 4053 | } else { |
| 4054 | motg->ext_chg_active = INACTIVE; |
| 4055 | complete(&motg->ext_chg_wait); |
| 4056 | /* |
| 4057 | * If usb cable is disconnected and then userspace |
| 4058 | * calls ioctl to unblock low power mode, make sure |
| 4059 | * otg_sm work for usb disconnect is processed first |
| 4060 | * followed by decrementing the PM usage counters. |
| 4061 | */ |
| 4062 | flush_work(&motg->sm_work); |
| 4063 | msm_otg_dbg_log_event(&motg->phy, |
| 4064 | "PM RUNTIME: EXT_CHG PUT", |
| 4065 | get_pm_runtime_counter(motg->phy.dev), 0); |
| 4066 | pm_runtime_put_sync(motg->phy.dev); |
| 4067 | } |
| 4068 | break; |
| 4069 | case MSM_USB_EXT_CHG_VOLTAGE_INFO: |
| 4070 | if (get_user(val, (int __user *)arg)) { |
| 4071 | pr_err("%s: get_user failed\n\n", __func__); |
| 4072 | ret = -EFAULT; |
| 4073 | break; |
| 4074 | } |
| 4075 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: VOL REQ", cmd, val); |
| 4076 | |
| 4077 | if (val == USB_REQUEST_5V) |
| 4078 | pr_debug("%s:voting 5V voltage request\n", __func__); |
| 4079 | else if (val == USB_REQUEST_9V) |
| 4080 | pr_debug("%s:voting 9V voltage request\n", __func__); |
| 4081 | break; |
| 4082 | case MSM_USB_EXT_CHG_RESULT: |
| 4083 | if (get_user(val, (int __user *)arg)) { |
| 4084 | pr_err("%s: get_user failed\n\n", __func__); |
| 4085 | ret = -EFAULT; |
| 4086 | break; |
| 4087 | } |
| 4088 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: VOL REQ", cmd, val); |
| 4089 | |
| 4090 | if (!val) |
| 4091 | pr_debug("%s:voltage request successful\n", __func__); |
| 4092 | else |
| 4093 | pr_debug("%s:voltage request failed\n", __func__); |
| 4094 | break; |
| 4095 | case MSM_USB_EXT_CHG_TYPE: |
| 4096 | if (get_user(val, (int __user *)arg)) { |
| 4097 | pr_err("%s: get_user failed\n\n", __func__); |
| 4098 | ret = -EFAULT; |
| 4099 | break; |
| 4100 | } |
| 4101 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: VOL REQ", cmd, val); |
| 4102 | |
| 4103 | if (val) |
| 4104 | pr_debug("%s:charger is external charger\n", __func__); |
| 4105 | else |
| 4106 | pr_debug("%s:charger is not ext charger\n", __func__); |
| 4107 | break; |
| 4108 | default: |
| 4109 | ret = -EINVAL; |
| 4110 | } |
| 4111 | |
| 4112 | return ret; |
| 4113 | } |
| 4114 | |
| 4115 | static int msm_otg_ext_chg_mmap(struct file *file, struct vm_area_struct *vma) |
| 4116 | { |
| 4117 | struct msm_otg *motg = file->private_data; |
| 4118 | unsigned long vsize = vma->vm_end - vma->vm_start; |
| 4119 | int ret; |
| 4120 | |
| 4121 | if (vma->vm_pgoff || vsize > PAGE_SIZE) |
| 4122 | return -EINVAL; |
| 4123 | |
| 4124 | vma->vm_pgoff = __phys_to_pfn(motg->io_res->start); |
| 4125 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
| 4126 | |
| 4127 | ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
| 4128 | vsize, vma->vm_page_prot); |
| 4129 | if (ret < 0) { |
| 4130 | pr_err("%s: failed with return val %d\n", __func__, ret); |
| 4131 | return ret; |
| 4132 | } |
| 4133 | |
| 4134 | return 0; |
| 4135 | } |
| 4136 | |
| 4137 | static int msm_otg_ext_chg_release(struct inode *inode, struct file *file) |
| 4138 | { |
| 4139 | struct msm_otg *motg = file->private_data; |
| 4140 | |
| 4141 | pr_debug("msm_otg ext chg release\n"); |
| 4142 | msm_otg_dbg_log_event(&motg->phy, "EXT CHG: RELEASE", |
| 4143 | motg->inputs, motg->phy.otg->state); |
| 4144 | |
| 4145 | motg->ext_chg_opened = false; |
| 4146 | |
| 4147 | return 0; |
| 4148 | } |
| 4149 | |
| 4150 | static const struct file_operations msm_otg_ext_chg_fops = { |
| 4151 | .owner = THIS_MODULE, |
| 4152 | .open = msm_otg_ext_chg_open, |
| 4153 | .unlocked_ioctl = msm_otg_ext_chg_ioctl, |
| 4154 | .mmap = msm_otg_ext_chg_mmap, |
| 4155 | .release = msm_otg_ext_chg_release, |
| 4156 | }; |
| 4157 | |
| 4158 | static int msm_otg_setup_ext_chg_cdev(struct msm_otg *motg) |
| 4159 | { |
| 4160 | int ret; |
| 4161 | |
| 4162 | if (motg->pdata->enable_sec_phy || motg->pdata->mode == USB_HOST || |
| 4163 | motg->pdata->otg_control != OTG_PMIC_CONTROL) { |
| 4164 | pr_debug("usb ext chg is not supported by msm otg\n"); |
| 4165 | return -ENODEV; |
| 4166 | } |
| 4167 | |
| 4168 | ret = alloc_chrdev_region(&motg->ext_chg_dev, 0, 1, "usb_ext_chg"); |
| 4169 | if (ret < 0) { |
| 4170 | pr_err("Fail to allocate usb ext char dev region\n"); |
| 4171 | return ret; |
| 4172 | } |
| 4173 | motg->ext_chg_class = class_create(THIS_MODULE, "msm_ext_chg"); |
| 4174 | if (ret < 0) { |
| 4175 | pr_err("Fail to create usb ext chg class\n"); |
| 4176 | goto unreg_chrdev; |
| 4177 | } |
| 4178 | cdev_init(&motg->ext_chg_cdev, &msm_otg_ext_chg_fops); |
| 4179 | motg->ext_chg_cdev.owner = THIS_MODULE; |
| 4180 | |
| 4181 | ret = cdev_add(&motg->ext_chg_cdev, motg->ext_chg_dev, 1); |
| 4182 | if (ret < 0) { |
| 4183 | pr_err("Fail to add usb ext chg cdev\n"); |
| 4184 | goto destroy_class; |
| 4185 | } |
| 4186 | motg->ext_chg_device = device_create(motg->ext_chg_class, |
| 4187 | NULL, motg->ext_chg_dev, NULL, |
| 4188 | "usb_ext_chg"); |
| 4189 | if (IS_ERR(motg->ext_chg_device)) { |
| 4190 | pr_err("Fail to create usb ext chg device\n"); |
| 4191 | ret = PTR_ERR(motg->ext_chg_device); |
| 4192 | motg->ext_chg_device = NULL; |
| 4193 | goto del_cdev; |
| 4194 | } |
| 4195 | |
| 4196 | init_completion(&motg->ext_chg_wait); |
| 4197 | pr_debug("msm otg ext chg cdev setup success\n"); |
| 4198 | return 0; |
| 4199 | |
| 4200 | del_cdev: |
| 4201 | cdev_del(&motg->ext_chg_cdev); |
| 4202 | destroy_class: |
| 4203 | class_destroy(motg->ext_chg_class); |
| 4204 | unreg_chrdev: |
| 4205 | unregister_chrdev_region(motg->ext_chg_dev, 1); |
| 4206 | |
| 4207 | return ret; |
| 4208 | } |
| 4209 | |
| 4210 | static ssize_t dpdm_pulldown_enable_show(struct device *dev, |
| 4211 | struct device_attribute *attr, char *buf) |
| 4212 | { |
| 4213 | struct msm_otg *motg = the_msm_otg; |
| 4214 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 4215 | |
| 4216 | return snprintf(buf, PAGE_SIZE, "%s\n", pdata->dpdm_pulldown_added ? |
| 4217 | "enabled" : "disabled"); |
| 4218 | } |
| 4219 | |
| 4220 | static ssize_t dpdm_pulldown_enable_store(struct device *dev, |
| 4221 | struct device_attribute *attr, const char |
| 4222 | *buf, size_t size) |
| 4223 | { |
| 4224 | struct msm_otg *motg = the_msm_otg; |
| 4225 | struct msm_otg_platform_data *pdata = motg->pdata; |
| 4226 | |
| 4227 | if (!strncasecmp(buf, "enable", 6)) { |
| 4228 | pdata->dpdm_pulldown_added = true; |
| 4229 | return size; |
| 4230 | } else if (!strncasecmp(buf, "disable", 7)) { |
| 4231 | pdata->dpdm_pulldown_added = false; |
| 4232 | return size; |
| 4233 | } |
| 4234 | |
| 4235 | return -EINVAL; |
| 4236 | } |
| 4237 | |
| 4238 | static DEVICE_ATTR(dpdm_pulldown_enable, 0644, |
| 4239 | dpdm_pulldown_enable_show, dpdm_pulldown_enable_store); |
| 4240 | |
| 4241 | static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event, |
| 4242 | void *ptr) |
| 4243 | { |
| 4244 | struct msm_otg *motg = container_of(nb, struct msm_otg, vbus_nb); |
| 4245 | |
| 4246 | if (event) |
| 4247 | set_bit(B_SESS_VLD, &motg->inputs); |
| 4248 | else |
| 4249 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 4250 | |
| 4251 | queue_work(motg->otg_wq, &motg->sm_work); |
| 4252 | |
| 4253 | return NOTIFY_DONE; |
| 4254 | } |
| 4255 | |
| 4256 | static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event, |
| 4257 | void *ptr) |
| 4258 | { |
| 4259 | struct msm_otg *motg = container_of(nb, struct msm_otg, id_nb); |
| 4260 | |
| 4261 | if (event) |
| 4262 | clear_bit(ID, &motg->inputs); |
| 4263 | else |
| 4264 | set_bit(ID, &motg->inputs); |
| 4265 | |
| 4266 | queue_work(motg->otg_wq, &motg->sm_work); |
| 4267 | |
| 4268 | return NOTIFY_DONE; |
| 4269 | } |
| 4270 | |
| 4271 | static int msm_otg_extcon_register(struct msm_otg *motg) |
| 4272 | { |
| 4273 | struct device_node *node = motg->pdev->dev.of_node; |
| 4274 | struct extcon_dev *edev; |
| 4275 | int ret = 0; |
| 4276 | |
| 4277 | if (!of_property_read_bool(node, "extcon")) |
| 4278 | return 0; |
| 4279 | |
| 4280 | edev = extcon_get_edev_by_phandle(&motg->pdev->dev, 0); |
| 4281 | if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV) |
| 4282 | return PTR_ERR(edev); |
| 4283 | |
| 4284 | if (!IS_ERR(edev)) { |
| 4285 | motg->extcon_vbus = edev; |
| 4286 | motg->vbus_nb.notifier_call = msm_otg_vbus_notifier; |
| 4287 | ret = extcon_register_notifier(edev, EXTCON_USB, |
| 4288 | &motg->vbus_nb); |
| 4289 | if (ret < 0) { |
| 4290 | dev_err(&motg->pdev->dev, "failed to register notifier for USB\n"); |
| 4291 | return ret; |
| 4292 | } |
| 4293 | } |
| 4294 | |
| 4295 | if (of_count_phandle_with_args(node, "extcon", NULL) > 1) { |
| 4296 | edev = extcon_get_edev_by_phandle(&motg->pdev->dev, 1); |
| 4297 | if (IS_ERR(edev) && PTR_ERR(edev) != -ENODEV) { |
| 4298 | ret = PTR_ERR(edev); |
| 4299 | goto err; |
| 4300 | } |
| 4301 | } |
| 4302 | |
| 4303 | if (!IS_ERR(edev)) { |
| 4304 | motg->extcon_id = edev; |
| 4305 | motg->id_nb.notifier_call = msm_otg_id_notifier; |
| 4306 | ret = extcon_register_notifier(edev, EXTCON_USB_HOST, |
| 4307 | &motg->id_nb); |
| 4308 | if (ret < 0) { |
| 4309 | dev_err(&motg->pdev->dev, "failed to register notifier for USB-HOST\n"); |
| 4310 | goto err; |
| 4311 | } |
| 4312 | } |
| 4313 | |
| 4314 | return 0; |
| 4315 | err: |
| 4316 | if (motg->extcon_vbus) |
| 4317 | extcon_unregister_notifier(motg->extcon_vbus, EXTCON_USB, |
| 4318 | &motg->vbus_nb); |
| 4319 | |
| 4320 | return ret; |
| 4321 | } |
| 4322 | |
| 4323 | struct msm_otg_platform_data *msm_otg_dt_to_pdata(struct platform_device *pdev) |
| 4324 | { |
| 4325 | struct device_node *node = pdev->dev.of_node; |
| 4326 | struct msm_otg_platform_data *pdata; |
| 4327 | int len = 0; |
| 4328 | int res_gpio; |
| 4329 | |
| 4330 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
| 4331 | if (!pdata) |
| 4332 | return NULL; |
| 4333 | |
| 4334 | len = of_property_count_elems_of_size(node, |
| 4335 | "qcom,hsusb-otg-phy-init-seq", sizeof(len)); |
| 4336 | if (len > 0) { |
| 4337 | pdata->phy_init_seq = devm_kzalloc(&pdev->dev, |
| 4338 | len * sizeof(len), GFP_KERNEL); |
| 4339 | if (!pdata->phy_init_seq) |
| 4340 | return NULL; |
| 4341 | of_property_read_u32_array(node, "qcom,hsusb-otg-phy-init-seq", |
| 4342 | pdata->phy_init_seq, len); |
| 4343 | } |
| 4344 | of_property_read_u32(node, "qcom,hsusb-otg-power-budget", |
| 4345 | &pdata->power_budget); |
| 4346 | of_property_read_u32(node, "qcom,hsusb-otg-mode", |
| 4347 | &pdata->mode); |
| 4348 | of_property_read_u32(node, "qcom,hsusb-otg-otg-control", |
| 4349 | &pdata->otg_control); |
| 4350 | of_property_read_u32(node, "qcom,hsusb-otg-default-mode", |
| 4351 | &pdata->default_mode); |
| 4352 | of_property_read_u32(node, "qcom,hsusb-otg-phy-type", |
| 4353 | &pdata->phy_type); |
| 4354 | pdata->disable_reset_on_disconnect = of_property_read_bool(node, |
| 4355 | "qcom,hsusb-otg-disable-reset"); |
| 4356 | pdata->pnoc_errata_fix = of_property_read_bool(node, |
| 4357 | "qcom,hsusb-otg-pnoc-errata-fix"); |
| 4358 | pdata->enable_lpm_on_dev_suspend = of_property_read_bool(node, |
| 4359 | "qcom,hsusb-otg-lpm-on-dev-suspend"); |
| 4360 | pdata->core_clk_always_on_workaround = of_property_read_bool(node, |
| 4361 | "qcom,hsusb-otg-clk-always-on-workaround"); |
| 4362 | pdata->delay_lpm_on_disconnect = of_property_read_bool(node, |
| 4363 | "qcom,hsusb-otg-delay-lpm"); |
| 4364 | pdata->dp_manual_pullup = of_property_read_bool(node, |
| 4365 | "qcom,dp-manual-pullup"); |
| 4366 | pdata->enable_sec_phy = of_property_read_bool(node, |
| 4367 | "qcom,usb2-enable-hsphy2"); |
| 4368 | of_property_read_u32(node, "qcom,hsusb-log2-itc", |
| 4369 | &pdata->log2_itc); |
| 4370 | |
| 4371 | of_property_read_u32(node, "qcom,hsusb-otg-mpm-dpsehv-int", |
| 4372 | &pdata->mpm_dpshv_int); |
| 4373 | of_property_read_u32(node, "qcom,hsusb-otg-mpm-dmsehv-int", |
| 4374 | &pdata->mpm_dmshv_int); |
| 4375 | pdata->pmic_id_irq = platform_get_irq_byname(pdev, "pmic_id_irq"); |
| 4376 | if (pdata->pmic_id_irq < 0) |
| 4377 | pdata->pmic_id_irq = 0; |
| 4378 | |
| 4379 | pdata->hub_reset_gpio = of_get_named_gpio( |
| 4380 | node, "qcom,hub-reset-gpio", 0); |
| 4381 | if (!gpio_is_valid(pdata->hub_reset_gpio)) |
| 4382 | pr_debug("hub_reset_gpio is not available\n"); |
| 4383 | |
| 4384 | pdata->usbeth_reset_gpio = of_get_named_gpio( |
| 4385 | node, "qcom,usbeth-reset-gpio", 0); |
| 4386 | if (!gpio_is_valid(pdata->usbeth_reset_gpio)) |
| 4387 | pr_debug("usbeth_reset_gpio is not available\n"); |
| 4388 | |
| 4389 | pdata->switch_sel_gpio = |
| 4390 | of_get_named_gpio(node, "qcom,sw-sel-gpio", 0); |
| 4391 | if (!gpio_is_valid(pdata->switch_sel_gpio)) |
| 4392 | pr_debug("switch_sel_gpio is not available\n"); |
| 4393 | |
| 4394 | pdata->usb_id_gpio = |
| 4395 | of_get_named_gpio(node, "qcom,usbid-gpio", 0); |
| 4396 | if (!gpio_is_valid(pdata->usb_id_gpio)) |
| 4397 | pr_debug("usb_id_gpio is not available\n"); |
| 4398 | |
| 4399 | pdata->l1_supported = of_property_read_bool(node, |
| 4400 | "qcom,hsusb-l1-supported"); |
| 4401 | pdata->enable_ahb2ahb_bypass = of_property_read_bool(node, |
| 4402 | "qcom,ahb-async-bridge-bypass"); |
| 4403 | pdata->disable_retention_with_vdd_min = of_property_read_bool(node, |
| 4404 | "qcom,disable-retention-with-vdd-min"); |
| 4405 | pdata->enable_phy_id_pullup = of_property_read_bool(node, |
| 4406 | "qcom,enable-phy-id-pullup"); |
| 4407 | pdata->phy_dvdd_always_on = of_property_read_bool(node, |
| 4408 | "qcom,phy-dvdd-always-on"); |
| 4409 | |
| 4410 | res_gpio = of_get_named_gpio(node, "qcom,hsusb-otg-vddmin-gpio", 0); |
| 4411 | if (!gpio_is_valid(res_gpio)) |
| 4412 | res_gpio = 0; |
| 4413 | pdata->vddmin_gpio = res_gpio; |
| 4414 | |
| 4415 | pdata->emulation = of_property_read_bool(node, |
| 4416 | "qcom,emulation"); |
| 4417 | |
| 4418 | pdata->enable_streaming = of_property_read_bool(node, |
| 4419 | "qcom,boost-sysclk-with-streaming"); |
| 4420 | |
| 4421 | pdata->enable_axi_prefetch = of_property_read_bool(node, |
| 4422 | "qcom,axi-prefetch-enable"); |
| 4423 | |
| 4424 | pdata->enable_sdp_typec_current_limit = of_property_read_bool(node, |
| 4425 | "qcom,enable-sdp-typec-current-limit"); |
| 4426 | pdata->vbus_low_as_hostmode = of_property_read_bool(node, |
| 4427 | "qcom,vbus-low-as-hostmode"); |
| 4428 | return pdata; |
| 4429 | } |
| 4430 | |
| 4431 | static int msm_otg_probe(struct platform_device *pdev) |
| 4432 | { |
| 4433 | int ret = 0; |
| 4434 | int len = 0; |
| 4435 | u32 tmp[3]; |
| 4436 | struct resource *res; |
| 4437 | struct msm_otg *motg; |
| 4438 | struct usb_phy *phy; |
| 4439 | struct msm_otg_platform_data *pdata; |
| 4440 | void __iomem *tcsr; |
| 4441 | int id_irq = 0; |
| 4442 | |
| 4443 | dev_info(&pdev->dev, "msm_otg probe\n"); |
| 4444 | |
| 4445 | motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL); |
| 4446 | if (!motg) { |
| 4447 | ret = -ENOMEM; |
| 4448 | return ret; |
| 4449 | } |
| 4450 | |
| 4451 | /* |
| 4452 | * USB Core is running its protocol engine based on CORE CLK, |
| 4453 | * CORE CLK must be running at >55Mhz for correct HSUSB |
| 4454 | * operation and USB core cannot tolerate frequency changes on |
| 4455 | * CORE CLK. For such USB cores, vote for maximum clk frequency |
| 4456 | * on pclk source |
| 4457 | */ |
| 4458 | motg->core_clk = clk_get(&pdev->dev, "core_clk"); |
| 4459 | if (IS_ERR(motg->core_clk)) { |
| 4460 | ret = PTR_ERR(motg->core_clk); |
| 4461 | motg->core_clk = NULL; |
| 4462 | if (ret != -EPROBE_DEFER) |
| 4463 | dev_err(&pdev->dev, "failed to get core_clk\n"); |
| 4464 | goto free_motg; |
| 4465 | } |
| 4466 | |
| 4467 | motg->core_reset = devm_reset_control_get(&pdev->dev, "core_reset"); |
| 4468 | if (IS_ERR(motg->core_reset)) { |
| 4469 | dev_err(&pdev->dev, "failed to get core_reset\n"); |
| 4470 | ret = PTR_ERR(motg->core_reset); |
| 4471 | goto put_core_clk; |
| 4472 | } |
| 4473 | |
| 4474 | /* |
| 4475 | * USB Core CLK can run at max freq if streaming is enabled. Hence, |
| 4476 | * get Max supported clk frequency for USB Core CLK and request to set |
| 4477 | * the same. Otherwise set USB Core CLK to defined default value. |
| 4478 | */ |
| 4479 | if (of_property_read_u32(pdev->dev.of_node, |
| 4480 | "qcom,max-nominal-sysclk-rate", &ret)) { |
| 4481 | ret = -EINVAL; |
| 4482 | goto put_core_clk; |
| 4483 | } else { |
| 4484 | motg->core_clk_nominal_rate = clk_round_rate(motg->core_clk, |
| 4485 | ret); |
| 4486 | } |
| 4487 | |
| 4488 | if (of_property_read_u32(pdev->dev.of_node, |
| 4489 | "qcom,max-svs-sysclk-rate", &ret)) { |
| 4490 | dev_dbg(&pdev->dev, "core_clk svs freq not specified\n"); |
| 4491 | } else { |
| 4492 | motg->core_clk_svs_rate = clk_round_rate(motg->core_clk, ret); |
| 4493 | } |
| 4494 | |
| 4495 | motg->default_noc_mode = USB_NOC_NOM_VOTE; |
| 4496 | if (of_property_read_bool(pdev->dev.of_node, "qcom,default-mode-svs")) { |
| 4497 | motg->core_clk_rate = motg->core_clk_svs_rate; |
| 4498 | motg->default_noc_mode = USB_NOC_SVS_VOTE; |
| 4499 | } else if (of_property_read_bool(pdev->dev.of_node, |
| 4500 | "qcom,boost-sysclk-with-streaming")) { |
| 4501 | motg->core_clk_rate = motg->core_clk_nominal_rate; |
| 4502 | } else { |
| 4503 | motg->core_clk_rate = clk_round_rate(motg->core_clk, |
| 4504 | USB_DEFAULT_SYSTEM_CLOCK); |
| 4505 | } |
| 4506 | |
| 4507 | if (IS_ERR_VALUE(motg->core_clk_rate)) { |
| 4508 | dev_err(&pdev->dev, "fail to get core clk max freq.\n"); |
| 4509 | } else { |
| 4510 | ret = clk_set_rate(motg->core_clk, motg->core_clk_rate); |
| 4511 | if (ret) |
| 4512 | dev_err(&pdev->dev, "fail to set core_clk freq:%d\n", |
| 4513 | ret); |
| 4514 | } |
| 4515 | |
| 4516 | motg->pclk = clk_get(&pdev->dev, "iface_clk"); |
| 4517 | if (IS_ERR(motg->pclk)) { |
| 4518 | ret = PTR_ERR(motg->pclk); |
| 4519 | motg->pclk = NULL; |
| 4520 | if (ret != -EPROBE_DEFER) |
| 4521 | dev_err(&pdev->dev, "failed to get iface_clk\n"); |
| 4522 | goto put_core_clk; |
| 4523 | } |
| 4524 | |
| 4525 | motg->xo_clk = clk_get(&pdev->dev, "xo"); |
| 4526 | if (IS_ERR(motg->xo_clk)) { |
| 4527 | ret = PTR_ERR(motg->xo_clk); |
| 4528 | motg->xo_clk = NULL; |
| 4529 | if (ret == -EPROBE_DEFER) |
| 4530 | goto put_pclk; |
| 4531 | } |
| 4532 | |
| 4533 | /* |
| 4534 | * On few platforms USB PHY is fed with sleep clk. |
| 4535 | * Hence don't fail probe. |
| 4536 | */ |
| 4537 | motg->sleep_clk = devm_clk_get(&pdev->dev, "sleep_clk"); |
| 4538 | if (IS_ERR(motg->sleep_clk)) { |
| 4539 | ret = PTR_ERR(motg->sleep_clk); |
| 4540 | motg->sleep_clk = NULL; |
| 4541 | if (ret == -EPROBE_DEFER) |
| 4542 | goto put_xo_clk; |
| 4543 | else |
| 4544 | dev_dbg(&pdev->dev, "failed to get sleep_clk\n"); |
| 4545 | } else { |
| 4546 | ret = clk_prepare_enable(motg->sleep_clk); |
| 4547 | if (ret) { |
| 4548 | dev_err(&pdev->dev, "%s failed to vote sleep_clk%d\n", |
| 4549 | __func__, ret); |
| 4550 | goto put_xo_clk; |
| 4551 | } |
| 4552 | } |
| 4553 | |
| 4554 | /* |
| 4555 | * If present, phy_reset_clk is used to reset the PHY, ULPI bridge |
| 4556 | * and CSR Wrapper. This is a reset only clock. |
| 4557 | */ |
| 4558 | |
| 4559 | if (of_property_match_string(pdev->dev.of_node, |
| 4560 | "clock-names", "phy_reset_clk") >= 0) { |
| 4561 | motg->phy_reset_clk = devm_clk_get(&pdev->dev, "phy_reset_clk"); |
| 4562 | if (IS_ERR(motg->phy_reset_clk)) { |
| 4563 | ret = PTR_ERR(motg->phy_reset_clk); |
| 4564 | goto disable_sleep_clk; |
| 4565 | } |
| 4566 | |
| 4567 | motg->phy_reset = devm_reset_control_get(&pdev->dev, |
| 4568 | "phy_reset"); |
| 4569 | if (IS_ERR(motg->phy_reset)) { |
| 4570 | dev_err(&pdev->dev, "failed to get phy_reset\n"); |
| 4571 | ret = PTR_ERR(motg->phy_reset); |
| 4572 | goto disable_sleep_clk; |
| 4573 | } |
| 4574 | } |
| 4575 | |
| 4576 | /* |
| 4577 | * If present, phy_por_clk is used to assert/de-assert phy POR |
| 4578 | * input. This is a reset only clock. phy POR must be asserted |
| 4579 | * after overriding the parameter registers via CSR wrapper or |
| 4580 | * ULPI bridge. |
| 4581 | */ |
| 4582 | if (of_property_match_string(pdev->dev.of_node, |
| 4583 | "clock-names", "phy_por_clk") >= 0) { |
| 4584 | motg->phy_por_clk = devm_clk_get(&pdev->dev, "phy_por_clk"); |
| 4585 | if (IS_ERR(motg->phy_por_clk)) { |
| 4586 | ret = PTR_ERR(motg->phy_por_clk); |
| 4587 | goto disable_sleep_clk; |
| 4588 | } |
| 4589 | |
| 4590 | motg->phy_por_reset = devm_reset_control_get(&pdev->dev, |
| 4591 | "phy_por_reset"); |
| 4592 | if (IS_ERR(motg->phy_por_reset)) { |
| 4593 | dev_err(&pdev->dev, "failed to get phy_por_reset\n"); |
| 4594 | ret = PTR_ERR(motg->phy_por_reset); |
| 4595 | goto disable_sleep_clk; |
| 4596 | } |
| 4597 | } |
| 4598 | |
| 4599 | /* |
| 4600 | * If present, phy_csr_clk is required for accessing PHY |
| 4601 | * CSR registers via AHB2PHY interface. |
| 4602 | */ |
| 4603 | if (of_property_match_string(pdev->dev.of_node, |
| 4604 | "clock-names", "phy_csr_clk") >= 0) { |
| 4605 | motg->phy_csr_clk = devm_clk_get(&pdev->dev, "phy_csr_clk"); |
| 4606 | if (IS_ERR(motg->phy_csr_clk)) { |
| 4607 | ret = PTR_ERR(motg->phy_csr_clk); |
| 4608 | goto disable_sleep_clk; |
| 4609 | } else { |
| 4610 | ret = clk_prepare_enable(motg->phy_csr_clk); |
| 4611 | if (ret) { |
| 4612 | dev_err(&pdev->dev, |
| 4613 | "fail to enable phy csr clk %d\n", ret); |
| 4614 | goto disable_sleep_clk; |
| 4615 | } |
| 4616 | } |
| 4617 | } |
| 4618 | |
| 4619 | of_property_read_u32(pdev->dev.of_node, "qcom,pm-qos-latency", |
| 4620 | &motg->pm_qos_latency); |
| 4621 | |
| 4622 | pdata = msm_otg_dt_to_pdata(pdev); |
| 4623 | if (!pdata) { |
| 4624 | ret = -ENOMEM; |
| 4625 | goto disable_phy_csr_clk; |
| 4626 | } |
| 4627 | pdev->dev.platform_data = pdata; |
| 4628 | |
| 4629 | pdata->bus_scale_table = msm_bus_cl_get_pdata(pdev); |
| 4630 | if (!pdata->bus_scale_table) |
| 4631 | dev_dbg(&pdev->dev, "bus scaling is disabled\n"); |
| 4632 | |
| 4633 | if (pdata->phy_type == QUSB_ULPI_PHY) { |
| 4634 | if (of_property_match_string(pdev->dev.of_node, |
| 4635 | "clock-names", "phy_ref_clk") >= 0) { |
| 4636 | motg->phy_ref_clk = devm_clk_get(&pdev->dev, |
| 4637 | "phy_ref_clk"); |
| 4638 | if (IS_ERR(motg->phy_ref_clk)) { |
| 4639 | ret = PTR_ERR(motg->phy_ref_clk); |
| 4640 | goto disable_phy_csr_clk; |
| 4641 | } else { |
| 4642 | ret = clk_prepare_enable(motg->phy_ref_clk); |
| 4643 | if (ret) { |
| 4644 | dev_err(&pdev->dev, |
| 4645 | "fail to enable phy ref clk %d\n", |
| 4646 | ret); |
| 4647 | goto disable_phy_csr_clk; |
| 4648 | } |
| 4649 | } |
| 4650 | } |
| 4651 | } |
| 4652 | |
| 4653 | motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
| 4654 | GFP_KERNEL); |
| 4655 | if (!motg->phy.otg) { |
| 4656 | ret = -ENOMEM; |
| 4657 | goto disable_phy_csr_clk; |
| 4658 | } |
| 4659 | |
| 4660 | the_msm_otg = motg; |
| 4661 | motg->pdata = pdata; |
| 4662 | phy = &motg->phy; |
| 4663 | phy->dev = &pdev->dev; |
| 4664 | motg->pdev = pdev; |
| 4665 | motg->dbg_idx = 0; |
| 4666 | motg->dbg_lock = __RW_LOCK_UNLOCKED(lck); |
| 4667 | |
| 4668 | if (motg->pdata->bus_scale_table) { |
| 4669 | motg->bus_perf_client = |
| 4670 | msm_bus_scale_register_client(motg->pdata->bus_scale_table); |
| 4671 | if (!motg->bus_perf_client) { |
| 4672 | dev_err(motg->phy.dev, "%s: Failed to register BUS\n" |
| 4673 | "scaling client!!\n", __func__); |
| 4674 | } else { |
| 4675 | debug_bus_voting_enabled = true; |
| 4676 | /* Some platforms require BUS vote to control clocks */ |
| 4677 | msm_otg_bus_vote(motg, USB_MIN_PERF_VOTE); |
| 4678 | } |
| 4679 | } |
| 4680 | |
| 4681 | ret = msm_otg_bus_freq_get(motg); |
| 4682 | if (ret) { |
| 4683 | pr_err("failed to get noc clocks: %d\n", ret); |
| 4684 | } else { |
| 4685 | ret = msm_otg_bus_freq_set(motg, motg->default_noc_mode); |
| 4686 | if (ret) |
| 4687 | pr_err("failed to vote explicit noc rates: %d\n", ret); |
| 4688 | } |
| 4689 | |
| 4690 | /* initialize reset counter */ |
| 4691 | motg->reset_counter = 0; |
| 4692 | |
| 4693 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); |
| 4694 | if (!res) { |
| 4695 | dev_err(&pdev->dev, "failed to get core iomem resource\n"); |
| 4696 | ret = -ENODEV; |
| 4697 | goto devote_bus_bw; |
| 4698 | } |
| 4699 | |
| 4700 | motg->io_res = res; |
| 4701 | motg->regs = ioremap(res->start, resource_size(res)); |
| 4702 | if (!motg->regs) { |
| 4703 | dev_err(&pdev->dev, "core iomem ioremap failed\n"); |
| 4704 | ret = -ENOMEM; |
| 4705 | goto devote_bus_bw; |
| 4706 | } |
| 4707 | dev_info(&pdev->dev, "OTG regs = %pK\n", motg->regs); |
| 4708 | |
| 4709 | if (pdata->enable_sec_phy) { |
| 4710 | res = platform_get_resource_byname(pdev, |
| 4711 | IORESOURCE_MEM, "tcsr"); |
| 4712 | if (!res) { |
| 4713 | dev_dbg(&pdev->dev, "missing TCSR memory resource\n"); |
| 4714 | } else { |
| 4715 | tcsr = devm_ioremap_nocache(&pdev->dev, res->start, |
| 4716 | resource_size(res)); |
| 4717 | if (!tcsr) { |
| 4718 | dev_dbg(&pdev->dev, "tcsr ioremap failed\n"); |
| 4719 | } else { |
| 4720 | /* Enable USB2 on secondary HSPHY. */ |
| 4721 | writel_relaxed(0x1, tcsr); |
| 4722 | /* |
| 4723 | * Ensure that TCSR write is completed before |
| 4724 | * USB registers initialization. |
| 4725 | */ |
| 4726 | mb(); |
| 4727 | } |
| 4728 | } |
| 4729 | } |
| 4730 | |
| 4731 | if (pdata->enable_sec_phy) |
| 4732 | motg->usb_phy_ctrl_reg = USB_PHY_CTRL2; |
| 4733 | else |
| 4734 | motg->usb_phy_ctrl_reg = USB_PHY_CTRL; |
| 4735 | |
| 4736 | /* |
| 4737 | * The USB PHY wrapper provides a register interface |
| 4738 | * through AHB2PHY for performing PHY related operations |
| 4739 | * like retention, HV interrupts and overriding parameter |
| 4740 | * registers etc. The registers start at 4 byte boundary |
| 4741 | * but only the first byte is valid and remaining are not |
| 4742 | * used. Relaxed versions of readl/writel should be used. |
| 4743 | * |
| 4744 | * The link does not have any PHY specific registers. |
| 4745 | * Hence set motg->usb_phy_ctrl_reg to. |
| 4746 | */ |
| 4747 | if (motg->pdata->phy_type == SNPS_FEMTO_PHY || |
| 4748 | pdata->phy_type == QUSB_ULPI_PHY) { |
| 4749 | res = platform_get_resource_byname(pdev, |
| 4750 | IORESOURCE_MEM, "phy_csr"); |
| 4751 | if (!res) { |
| 4752 | dev_err(&pdev->dev, "PHY CSR IOMEM missing!\n"); |
| 4753 | ret = -ENODEV; |
| 4754 | goto free_regs; |
| 4755 | } |
| 4756 | motg->phy_csr_regs = devm_ioremap_resource(&pdev->dev, res); |
| 4757 | if (IS_ERR(motg->phy_csr_regs)) { |
| 4758 | ret = PTR_ERR(motg->phy_csr_regs); |
| 4759 | dev_err(&pdev->dev, "PHY CSR ioremap failed!\n"); |
| 4760 | goto free_regs; |
| 4761 | } |
| 4762 | motg->usb_phy_ctrl_reg = 0; |
| 4763 | } |
| 4764 | |
| 4765 | motg->irq = platform_get_irq(pdev, 0); |
| 4766 | if (!motg->irq) { |
| 4767 | dev_err(&pdev->dev, "platform_get_irq failed\n"); |
| 4768 | ret = -ENODEV; |
| 4769 | goto free_regs; |
| 4770 | } |
| 4771 | |
| 4772 | motg->async_irq = platform_get_irq_byname(pdev, "async_irq"); |
| 4773 | if (motg->async_irq < 0) { |
| 4774 | dev_err(&pdev->dev, "platform_get_irq for async_int failed\n"); |
| 4775 | motg->async_irq = 0; |
| 4776 | goto free_regs; |
| 4777 | } |
| 4778 | |
| 4779 | if (motg->xo_clk) { |
| 4780 | ret = clk_prepare_enable(motg->xo_clk); |
| 4781 | if (ret) { |
| 4782 | dev_err(&pdev->dev, |
| 4783 | "%s failed to vote for TCXO %d\n", |
| 4784 | __func__, ret); |
| 4785 | goto free_xo_handle; |
| 4786 | } |
| 4787 | } |
| 4788 | |
| 4789 | |
| 4790 | clk_prepare_enable(motg->pclk); |
| 4791 | |
| 4792 | hsusb_vdd = devm_regulator_get(motg->phy.dev, "hsusb_vdd_dig"); |
| 4793 | if (IS_ERR(hsusb_vdd)) { |
| 4794 | hsusb_vdd = devm_regulator_get(motg->phy.dev, "HSUSB_VDDCX"); |
| 4795 | if (IS_ERR(hsusb_vdd)) { |
| 4796 | dev_err(motg->phy.dev, "unable to get hsusb vddcx\n"); |
| 4797 | ret = PTR_ERR(hsusb_vdd); |
| 4798 | goto devote_xo_handle; |
| 4799 | } |
| 4800 | } |
| 4801 | |
| 4802 | len = of_property_count_elems_of_size(pdev->dev.of_node, |
| 4803 | "qcom,vdd-voltage-level", sizeof(len)); |
| 4804 | if (len > 0) { |
| 4805 | if (len == sizeof(tmp) / sizeof(len)) { |
| 4806 | of_property_read_u32_array(pdev->dev.of_node, |
| 4807 | "qcom,vdd-voltage-level", |
| 4808 | tmp, len); |
| 4809 | vdd_val[0] = tmp[0]; |
| 4810 | vdd_val[1] = tmp[1]; |
| 4811 | vdd_val[2] = tmp[2]; |
| 4812 | } else { |
| 4813 | dev_dbg(&pdev->dev, |
| 4814 | "Using default hsusb vdd config.\n"); |
| 4815 | goto devote_xo_handle; |
| 4816 | } |
| 4817 | } else { |
| 4818 | goto devote_xo_handle; |
| 4819 | } |
| 4820 | |
| 4821 | ret = msm_hsusb_config_vddcx(1); |
| 4822 | if (ret) { |
| 4823 | dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); |
| 4824 | goto devote_xo_handle; |
| 4825 | } |
| 4826 | |
| 4827 | ret = regulator_enable(hsusb_vdd); |
| 4828 | if (ret) { |
| 4829 | dev_err(&pdev->dev, "unable to enable the hsusb vddcx\n"); |
| 4830 | goto free_config_vddcx; |
| 4831 | } |
| 4832 | |
| 4833 | ret = msm_hsusb_ldo_init(motg, 1); |
| 4834 | if (ret) { |
| 4835 | dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); |
| 4836 | goto free_hsusb_vdd; |
| 4837 | } |
| 4838 | |
| 4839 | /* Get pinctrl if target uses pinctrl */ |
| 4840 | motg->phy_pinctrl = devm_pinctrl_get(&pdev->dev); |
| 4841 | if (IS_ERR(motg->phy_pinctrl)) { |
| 4842 | if (of_property_read_bool(pdev->dev.of_node, "pinctrl-names")) { |
| 4843 | dev_err(&pdev->dev, "Error encountered while getting pinctrl"); |
| 4844 | ret = PTR_ERR(motg->phy_pinctrl); |
| 4845 | goto free_ldo_init; |
| 4846 | } |
| 4847 | dev_dbg(&pdev->dev, "Target does not use pinctrl\n"); |
| 4848 | motg->phy_pinctrl = NULL; |
| 4849 | } |
| 4850 | |
| 4851 | ret = msm_hsusb_ldo_enable(motg, USB_PHY_REG_ON); |
| 4852 | if (ret) { |
| 4853 | dev_err(&pdev->dev, "hsusb vreg enable failed\n"); |
| 4854 | goto free_ldo_init; |
| 4855 | } |
| 4856 | clk_prepare_enable(motg->core_clk); |
| 4857 | |
| 4858 | /* Check if USB mem_type change is needed to workaround PNOC hw issue */ |
| 4859 | msm_otg_pnoc_errata_fix(motg); |
| 4860 | |
| 4861 | writel_relaxed(0, USB_USBINTR); |
| 4862 | writel_relaxed(0, USB_OTGSC); |
| 4863 | /* Ensure that above STOREs are completed before enabling interrupts */ |
| 4864 | mb(); |
| 4865 | |
| 4866 | motg->id_state = USB_ID_FLOAT; |
| 4867 | set_bit(ID, &motg->inputs); |
| 4868 | INIT_WORK(&motg->sm_work, msm_otg_sm_work); |
| 4869 | INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work); |
| 4870 | INIT_DELAYED_WORK(&motg->id_status_work, msm_id_status_w); |
| 4871 | INIT_DELAYED_WORK(&motg->perf_vote_work, msm_otg_perf_vote_work); |
| 4872 | setup_timer(&motg->chg_check_timer, msm_otg_chg_check_timer_func, |
| 4873 | (unsigned long) motg); |
| 4874 | motg->otg_wq = alloc_ordered_workqueue("k_otg", 0); |
| 4875 | if (!motg->otg_wq) { |
| 4876 | pr_err("%s: Unable to create workqueue otg_wq\n", |
| 4877 | __func__); |
| 4878 | goto disable_core_clk; |
| 4879 | } |
| 4880 | |
| 4881 | ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED, |
| 4882 | "msm_otg", motg); |
| 4883 | if (ret) { |
| 4884 | dev_err(&pdev->dev, "request irq failed\n"); |
| 4885 | goto destroy_wq; |
| 4886 | } |
| 4887 | |
| 4888 | motg->phy_irq = platform_get_irq_byname(pdev, "phy_irq"); |
| 4889 | if (motg->phy_irq < 0) { |
| 4890 | dev_dbg(&pdev->dev, "phy_irq is not present\n"); |
| 4891 | motg->phy_irq = 0; |
| 4892 | } else { |
| 4893 | |
| 4894 | /* clear all interrupts before enabling the IRQ */ |
| 4895 | writeb_relaxed(0xFF, USB2_PHY_USB_PHY_INTERRUPT_CLEAR0); |
| 4896 | writeb_relaxed(0xFF, USB2_PHY_USB_PHY_INTERRUPT_CLEAR1); |
| 4897 | |
| 4898 | writeb_relaxed(0x1, USB2_PHY_USB_PHY_IRQ_CMD); |
| 4899 | /* |
| 4900 | * Databook says 200 usec delay is required for |
| 4901 | * clearing the interrupts. |
| 4902 | */ |
| 4903 | udelay(200); |
| 4904 | writeb_relaxed(0x0, USB2_PHY_USB_PHY_IRQ_CMD); |
| 4905 | |
| 4906 | ret = request_irq(motg->phy_irq, msm_otg_phy_irq_handler, |
| 4907 | IRQF_TRIGGER_RISING, "msm_otg_phy_irq", motg); |
| 4908 | if (ret < 0) { |
| 4909 | dev_err(&pdev->dev, "phy_irq request fail %d\n", ret); |
| 4910 | goto free_irq; |
| 4911 | } |
| 4912 | } |
| 4913 | |
| 4914 | ret = request_irq(motg->async_irq, msm_otg_irq, |
| 4915 | IRQF_TRIGGER_RISING, "msm_otg", motg); |
| 4916 | if (ret) { |
| 4917 | dev_err(&pdev->dev, "request irq failed (ASYNC INT)\n"); |
| 4918 | goto free_phy_irq; |
| 4919 | } |
| 4920 | disable_irq(motg->async_irq); |
| 4921 | |
| 4922 | if (pdata->otg_control == OTG_PHY_CONTROL && pdata->mpm_otgsessvld_int) |
| 4923 | msm_mpm_enable_pin(pdata->mpm_otgsessvld_int, 1); |
| 4924 | |
| 4925 | if (pdata->mpm_dpshv_int) |
| 4926 | msm_mpm_enable_pin(pdata->mpm_dpshv_int, 1); |
| 4927 | if (pdata->mpm_dmshv_int) |
| 4928 | msm_mpm_enable_pin(pdata->mpm_dmshv_int, 1); |
| 4929 | |
| 4930 | phy->init = msm_otg_reset; |
| 4931 | phy->set_power = msm_otg_set_power; |
| 4932 | phy->set_suspend = msm_otg_set_suspend; |
| 4933 | phy->dbg_event = msm_otg_dbg_log_event; |
| 4934 | |
| 4935 | phy->io_ops = &msm_otg_io_ops; |
| 4936 | |
| 4937 | phy->otg->usb_phy = &motg->phy; |
| 4938 | phy->otg->set_host = msm_otg_set_host; |
| 4939 | phy->otg->set_peripheral = msm_otg_set_peripheral; |
| 4940 | if (pdata->dp_manual_pullup) |
| 4941 | phy->flags |= ENABLE_DP_MANUAL_PULLUP; |
| 4942 | |
| 4943 | if (pdata->enable_sec_phy) |
| 4944 | phy->flags |= ENABLE_SECONDARY_PHY; |
| 4945 | |
| 4946 | ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2); |
| 4947 | if (ret) { |
| 4948 | dev_err(&pdev->dev, "usb_add_phy failed\n"); |
| 4949 | goto free_async_irq; |
| 4950 | } |
| 4951 | |
| 4952 | ret = usb_phy_regulator_init(motg); |
| 4953 | if (ret) { |
| 4954 | dev_err(&pdev->dev, "usb_phy_regulator_init failed\n"); |
| 4955 | goto remove_phy; |
| 4956 | } |
| 4957 | |
| 4958 | if (motg->pdata->mode == USB_OTG && |
| 4959 | motg->pdata->otg_control == OTG_PMIC_CONTROL && |
| 4960 | !motg->phy_irq) { |
| 4961 | |
| 4962 | if (gpio_is_valid(motg->pdata->usb_id_gpio)) { |
| 4963 | /* usb_id_gpio request */ |
| 4964 | ret = gpio_request(motg->pdata->usb_id_gpio, |
| 4965 | "USB_ID_GPIO"); |
| 4966 | if (ret < 0) { |
| 4967 | dev_err(&pdev->dev, "gpio req failed for id\n"); |
| 4968 | motg->pdata->usb_id_gpio = 0; |
| 4969 | goto remove_phy; |
| 4970 | } |
| 4971 | |
| 4972 | /* |
| 4973 | * The following code implements switch between the HOST |
| 4974 | * mode to device mode when used different HW components |
| 4975 | * on the same port: USB HUB and the usb jack type B |
| 4976 | * for device mode In this case HUB should be gone |
| 4977 | * only once out of reset at the boot time and after |
| 4978 | * that always stay on |
| 4979 | */ |
| 4980 | if (gpio_is_valid(motg->pdata->hub_reset_gpio)) { |
| 4981 | ret = devm_gpio_request(&pdev->dev, |
| 4982 | motg->pdata->hub_reset_gpio, |
| 4983 | "qcom,hub-reset-gpio"); |
| 4984 | if (ret < 0) { |
| 4985 | dev_err(&pdev->dev, "gpio req failed for hub reset\n"); |
| 4986 | goto remove_phy; |
| 4987 | } |
| 4988 | gpio_direction_output( |
| 4989 | motg->pdata->hub_reset_gpio, 1); |
| 4990 | } |
| 4991 | |
| 4992 | if (gpio_is_valid(motg->pdata->switch_sel_gpio)) { |
| 4993 | ret = devm_gpio_request(&pdev->dev, |
| 4994 | motg->pdata->switch_sel_gpio, |
| 4995 | "qcom,sw-sel-gpio"); |
| 4996 | if (ret < 0) { |
| 4997 | dev_err(&pdev->dev, "gpio req failed for switch sel\n"); |
| 4998 | goto remove_phy; |
| 4999 | } |
| 5000 | if (gpio_get_value(motg->pdata->usb_id_gpio)) |
| 5001 | gpio_direction_input( |
| 5002 | motg->pdata->switch_sel_gpio); |
| 5003 | |
| 5004 | else |
| 5005 | gpio_direction_output( |
| 5006 | motg->pdata->switch_sel_gpio, |
| 5007 | 1); |
| 5008 | } |
| 5009 | |
| 5010 | /* usb_id_gpio to irq */ |
| 5011 | id_irq = gpio_to_irq(motg->pdata->usb_id_gpio); |
| 5012 | motg->ext_id_irq = id_irq; |
| 5013 | } else if (motg->pdata->pmic_id_irq) { |
| 5014 | id_irq = motg->pdata->pmic_id_irq; |
| 5015 | } |
| 5016 | |
| 5017 | if (id_irq) { |
| 5018 | ret = request_irq(id_irq, |
| 5019 | msm_id_irq, |
| 5020 | IRQF_TRIGGER_RISING | |
| 5021 | IRQF_TRIGGER_FALLING, |
| 5022 | "msm_otg", motg); |
| 5023 | if (ret) { |
| 5024 | dev_err(&pdev->dev, "request irq failed for ID\n"); |
| 5025 | goto remove_phy; |
| 5026 | } |
| 5027 | } else { |
| 5028 | /* PMIC does USB ID detection and notifies through |
| 5029 | * USB_OTG property of USB powersupply. |
| 5030 | */ |
| 5031 | dev_dbg(&pdev->dev, "PMIC does ID detection\n"); |
| 5032 | } |
| 5033 | } |
| 5034 | |
| 5035 | platform_set_drvdata(pdev, motg); |
| 5036 | device_init_wakeup(&pdev->dev, 1); |
| 5037 | |
| 5038 | ret = msm_otg_debugfs_init(motg); |
| 5039 | if (ret) |
| 5040 | dev_dbg(&pdev->dev, "mode debugfs file is not available\n"); |
| 5041 | |
| 5042 | if (motg->pdata->otg_control == OTG_PMIC_CONTROL && |
| 5043 | (!(motg->pdata->mode == USB_OTG) || |
| 5044 | motg->pdata->pmic_id_irq || motg->ext_id_irq || |
| 5045 | !motg->phy_irq)) |
| 5046 | motg->caps = ALLOW_PHY_POWER_COLLAPSE | ALLOW_PHY_RETENTION; |
| 5047 | |
| 5048 | if (motg->pdata->otg_control == OTG_PHY_CONTROL || motg->phy_irq || |
| 5049 | motg->pdata->enable_phy_id_pullup) |
| 5050 | motg->caps = ALLOW_PHY_RETENTION | ALLOW_PHY_REGULATORS_LPM; |
| 5051 | |
| 5052 | if (motg->pdata->mpm_dpshv_int || motg->pdata->mpm_dmshv_int) |
| 5053 | motg->caps |= ALLOW_HOST_PHY_RETENTION; |
| 5054 | |
| 5055 | device_create_file(&pdev->dev, &dev_attr_dpdm_pulldown_enable); |
| 5056 | |
| 5057 | if (motg->pdata->enable_lpm_on_dev_suspend) |
| 5058 | motg->caps |= ALLOW_LPM_ON_DEV_SUSPEND; |
| 5059 | |
| 5060 | if (motg->pdata->disable_retention_with_vdd_min) |
| 5061 | motg->caps |= ALLOW_VDD_MIN_WITH_RETENTION_DISABLED; |
| 5062 | |
| 5063 | /* |
| 5064 | * PHY DVDD is supplied by a always on PMIC LDO (unlike |
| 5065 | * vddcx/vddmx). PHY can keep D+ pull-up and D+/D- |
| 5066 | * pull-down during suspend without any additional |
| 5067 | * hardware re-work. |
| 5068 | */ |
| 5069 | if (motg->pdata->phy_type == SNPS_FEMTO_PHY) |
| 5070 | motg->caps |= ALLOW_BUS_SUSPEND_WITHOUT_REWORK; |
| 5071 | |
| 5072 | pm_stay_awake(&pdev->dev); |
| 5073 | pm_runtime_set_active(&pdev->dev); |
| 5074 | pm_runtime_enable(&pdev->dev); |
| 5075 | |
| 5076 | if (motg->pdata->delay_lpm_on_disconnect) { |
| 5077 | pm_runtime_set_autosuspend_delay(&pdev->dev, |
| 5078 | lpm_disconnect_thresh); |
| 5079 | pm_runtime_use_autosuspend(&pdev->dev); |
| 5080 | } |
| 5081 | |
| 5082 | ret = msm_otg_setup_ext_chg_cdev(motg); |
| 5083 | if (ret) |
| 5084 | dev_dbg(&pdev->dev, "fail to setup cdev\n"); |
| 5085 | |
| 5086 | if (pdev->dev.of_node) { |
| 5087 | ret = msm_otg_setup_devices(pdev, pdata->mode, true); |
| 5088 | if (ret) { |
| 5089 | dev_err(&pdev->dev, "devices setup failed\n"); |
| 5090 | goto remove_cdev; |
| 5091 | } |
| 5092 | } |
| 5093 | |
| 5094 | psy = power_supply_get_by_name("usb"); |
| 5095 | if (!psy) { |
| 5096 | dev_dbg(&pdev->dev, "Could not get usb power_supply\n"); |
| 5097 | ret = -EPROBE_DEFER; |
| 5098 | goto otg_remove_devices; |
| 5099 | } |
| 5100 | |
| 5101 | |
| 5102 | ret = msm_otg_extcon_register(motg); |
| 5103 | if (ret) |
| 5104 | goto put_psy; |
| 5105 | |
| 5106 | if (motg->extcon_vbus) { |
| 5107 | ret = extcon_get_cable_state_(motg->extcon_vbus, EXTCON_USB); |
| 5108 | if (ret) |
| 5109 | set_bit(B_SESS_VLD, &motg->inputs); |
| 5110 | else |
| 5111 | clear_bit(B_SESS_VLD, &motg->inputs); |
| 5112 | } |
| 5113 | |
| 5114 | if (motg->extcon_id) { |
| 5115 | ret = extcon_get_cable_state_(motg->extcon_id, EXTCON_USB_HOST); |
| 5116 | if (ret) |
| 5117 | clear_bit(ID, &motg->inputs); |
| 5118 | else |
| 5119 | set_bit(ID, &motg->inputs); |
| 5120 | } |
| 5121 | |
| 5122 | if (gpio_is_valid(motg->pdata->hub_reset_gpio)) { |
| 5123 | ret = devm_gpio_request(&pdev->dev, |
| 5124 | motg->pdata->hub_reset_gpio, |
| 5125 | "HUB_RESET"); |
| 5126 | if (ret < 0) { |
| 5127 | dev_err(&pdev->dev, "gpio req failed for hub_reset\n"); |
| 5128 | } else { |
| 5129 | gpio_direction_output( |
| 5130 | motg->pdata->hub_reset_gpio, 0); |
| 5131 | /* 5 microsecs reset signaling to usb hub */ |
| 5132 | usleep_range(5, 10); |
| 5133 | gpio_direction_output( |
| 5134 | motg->pdata->hub_reset_gpio, 1); |
| 5135 | } |
| 5136 | } |
| 5137 | |
| 5138 | if (gpio_is_valid(motg->pdata->usbeth_reset_gpio)) { |
| 5139 | ret = devm_gpio_request(&pdev->dev, |
| 5140 | motg->pdata->usbeth_reset_gpio, |
| 5141 | "ETH_RESET"); |
| 5142 | if (ret < 0) { |
| 5143 | dev_err(&pdev->dev, "gpio req failed for usbeth_reset\n"); |
| 5144 | } else { |
| 5145 | gpio_direction_output( |
| 5146 | motg->pdata->usbeth_reset_gpio, 0); |
| 5147 | /* 100 microsecs reset signaling to usb-to-eth */ |
| 5148 | usleep_range(100, 110); |
| 5149 | gpio_direction_output( |
| 5150 | motg->pdata->usbeth_reset_gpio, 1); |
| 5151 | } |
| 5152 | } |
| 5153 | |
| 5154 | motg->pm_notify.notifier_call = msm_otg_pm_notify; |
| 5155 | register_pm_notifier(&motg->pm_notify); |
| 5156 | msm_otg_dbg_log_event(phy, "OTG PROBE", motg->caps, motg->lpm_flags); |
| 5157 | |
| 5158 | return 0; |
| 5159 | |
| 5160 | put_psy: |
| 5161 | if (psy) |
| 5162 | power_supply_put(psy); |
| 5163 | otg_remove_devices: |
| 5164 | if (pdev->dev.of_node) |
| 5165 | msm_otg_setup_devices(pdev, motg->pdata->mode, false); |
| 5166 | remove_cdev: |
| 5167 | if (!motg->ext_chg_device) { |
| 5168 | device_destroy(motg->ext_chg_class, motg->ext_chg_dev); |
| 5169 | cdev_del(&motg->ext_chg_cdev); |
| 5170 | class_destroy(motg->ext_chg_class); |
| 5171 | unregister_chrdev_region(motg->ext_chg_dev, 1); |
| 5172 | } |
| 5173 | remove_phy: |
| 5174 | usb_remove_phy(&motg->phy); |
| 5175 | free_async_irq: |
| 5176 | free_irq(motg->async_irq, motg); |
| 5177 | free_phy_irq: |
| 5178 | if (motg->phy_irq) |
| 5179 | free_irq(motg->phy_irq, motg); |
| 5180 | free_irq: |
| 5181 | free_irq(motg->irq, motg); |
| 5182 | destroy_wq: |
| 5183 | destroy_workqueue(motg->otg_wq); |
| 5184 | disable_core_clk: |
| 5185 | clk_disable_unprepare(motg->core_clk); |
| 5186 | msm_hsusb_ldo_enable(motg, USB_PHY_REG_OFF); |
| 5187 | free_ldo_init: |
| 5188 | msm_hsusb_ldo_init(motg, 0); |
| 5189 | free_hsusb_vdd: |
| 5190 | regulator_disable(hsusb_vdd); |
| 5191 | free_config_vddcx: |
| 5192 | regulator_set_voltage(hsusb_vdd, |
| 5193 | vdd_val[VDD_NONE], |
| 5194 | vdd_val[VDD_MAX]); |
| 5195 | devote_xo_handle: |
| 5196 | clk_disable_unprepare(motg->pclk); |
| 5197 | if (motg->xo_clk) |
| 5198 | clk_disable_unprepare(motg->xo_clk); |
| 5199 | free_xo_handle: |
| 5200 | if (motg->xo_clk) { |
| 5201 | clk_put(motg->xo_clk); |
| 5202 | motg->xo_clk = NULL; |
| 5203 | } |
| 5204 | free_regs: |
| 5205 | iounmap(motg->regs); |
| 5206 | devote_bus_bw: |
| 5207 | if (motg->bus_perf_client) { |
| 5208 | msm_otg_bus_vote(motg, USB_NO_PERF_VOTE); |
| 5209 | msm_bus_scale_unregister_client(motg->bus_perf_client); |
| 5210 | } |
| 5211 | disable_phy_csr_clk: |
| 5212 | if (motg->phy_csr_clk) |
| 5213 | clk_disable_unprepare(motg->phy_csr_clk); |
| 5214 | disable_sleep_clk: |
| 5215 | if (motg->sleep_clk) |
| 5216 | clk_disable_unprepare(motg->sleep_clk); |
| 5217 | put_xo_clk: |
| 5218 | if (motg->xo_clk) |
| 5219 | clk_put(motg->xo_clk); |
| 5220 | put_pclk: |
| 5221 | if (motg->pclk) |
| 5222 | clk_put(motg->pclk); |
| 5223 | put_core_clk: |
| 5224 | if (motg->core_clk) |
| 5225 | clk_put(motg->core_clk); |
| 5226 | free_motg: |
| 5227 | kfree(motg); |
| 5228 | return ret; |
| 5229 | } |
| 5230 | |
| 5231 | static int msm_otg_remove(struct platform_device *pdev) |
| 5232 | { |
| 5233 | struct msm_otg *motg = platform_get_drvdata(pdev); |
| 5234 | struct usb_phy *phy = &motg->phy; |
| 5235 | int cnt = 0; |
| 5236 | |
| 5237 | if (phy->otg->host || phy->otg->gadget) |
| 5238 | return -EBUSY; |
| 5239 | |
| 5240 | unregister_pm_notifier(&motg->pm_notify); |
| 5241 | |
| 5242 | extcon_unregister_notifier(motg->extcon_id, EXTCON_USB_HOST, |
| 5243 | &motg->id_nb); |
| 5244 | extcon_unregister_notifier(motg->extcon_vbus, EXTCON_USB, |
| 5245 | &motg->vbus_nb); |
| 5246 | |
| 5247 | if (!motg->ext_chg_device) { |
| 5248 | device_destroy(motg->ext_chg_class, motg->ext_chg_dev); |
| 5249 | cdev_del(&motg->ext_chg_cdev); |
| 5250 | class_destroy(motg->ext_chg_class); |
| 5251 | unregister_chrdev_region(motg->ext_chg_dev, 1); |
| 5252 | } |
| 5253 | |
| 5254 | if (pdev->dev.of_node) |
| 5255 | msm_otg_setup_devices(pdev, motg->pdata->mode, false); |
| 5256 | if (psy) |
| 5257 | power_supply_put(psy); |
| 5258 | msm_otg_debugfs_cleanup(); |
| 5259 | cancel_delayed_work_sync(&motg->chg_work); |
| 5260 | cancel_delayed_work_sync(&motg->id_status_work); |
| 5261 | cancel_delayed_work_sync(&motg->perf_vote_work); |
| 5262 | msm_otg_perf_vote_update(motg, false); |
| 5263 | cancel_work_sync(&motg->sm_work); |
| 5264 | destroy_workqueue(motg->otg_wq); |
| 5265 | |
| 5266 | pm_runtime_resume(&pdev->dev); |
| 5267 | |
| 5268 | device_init_wakeup(&pdev->dev, 0); |
| 5269 | pm_runtime_disable(&pdev->dev); |
| 5270 | |
| 5271 | if (motg->phy_irq) |
| 5272 | free_irq(motg->phy_irq, motg); |
| 5273 | if (motg->pdata->pmic_id_irq) |
| 5274 | free_irq(motg->pdata->pmic_id_irq, motg); |
| 5275 | usb_remove_phy(phy); |
| 5276 | free_irq(motg->irq, motg); |
| 5277 | |
| 5278 | if (motg->pdata->mpm_dpshv_int || motg->pdata->mpm_dmshv_int) |
| 5279 | device_remove_file(&pdev->dev, |
| 5280 | &dev_attr_dpdm_pulldown_enable); |
| 5281 | if (motg->pdata->otg_control == OTG_PHY_CONTROL && |
| 5282 | motg->pdata->mpm_otgsessvld_int) |
| 5283 | msm_mpm_enable_pin(motg->pdata->mpm_otgsessvld_int, 0); |
| 5284 | |
| 5285 | if (motg->pdata->mpm_dpshv_int) |
| 5286 | msm_mpm_enable_pin(motg->pdata->mpm_dpshv_int, 0); |
| 5287 | if (motg->pdata->mpm_dmshv_int) |
| 5288 | msm_mpm_enable_pin(motg->pdata->mpm_dmshv_int, 0); |
| 5289 | |
| 5290 | /* |
| 5291 | * Put PHY in low power mode. |
| 5292 | */ |
| 5293 | ulpi_read(phy, 0x14); |
| 5294 | ulpi_write(phy, 0x08, 0x09); |
| 5295 | |
| 5296 | writel_relaxed(readl_relaxed(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); |
| 5297 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { |
| 5298 | if (readl_relaxed(USB_PORTSC) & PORTSC_PHCD) |
| 5299 | break; |
| 5300 | udelay(1); |
| 5301 | cnt++; |
| 5302 | } |
| 5303 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) |
| 5304 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
| 5305 | |
| 5306 | clk_disable_unprepare(motg->pclk); |
| 5307 | clk_disable_unprepare(motg->core_clk); |
| 5308 | if (motg->phy_csr_clk) |
| 5309 | clk_disable_unprepare(motg->phy_csr_clk); |
| 5310 | if (motg->xo_clk) { |
| 5311 | clk_disable_unprepare(motg->xo_clk); |
| 5312 | clk_put(motg->xo_clk); |
| 5313 | } |
| 5314 | |
| 5315 | if (!IS_ERR(motg->sleep_clk)) |
| 5316 | clk_disable_unprepare(motg->sleep_clk); |
| 5317 | |
| 5318 | msm_hsusb_ldo_enable(motg, USB_PHY_REG_OFF); |
| 5319 | msm_hsusb_ldo_init(motg, 0); |
| 5320 | regulator_disable(hsusb_vdd); |
| 5321 | regulator_set_voltage(hsusb_vdd, |
| 5322 | vdd_val[VDD_NONE], |
| 5323 | vdd_val[VDD_MAX]); |
| 5324 | |
| 5325 | iounmap(motg->regs); |
| 5326 | pm_runtime_set_suspended(&pdev->dev); |
| 5327 | |
| 5328 | clk_put(motg->pclk); |
| 5329 | clk_put(motg->core_clk); |
| 5330 | |
| 5331 | if (motg->bus_perf_client) { |
| 5332 | msm_otg_bus_vote(motg, USB_NO_PERF_VOTE); |
| 5333 | msm_bus_scale_unregister_client(motg->bus_perf_client); |
| 5334 | } |
| 5335 | |
| 5336 | return 0; |
| 5337 | } |
| 5338 | |
| 5339 | static void msm_otg_shutdown(struct platform_device *pdev) |
| 5340 | { |
| 5341 | struct msm_otg *motg = platform_get_drvdata(pdev); |
| 5342 | |
| 5343 | dev_dbg(&pdev->dev, "OTG shutdown\n"); |
| 5344 | msm_hsusb_vbus_power(motg, 0); |
| 5345 | } |
| 5346 | |
| 5347 | #ifdef CONFIG_PM |
| 5348 | static int msm_otg_runtime_idle(struct device *dev) |
| 5349 | { |
| 5350 | struct msm_otg *motg = dev_get_drvdata(dev); |
| 5351 | struct usb_phy *phy = &motg->phy; |
| 5352 | |
| 5353 | dev_dbg(dev, "OTG runtime idle\n"); |
| 5354 | msm_otg_dbg_log_event(phy, "RUNTIME IDLE", |
| 5355 | phy->otg->state, motg->ext_chg_active); |
| 5356 | |
| 5357 | if (phy->otg->state == OTG_STATE_UNDEFINED) |
| 5358 | return -EAGAIN; |
| 5359 | |
| 5360 | if (motg->ext_chg_active == DEFAULT) { |
| 5361 | dev_dbg(dev, "Deferring LPM\n"); |
| 5362 | /* |
| 5363 | * Charger detection may happen in user space. |
| 5364 | * Delay entering LPM by 3 sec. Otherwise we |
| 5365 | * have to exit LPM when user space begins |
| 5366 | * charger detection. |
| 5367 | * |
| 5368 | * This timer will be canceled when user space |
| 5369 | * votes against LPM by incrementing PM usage |
| 5370 | * counter. We enter low power mode when |
| 5371 | * PM usage counter is decremented. |
| 5372 | */ |
| 5373 | pm_schedule_suspend(dev, 3000); |
| 5374 | return -EAGAIN; |
| 5375 | } |
| 5376 | |
| 5377 | return 0; |
| 5378 | } |
| 5379 | |
| 5380 | static int msm_otg_runtime_suspend(struct device *dev) |
| 5381 | { |
| 5382 | struct msm_otg *motg = dev_get_drvdata(dev); |
| 5383 | |
| 5384 | dev_dbg(dev, "OTG runtime suspend\n"); |
| 5385 | msm_otg_dbg_log_event(&motg->phy, "RUNTIME SUSPEND", |
| 5386 | get_pm_runtime_counter(dev), 0); |
| 5387 | return msm_otg_suspend(motg); |
| 5388 | } |
| 5389 | |
| 5390 | static int msm_otg_runtime_resume(struct device *dev) |
| 5391 | { |
| 5392 | struct msm_otg *motg = dev_get_drvdata(dev); |
| 5393 | |
| 5394 | dev_dbg(dev, "OTG runtime resume\n"); |
| 5395 | msm_otg_dbg_log_event(&motg->phy, "RUNTIME RESUME", |
| 5396 | get_pm_runtime_counter(dev), 0); |
| 5397 | |
| 5398 | return msm_otg_resume(motg); |
| 5399 | } |
| 5400 | #endif |
| 5401 | |
| 5402 | #ifdef CONFIG_PM_SLEEP |
| 5403 | static int msm_otg_pm_suspend(struct device *dev) |
| 5404 | { |
| 5405 | struct msm_otg *motg = dev_get_drvdata(dev); |
| 5406 | |
| 5407 | dev_dbg(dev, "OTG PM suspend\n"); |
| 5408 | msm_otg_dbg_log_event(&motg->phy, "PM SUSPEND START", |
| 5409 | get_pm_runtime_counter(dev), |
| 5410 | atomic_read(&motg->pm_suspended)); |
| 5411 | |
| 5412 | /* flush any pending sm_work first */ |
| 5413 | flush_work(&motg->sm_work); |
| 5414 | if (!atomic_read(&motg->in_lpm)) { |
| 5415 | dev_err(dev, "Abort PM suspend!! (USB is outside LPM)\n"); |
| 5416 | return -EBUSY; |
| 5417 | } |
| 5418 | atomic_set(&motg->pm_suspended, 1); |
| 5419 | |
| 5420 | return 0; |
| 5421 | } |
| 5422 | |
| 5423 | static int msm_otg_pm_resume(struct device *dev) |
| 5424 | { |
| 5425 | int ret = 0; |
| 5426 | struct msm_otg *motg = dev_get_drvdata(dev); |
| 5427 | |
| 5428 | dev_dbg(dev, "OTG PM resume\n"); |
| 5429 | msm_otg_dbg_log_event(&motg->phy, "PM RESUME START", |
| 5430 | get_pm_runtime_counter(dev), pm_runtime_suspended(dev)); |
| 5431 | |
| 5432 | if (motg->resume_pending || motg->phy_irq_pending) { |
| 5433 | msm_otg_dbg_log_event(&motg->phy, "PM RESUME BY USB", |
| 5434 | motg->async_int, motg->resume_pending); |
| 5435 | /* sm work if pending will start in pm notify to exit LPM */ |
| 5436 | } |
| 5437 | |
| 5438 | return ret; |
| 5439 | } |
| 5440 | #endif |
| 5441 | |
| 5442 | #ifdef CONFIG_PM |
| 5443 | static const struct dev_pm_ops msm_otg_dev_pm_ops = { |
| 5444 | SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume) |
| 5445 | SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume, |
| 5446 | msm_otg_runtime_idle) |
| 5447 | }; |
| 5448 | #endif |
| 5449 | |
| 5450 | static const struct of_device_id msm_otg_dt_match[] = { |
| 5451 | { .compatible = "qcom,hsusb-otg", |
| 5452 | }, |
| 5453 | {} |
| 5454 | }; |
| 5455 | |
| 5456 | static struct platform_driver msm_otg_driver = { |
| 5457 | .probe = msm_otg_probe, |
| 5458 | .remove = msm_otg_remove, |
| 5459 | .shutdown = msm_otg_shutdown, |
| 5460 | .driver = { |
| 5461 | .name = DRIVER_NAME, |
| 5462 | .owner = THIS_MODULE, |
| 5463 | #ifdef CONFIG_PM |
| 5464 | .pm = &msm_otg_dev_pm_ops, |
| 5465 | #endif |
| 5466 | .of_match_table = msm_otg_dt_match, |
| 5467 | }, |
| 5468 | }; |
| 5469 | |
| 5470 | module_platform_driver(msm_otg_driver); |
| 5471 | |
| 5472 | MODULE_LICENSE("GPL v2"); |
| 5473 | MODULE_DESCRIPTION("MSM USB transceiver driver"); |